CN110400834B - A kind of reverse conduction IGBT without Snapback effect and its manufacturing method - Google Patents

Abstract

The invention relates to semiconductor technology, in particular to a reverse conduction IGBT without snapback effect and a manufacturing method thereof. The main scheme of the present invention is to improve the collector structure on the back of the IGBT, by optimizing the doping concentration and thickness of the P++ collector region and the N++ layer, the reverse blocking voltage of the device is reduced as much as possible, and the reverse blocking voltage is used in the reverse blocking mode. Avalanche breakdown effect and tunnel breakdown effect to achieve reverse conduction. Compared with the conventional reverse conduction IGBT, because there is no N+ short-circuit region, there is no transition from the MOSFET conduction mode to the IGBT conduction mode during forward conduction, so the new reverse conduction IGBT proposed by the present invention does not occur when forward conduction occurs. snapback phenomenon. Since the reverse conduction threshold voltage of the novel reverse conduction IGBT proposed by the present invention is larger than that of the conventional reverse conduction IGBT, it is suitable for situations such as a quasi-resonant circuit where the forward conduction time accounts for most of the reverse conduction time and the reverse conduction time is short. In addition, the novel reverse conduction IGBT proposed by the present invention also has the advantages of small forward conduction voltage drop, good soft recovery characteristics, and the like.

Description

A kind of reverse conduction IGBT without Snapback effect and its manufacturing method

technical field

The invention belongs to the technical field of power semiconductors, and relates to a reverse conduction IGBT without Snapback effect and a manufacturing method thereof.

Background technique

Insulated Gate Bipolar Transistor (IGBT) is a composite device developed in the 1980s. It uses MOSFET to drive bipolar transistors and has the common advantages of MOSFETs and BJTs - high input impedance and low on-state voltage drop, so it is widely used. Used in medium frequency and medium power electrical. However, since the IGBT does not have the capability of reverse conduction, in the application of its inductive load, a fast recovery diode (Fast Recovery Diode, FRD for short) needs to be connected in reverse parallel to provide freewheeling protection.

Because IGBT and FRD are easy to introduce parasitic inductance during welding, which will result in high application cost and poor reliability of actual IGBT, people integrate IGBT and FRD on the same chip to develop a reverse conducting insulated gate bipolar transistor (Reverse Conducting-IGBT, referred to as RC-IGBT), the collector short-circuit structure is adopted, and the N+ region and the P+ region arranged in parallel and alternately are formed by backside lithography. When positive bias is applied to the emitter and zero bias is applied to the collector, the PN junction formed by the P-type base region-N-drift region-N+ short-circuit region is in a forward biased state, enabling the device to achieve reverse conduction. However, this inherent structure makes the device change from MOSFET conduction mode to IGBT conduction mode during forward conduction, which is manifested as a snapback phenomenon (ie, voltage rebound phenomenon), which will aggravate the concentration of current and directly affect the reliability of the device. sex. In addition, since the FRD is only integrated in a part of the area, it is easy to cause uneven current distribution during reverse conduction, which will also affect the reliability of the device.

The reverse conduction function can also be realized by introducing a tunnel diode on the back of the conventional IGBT. When the emitter is positively biased and the collector is zero biased, the tunnel diode formed by the P++ collector/N++ region is in a reverse bias state. When the voltage increases, the energy band of the barrier region becomes more inclined. When the built-in electric field increases to a certain extent, a large number of electrons can directly pass through the forbidden band from the valence band and enter the conduction band to realize reverse conduction. However, the doping concentration of the P++/N++ region constituting the tunnel diode is very high, reaching 1×10 ²⁰ cm ^-3 to 1×10 ²¹ cm ^-3 . The process is very difficult and the IGBT exists in the forward conduction by the tunnel diode. The transition from the conduction mode to the conduction mode of the IGBT, therefore, the snapback phenomenon also occurs.

In the conventional field stop IGBT, due to the existence of the N+ field stop layer, in the forward blocking mode, the electric field rapidly drops to 0 in the N+ field stop layer, and the electric field presents a trapezoidal distribution, so the thickness of the drift region can be reduced to achieve The same level of pressure resistance. The doping concentration of the N+ field stop layer is usually 1×10 ¹⁵ cm ^-3 to 1×10 ¹⁶ cm ^-3 , and its reverse blocking voltage is usually tens of volts to several hundreds of volts, so the field stop IGBT does not have the reverse blocking voltage. The ability to guide.

SUMMARY OF THE INVENTION

The purpose of the present invention is to solve the problem of the snapback phenomenon existing in the forward conduction of the traditional RC-IGBT, and the situation that the reverse conduction characteristic of the device is not strictly required due to the asymmetry of the forward and reverse conduction time of the device, to propose a A new type of reverse conduction type IGBT without snapback effect and its manufacturing method.

For achieving the above object, the present invention adopts the following technical scheme:

A new type of reverse conduction IGBT without snapback effect, as shown in Figure 1, includes a collector structure, a drift region structure, a gate structure and an emitter structure;

The collector structure includes a P++ collector region 10 and a metallized collector 10 located on the lower surface of the P++ collector region 10;

The drift region structure includes an N++ layer 9 and an N+ field stop layer 8 arranged in parallel, and an N-drift region layer 1 located on the upper surface of the N++ layer 9 and the N+ field stop layer 8. The N++ layer 9 and the N+ field stop layer 8 are located at The upper surface of the P++ collector region 10;

The gate structure is a trench gate, embedded at both ends of the upper surface of the N-drift zone layer 1, and its structure includes a gate oxide layer 7 and a polysilicon gate electrode 6 located in the gate oxide layer 7;

The emitter structure is located between two trench gates, and its structure includes an N+ emitter region 5, a P-type base region 3, a P+ contact region 2 and a metallized emitter 4, and the P-type base region 3 is embedded in the N+ emitter. - The upper surface of the drift region layer 1, the N+ emitter region 5 is located on the upper layer of the P-type base region 3 and is in contact with the trench gate, the P+ contact region 2 is located in the P-type base region 3, and is located on both sides of the N+ emitter regions 5, both ends of P+ contact region 2 also extend to the lower surface of N+ emitter region 5; The upper surface of the metallized emitter 4 only covers part of the N+ emitter region 5 .

The main scheme of the present invention mainly relates to the back collector structure of the IGBT. By optimizing the doping concentration of the P++ collector region and the N++ layer, reverse conduction is realized by utilizing the avalanche breakdown of the P++ collector region and the N++ layer.

In the conventional reverse conduction IGBT, the schematic diagram of the structure is shown in Figure 2. The doping concentration of the N+ field stop layer 8 is about 1×10 ¹⁵ cm ^-3 to 1×10 ¹⁶ cm ^-3 , which is due to the doping concentration of the N+ field stop layer 8 When it is too large, the snapback voltage V _snapback of the device is very large, which will adversely affect the reliability of the device. When the conventional reverse conduction IGBT is conducting in the forward direction, due to the existence of the N+ short circuit region, the device first enters the MOSFET working mode. Voltage snapback.

The IGBT structure of introducing a tunnel diode on the back side to achieve reverse conduction is shown in Figure 3. In this structure, the doping concentration of the P++ collector 10 and the N++ layer 9 is 1×10 ²⁰ cm ^-3 to 1×10 ²¹ cm ^-3 , and Due to the characteristics of the tunnel diode, the IGBT transitions from the conduction mode of the tunnel diode to the conduction mode of the IGBT during forward conduction, so the snapback phenomenon also occurs.

The structure of a conventional FS-IGBT is shown in Figure 4, where the doping concentration of the N+ field stop layer is usually 1×10 ¹⁵ cm ^-3 to 1×10 ¹⁶ cm ^-3 , so the reverse blocking voltage of the device is usually several tens of volts ~ a few hundred volts, so the FS-IGBT does not have the ability to conduct in reverse.

The structure of the new type of reverse conduction IGBT proposed by the present invention is shown in Figure 1. The reverse conduction is realized by the avalanche breakdown of the P++ collector region and the N++ field stop layer. The doping concentration of the P++ collector region 9 and the N++ layer 9 is 1 ×10 ¹⁷ cm ^-3 ～1×10 ¹⁹ cm ^-3 , the doping concentration of the N+ field stop layer 8 is 1×10 ¹⁵ cm ^-3 ～1×10 ¹⁶ cm ^-3 , and the forward conduction characteristics are similar to those of conventional FS-IGBTs Similarly, there is no conduction mode transition, so no snapback phenomenon occurs when the novel reverse conducting IGBT proposed by the present invention is forwardly conducting.

The specific embodiment of the present invention is described by taking the design of a trench gate reverse-conducting IGBT half-cell with a withstand voltage of 1200V as an example. There are two manufacturing methods. The first manufacturing method is to form an N+ field stop layer and a N++ layer, the steps are as follows:

Step 1: Select an N-type silicon wafer with a doping concentration of 5e13cm ^-3 as the substrate silicon wafer, that is, the N-type semiconductor drift region 1 in the structure. First, phosphorus ions are implanted on the back of the N-drift region layer 1 and the junction is pushed. forming an N+ field stop layer 8;

The second step: the N++ layer 9 is formed by another phosphorus ion implantation and push junction;

The third step: grow 100 nm gate oxide on the upper surface of the N-drift zone layer 1 , that is, the gate oxide layer 7 , and then deposit polysilicon to form the polysilicon gate electrode 6 .

The fourth step: implanting P-type impurities in the N-drift region layer 1 and pushing the junction to form a P-type base region 3;

The fourth step: implanting N-type impurities in the P-type base region 3 to form an N+ emitter region 5;

Step 6: Implant P-type impurities in the P-type base region 3 and push the junction to form the P+ contact region 2;

The seventh step: depositing a BPSG insulating dielectric layer on the upper surface of the device, and etching the ohmic contact hole;

The eighth step: depositing metal on the upper surface of the N+ emitter region 5 to form a cathode metal 4, which only covers part of the N+ emitter region 5, and the cathode metal 4 simultaneously covers the P+ contact region 2;

The ninth step: deposit passivation layer;

The tenth step: implanting P-type impurities into the back surface and ion activation to form a P++ collector region 10;

The eleventh step: backside metallization, forming a metallized collector electrode 10 on the lower surface of the P++ collector region 10 .

The second manufacturing method is to perform impurity compensation to form an N+ field stop layer by implanting boron ions into part of the N++ layer and pushing the junction. The steps are as follows:

Step 1: Select an N-type silicon wafer with a doping concentration of 5e13cm ^-3 as the substrate silicon wafer, that is, the N-type semiconductor drift region 1 in the structure. First, phosphorus ions are implanted on the back of the N-drift region layer 1 and the junction is pushed. Form N++ layer 9;

The second step is to perform impurity compensation on the N++ layer to form the N+ layer 8 through one boron ion implantation and push junction;

The third step: grow 100 nm gate oxide on the upper surface of the N-drift zone layer 1 , that is, the gate oxide layer 7 , and then deposit polysilicon to form the polysilicon gate electrode 6 .

The fourth step: implanting P-type impurities in the N-drift region layer 1 and pushing the junction to form a P-type base region 3;

The fourth step: implanting N-type impurities in the P-type base region 3 to form an N+ emitter region 5;

Step 6: Implant P-type impurities in the P-type base region 3 and push the junction to form the P+ contact region 2;

The seventh step: depositing a BPSG insulating dielectric layer on the upper surface of the device, and etching the ohmic contact hole;

The eighth step: depositing metal on the upper surface of the N+ emitter region 5 to form a cathode metal 4, which only covers part of the N+ emitter region 5, and the cathode metal 4 simultaneously covers the P+ contact region 2;

The ninth step: deposit passivation layer;

The tenth step: implanting P-type impurities into the back surface and ion activation to form a P++ collector region 10;

The eleventh step: backside metallization, forming a metallized collector electrode 10 on the lower surface of the P++ collector region 10 .

The beneficial effect of the present invention is to propose a new type of reverse conduction type IGBT without snapback effect, which has the advantages of low cost, simple process, It has the advantages of good forward conduction characteristics and good soft recovery characteristics.

Description of drawings

FIG. 1 is a schematic diagram of the cell structure of the novel trench gate type reverse conduction IGBT of the present invention.

FIG. 2 is a schematic diagram of a cell structure of a conventional trench gate type reverse conduction IGBT.

FIG. 3 is a schematic diagram of the cell structure of an IGBT that realizes reverse conduction by introducing a tunnel diode on the back side.

FIG. 4 is a schematic diagram of the cell structure of a conventional FS-IGBT.

5 is the doping distribution near the collector of the novel trench gate type reverse conduction IGBT, the conventional FS-IGBT, and the IGBT using a tunnel diode to realize reverse conduction of the present invention.

FIG. 6 is the forward conduction characteristic curve of the novel reverse conduction IGBT of the present invention, the conventional reverse conduction IGBT and the IGBT introduced into the tunnel diode to realize reverse conduction.

FIG. 7 is the reverse conduction characteristic curve of the novel reverse conduction IGBT of the present invention, the conventional reverse conduction IGBT, the IGBT introduced into the tunnel diode to realize reverse conduction, and the conventional FS-IGBT.

8 is a schematic diagram of the electric field at the P++/N++ junction, the impact ionization rate and the tunnel generation rate when the novel reverse conduction IGBT of the present invention and the IGBT with the introduction of a tunnel diode to realize reverse conduction are reverse conduction.

FIG. 9 is a curve of the reverse blocking voltage of the novel reverse conduction IGBT of the present invention as a function of the concentration of the N+ layer.

Figure 10 is a double pulse circuit used to reflect the reverse recovery characteristics of the device

FIG. 11 is the reverse recovery characteristic curve of the conventional reverse conduction IGBT and the novel reverse conduction IGBT of the present invention.

Figure 12 is a single-ended quasi-resonant circuit used in an induction cooker.

FIG. 13 is a comparison diagram of current and voltage respectively applying the traditional reverse conduction IGBT and the novel reverse conduction IGBT of the present invention in a single-ended quasi-resonant circuit.

14 is a comparison diagram of the currents flowing through the resonant capacitor and the resonant inductance when the conventional reverse conduction IGBT and the novel reverse conduction IGBT of the present invention are respectively applied in the quasi-resonant circuit.

FIG. 15 is a process flow diagram of the first manufacturing method.

FIG. 16 is a process flow diagram of the second manufacturing method.

Detailed ways

The present invention is described in detail below in conjunction with the accompanying drawings:

A new type of reverse conduction IGBT without snapback effect proposed by the present invention has a structure as shown in Figure 1, including a collector structure, a drift region structure, an emitter structure and a gate structure; the collector structure includes a P++ collector region 10 and a metallized collector 10 located on the lower surface of the P++ collector region 10; the drift region structure includes an N++ layer 9, an N+ field stop layer 8 and an N-drift region layer located on the upper surface of the N++ layer 9 and the N+ field stop layer 8 1. The N++ layer 8 and the N+ field stop layer 8 are arranged side by side on the upper surface of the P++ collector region 10; the gate structure is a trench gate, embedded and arranged on the upper surface of the N-drift zone layer 1, and its structure includes gate oxide Layer 7 and polysilicon gate electrode 6 in gate oxide layer 7; the emitter structure is located between two trench gates, and its structure includes N+ emitter region 5, P-type base region 3, P+ contact region 2 and metallization Emitter 4, the P-type base region 3 is embedded in the upper surface of the N-drift region layer 1, the N+ emitter region 5 is located on the upper layer of the P-type base region 3, and the P+ contact region 2 is located in the P-type base region 3 , and arranged in parallel with the N+ emitter region 5; the junction depth of the P+ contact region 2 is greater than that of the N+ emitter region 5; the metallized emitter 4 is located on the upper surface of the N+ emitter region 5 and the P+ contact region 2, and the metallized emitter 4 is only Covers part of the N+ emission area 5.

The novel non-snapback effect reverse conduction IGBT proposed by the present invention works as follows:

During forward conduction, a positive bias is applied to the polysilicon gate electrode 6 in the cell as shown in FIG. 1, the electrons in the P-type base region 3 accumulate on the gate oxide side, and the channel is reversed to form a connection. The N-type electron channel of the N+ emitter region 5 and the N-drift region layer 1 . Positive voltage is applied to the metallized collector 10, and zero potential is applied to the metallized emitter 4. The electron current flows from the N+ emitter region 5 into the N-drift region layer 1 through the N-type electron channel, providing the base drive current for the PNP transistor composed of the P-type base region 3-N-drift region layer 1-P++ collector region 10 , after the PNP transistor is turned on, the P++ collector region 10 injects a large number of holes into the N-drift region layer 1 to form conductance modulation, and the IGBT conducts forward. Compared with the conventional reverse conduction IGBT (the structure is shown in Figure 2), the novel reverse conduction IGBT of the present invention has no N+ short-circuit region, so when the device is in forward conduction, there is no transition from the conduction mode of the MOSFET to the conduction mode of the IGBT. Therefore, the snapback phenomenon does not occur in the novel reverse conduction IGBT of the present invention. The forward conduction characteristic curves of the conventional reverse conduction IGBT, the novel reverse conduction IGBT of the present invention, and the IGBT using a tunnel diode to realize reverse conduction are shown in FIG. 6 .

During reverse conduction, zero potential is applied to the polysilicon gate electrode 6, positive voltage is applied to the metallized emitter 4, and zero potential is applied to the metallized collector 10, the device is in reverse blocking mode, and the emitter voltage is determined by the P++ collector region. The PN junction formed by 10 and N++ layer 9 supports, as the emitter-collector voltage increases, the depletion region at the PN junction formed by P++ collector region 10 and N++ layer 9 expands, and the electric field increases. When the emitter-collector voltage increases to the breakdown voltage of the PN junction, the PN junction breaks down, and a large number of electron-hole pairs are generated in the space charge region to realize reverse conduction. Conventional reverse conduction IGBT, the present invention The reverse conduction characteristic curves of the new type of reverse conduction IGBT, the reverse conduction IGBT and FS-IGBT using tunnel diodes are shown in Figure 7.

The specific embodiment of the present invention is described by taking the design of a trench gate reverse-conducting IGBT half-cell with a withstand voltage of 1200V as an example. There are two manufacturing methods. The first manufacturing method is to form an N+ field stop layer and a N++ layer, the steps are as follows:

Step 1: Select an N-type silicon wafer with a doping concentration of 5e13cm ^-3 as the substrate silicon wafer, that is, the N-type semiconductor drift region 1 in the structure. First, phosphorus ions are implanted on the back of the N-drift region layer 1 and the junction is pushed. forming an N+ field stop layer 8;

The second step: the N++ layer 9 is formed by another phosphorus ion implantation and push junction;

The third step: grow 100 nm gate oxide on the upper surface of the N-drift zone layer 1 , that is, the gate oxide layer 7 , and then deposit polysilicon to form the polysilicon gate electrode 6 .

The fourth step: implanting P-type impurities in the N-drift region layer 1 and pushing the junction to form a P-type base region 3;

The fourth step: implanting N-type impurities in the P-type base region 3 to form an N+ emitter region 5;

Step 6: Implant P-type impurities in the P-type base region 3 and push the junction to form the P+ contact region 2;

The seventh step: depositing a BPSG insulating dielectric layer on the upper surface of the device, and etching the ohmic contact hole;

The eighth step: depositing metal on the upper surface of the N+ emitter region 5 to form a cathode metal 4, which only covers part of the N+ emitter region 5, and the cathode metal 4 simultaneously covers the P+ contact region 2;

The ninth step: deposit passivation layer;

The tenth step: implanting P-type impurities into the back surface and ion activation to form a P++ collector region 10;

The eleventh step: backside metallization, forming a metallized collector electrode 10 on the lower surface of the P++ collector region 10 .

The second manufacturing method is to form an N+ field stop layer by performing impurity compensation on the N++ layer, and the steps are as follows:

Step 1: Select an N-type silicon wafer with a doping concentration of 5e13cm ^-3 as the substrate silicon wafer, that is, the N-type semiconductor drift region 1 in the structure. First, phosphorus ions are implanted on the back of the N-drift region layer 1 and the junction is pushed. Form N++ layer 9;

The second step is to perform impurity compensation on the N++ layer to form the N+ layer 8 through one boron ion implantation and push junction;

The third step: grow 100 nm gate oxide on the upper surface of the N-drift zone layer 1 , that is, the gate oxide layer 7 , and then deposit polysilicon to form the polysilicon gate electrode 6 .

The fourth step: implanting P-type impurities in the N-drift region layer 1 and pushing the junction to form a P-type base region 3;

The fourth step: implanting N-type impurities in the P-type base region 3 to form an N+ emitter region 5;

Step 6: Implant P-type impurities in the P-type base region 3 and push the junction to form the P+ contact region 2;

The seventh step: depositing a BPSG insulating dielectric layer on the upper surface of the device, and etching the ohmic contact hole;

The eighth step: depositing metal on the upper surface of the N+ emitter region 5 to form a cathode metal 4, which only covers part of the N+ emitter region 5, and the cathode metal 4 simultaneously covers the P+ contact region 2;

The ninth step: deposit passivation layer;

The tenth step: implanting P-type impurities into the back surface and ion activation to form a P++ collector region 10;

The eleventh step: backside metallization, forming a metallized collector electrode 10 on the lower surface of the P++ collector region 10 .

The simulation and comparison of the novel reverse conduction IGBT provided by the present invention and the conventional reverse conduction IGBT structure further confirms the superiority of the structure. The conventional reverse conduction IGBT structure is shown in Figure 2, and the new reverse conduction IGBT structure provided by the present invention is shown in Figure 1. The cell thickness of the device is 100um. In the conventional reverse conduction IGBT structure, the N+ short circuit region 10 and the P+ current collector The ratio of zone 9 is 1:5.

It can be seen from FIG. 6 that the forward conduction characteristics of the novel reverse conduction IGBT proposed by the present invention are better than that of the conventional reverse conduction IGBT and the IGBT using the tunnel diode to realize reverse conduction. The conventional reverse conduction IGBT has obvious snapback effect, and the snapback voltage V _SB = 8.8 V; The IGBT that uses the tunnel diode to realize the reverse conduction also shows the obvious snapback phenomenon; the novel reverse conduction IGBT proposed by the present invention does not have the phenomenon of voltage rebound. When the forward conduction current density is 100A/ ^cm2 , the forward conduction voltage drop of the conventional reverse conduction IGBT is about 1.19V, and the forward conduction voltage drop of the reverse conduction IGBT proposed by the present invention is about 1.05V, which is reduced by 11.8%, This is due to the larger effective collector area in the present invention.

It can be seen from FIG. 7 that when Vce is -5V, the novel reverse conduction IGBT device of the present invention realizes reverse conduction, that is, the PN junction formed by the P++ collector region 10 and the N++ layer 9 breaks down, generating a large number of electron-hole pairs. , since both the P++ collector region 10 and the N++ layer 9 are heavily doped, the peak electric field Emax during breakdown is about 1.25e6V/cm. It can be seen from Figure 8 that the PN junction breakdown includes both avalanche breakdown and tunneling. breakdown, but mainly avalanche breakdown. From the mechanism of junction breakdown, it can be known that reverse conduction can be achieved as long as Vce is maintained at -5V. In the IGBT that uses a tunnel diode to achieve reverse conduction, tunnel breakdown is the main method. Because the barrier region is very thin, even if the electric field is strong, the acceleration of the carriers in the barrier region cannot reach the kinetic energy necessary for the multiplication effect. , the avalanche breakdown cannot occur. For conventional FS-IGBT, its reverse blocking voltage reaches about 300V, so it does not have the ability to conduct reverse conduction.

Figure 9 shows the curve of the reverse blocking voltage as a function of the doping concentration of the N+ field stop layer in the novel reverse conduction IGBT proposed by the present invention. The doping concentration of the N+ field stop layer should be increased to reduce the reverse blocking voltage of the device. , resulting in avalanche breakdown of the device at a lower emitter voltage. Therefore, in the novel reverse conduction IGBT proposed by the present invention, the doping concentration of the P++ collector region 10 and the N++ layer 9 should reach 1×10 ¹⁷ cm ^-3 to 1×10 ¹⁹ cm ^-3 , which is mainly realized by the avalanche breakdown effect. Reverse conduction.

The double-pulse circuit shown in Figure 10 can be used to reflect the reverse recovery characteristics of the device IGBT1, that is, the process of extracting excess carriers in the drift region when IGBT1 transitions from reverse conduction mode to forward blocking mode. The reverse current drop rate [dJ/dt] _R creates a large potential in the circuit inductance, which is superimposed on the supply voltage, creating a voltage overshoot phenomenon. This phenomenon can be measured by the softness factor S. The larger S is, the smaller the reverse current drop rate [dJ/dt] _R is. When S>0.8, it can be judged that the device has the characteristics of soft recovery. It can be seen from FIG. 11 that the softness factor S of the novel reverse conduction IGBT proposed by the present invention is about 10, and has good soft recovery characteristics.

Figure 12 is a single-ended quasi-resonant circuit commonly used in induction cookers. By controlling the turn-on and turn-off of IGBTs in the circuit, periodic current flows through the inductor to form an alternating magnetic field. Fig. 13 is the time-dependent curve of the collector current Ic and the collector-emitter voltage Vce of the IGBT obtained by applying the conventional reverse-conducting IGBT and the novel reverse-conducting IGBT proposed by the present invention in the quasi-resonant circuit shown in Fig. 12, respectively, It can be seen from the comparison that the novel reverse-conducting IGBT proposed by the present invention can replace the application of the conventional reverse-conducting IGBT in the quasi-resonant circuit, and both can generate a periodically changing current on the resonant inductance Lr. It can be seen from Figure 14 that the forward conduction time in one cycle accounts for 46.5%, and the reverse conduction time only accounts for about 13%. Therefore, the energy consumption of the device in one cycle is mainly determined by the two processes of forward conduction and shutdown. The energy consumption generated during the conduction process is very small, so although the threshold voltage of the reverse conduction of the new reverse conduction IGBT proposed by the present invention is relatively large, due to the short reverse conduction time and the small reverse conduction current, it will not cause excessive conduction. large energy consumption.

To sum up, compared with the conventional reverse conduction IGBT, the new reverse conduction IGBT proposed by the present invention will not occur the Snapback phenomenon when conducting forward conduction, and has better forward conduction characteristics, although the threshold voltage of reverse conduction is larger. , but in applications such as quasi-resonant circuits where the forward conduction time is the majority, it will not bring much additional energy consumption. In addition, the novel reverse conduction IGBT proposed by the present invention also has the characteristics of better soft recovery characteristics.

Claims (4)

1. A reverse conducting IGBT without Snapback effect, comprising a collector structure, a drift region structure, a gate structure and an emitter structure; The collector structure comprises a P++ collector region (10) and a metallized collector (11) located on the lower surface of the P++ collector region (10); The drift region structure comprises an N++ layer (9) and an N+ field stop layer (8) arranged in parallel, and an N-drift region layer (1) located on the upper surface of the N++ layer (9) and the N+ field stop layer (8), The N++ layer (9) and the N+ field stop layer (8) are located on the upper surface of the P++ collector region (10); The gate structure is a trench gate, embedded at both ends of the upper surface of the N-drift zone layer (1), and its structure includes a gate oxide layer (7) and a polysilicon gate electrode (6) located in the gate oxide layer (7). ); The emitter structure is located between two trench gates, and its structure includes an N+ emitter region (5), a P-type base region (3), a P+ contact region (2) and a metallized emitter (4). The type base region (3) is embedded and arranged on the upper surface of the N-drift region layer (1), the N+ emitter region (5) is located on the upper layer of the P-type base region (3) and is in contact with the trench gate, and the P+ contact region ( 2) It is located in the P-type base region (3) and between the N+ emitter regions (5) on both sides, and both ends of the P+ contact region (2) also extend to the lower surface of the N+ emitter region (5); the P+ contact region ( 2) The junction depth is greater than that of the N+ emitter region (5); the metallized emitter (4) is located on the upper surface of the N+ emitter region (5) and the P+ contact region (2), and the metallized emitter (4) only covers part of it N+ emission region (5). 2. a kind of non-Snapback effect reverse conduction IGBT according to claim 1, is characterized in that, utilizes the avalanche breakdown of P++ collector region (10) and N++ layer (9) to realize reverse conduction, P++ collector region ( 10) The concentration is 1×10 ¹⁷ cm ^-3 ～1×10 ¹⁹ cm ^-3 , the junction depth is 0.5～1um; the doping concentration of the N+ field stop layer (8) is 1×10 ¹⁵ cm ^-3 ～1×10 ¹⁶ cm ^-3 , the junction depth is 2～5um; the doping concentration of the N++ layer (9) is 1×10 ¹⁷ cm ^-3 ～1×10 ¹⁹ cm ^-3 , the junction depth is the same as that of the N+ field stop layer (8), 2 to 5um. 3. the manufacturing method of a kind of non-Snapback effect reverse conduction IGBT according to claim 1, is characterized in that, comprises the following steps: The first step: select an N-type silicon wafer with a doping concentration of 5e13cm ^-3 as the substrate silicon wafer, that is, the N-drift zone layer (1) in the structure, first pass phosphorus ions on the back of the N-drift zone layer (1). implanting and pushing the junction to form an N+ field stop layer (8); The second step: an N++ layer (9) is formed by another phosphorus ion implantation and push junction; The third step: growing 100nm gate oxide on the upper surface of the N-drift zone layer (1), that is, the gate oxide layer (7), and then depositing polysilicon to form a polysilicon gate electrode (6); The fourth step: implanting P-type impurities in the N-drift region layer (1) and pushing the junction to form a P-type base region (3); The fourth step: injecting N-type impurities into the P-type base region (3) to form an N+ emitter region (5); The sixth step: implanting P-type impurities in the P-type base region (3) and pushing the junction to form a P+ contact region (2); The seventh step: depositing a BPSG insulating dielectric layer on the upper surface of the device, and etching the ohmic contact hole; The eighth step: depositing metal on the upper surface of the N+ emitter region (5) to form a metallized emitter (4), covering only part of the N+ emitter region (5), while the metallized emitter (4) covers the P+ contact region at the same time (2) on; The ninth step: deposit passivation layer; The tenth step: injecting P-type impurities into the back surface and performing ion activation to form a P++ collector region (10); The eleventh step: backside metallization, forming a metallized collector electrode (11) on the lower surface of the P++ collector region (10). 4. a kind of manufacturing method of no Snapback effect reverse conduction IGBT according to claim 1, is characterized in that, comprises the following steps: The first step: select an N-type silicon wafer with a doping concentration of 5e13cm ^-3 as the substrate silicon wafer, that is, the N-drift zone layer (1) in the structure, first pass phosphorus ions on the back of the N-drift zone layer (1). Implant and push the junction to form the N++ layer (9); The second step: performing impurity compensation on the N++ layer to form an N+ field stop layer (8) by implanting boron ions once and pushing the junction; The third step: growing 100nm gate oxide on the upper surface of the N-drift zone layer (1), that is, the gate oxide layer (7), and then depositing polysilicon to form a polysilicon gate electrode (6); The fourth step: implanting P-type impurities in the N-drift region layer (1) and pushing the junction to form a P-type base region (3); The fourth step: injecting N-type impurities into the P-type base region (3) to form an N+ emitter region (5); The sixth step: implanting P-type impurities in the P-type base region (3) and pushing the junction to form a P+ contact region (2); The seventh step: depositing a BPSG insulating dielectric layer on the upper surface of the device, and etching the ohmic contact hole; The eighth step: depositing metal on the upper surface of the N+ emitter region (5) to form a metallized emitter (4), covering only part of the N+ emitter region (5), while the metallized emitter (4) covers the P+ contact region at the same time (2) on; The ninth step: deposit passivation layer; The tenth step: injecting P-type impurities into the back surface and performing ion activation to form a P++ collector region (10); The eleventh step: backside metallization, forming a metallized collector electrode (11) on the lower surface of the P++ collector region (10).

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