CN108807296A - Top has the chip-packaging structure and its manufacturing method of guide-joining plate - Google Patents
Top has the chip-packaging structure and its manufacturing method of guide-joining plate Download PDFInfo
- Publication number
- CN108807296A CN108807296A CN201710300747.2A CN201710300747A CN108807296A CN 108807296 A CN108807296 A CN 108807296A CN 201710300747 A CN201710300747 A CN 201710300747A CN 108807296 A CN108807296 A CN 108807296A
- Authority
- CN
- China
- Prior art keywords
- chip
- guide
- joining plate
- packaging structure
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
- G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
- G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
- G06V40/12—Fingerprints or palmprints
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Human Computer Interaction (AREA)
- Multimedia (AREA)
- Theoretical Computer Science (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
A kind of chip-packaging structure and its manufacturing method of the top with guide-joining plate, the chip-packaging structure include：One substrate；There are multiple weld pads on the substrate；An at least chip, lower surface are placed on the substrate；There are multiple weld pads on each chip, multiple weld pads on the substrate can be connected by conducting wire；An at least guide-joining plate, the guide-joining plate are a laminar board-like material；Each guide-joining plate is pasted on the upper surface of corresponding chip；Wherein, the material of the guide-joining plate is different from subsequently by the material of the structure of encapsulation.
Description
Technical field
The present invention relates to chip-packaging structure, especially a kind of top has chip-packaging structure and its manufacture of guide-joining plate
Method.
Background technology
In semiconductor technology, some kinds of chip due to must photosensitive or electromagnetic induction it requires above chip
Encapsulating structure must be made comparable thin, so that the chip in lower section can photosensitive or electromagnetic induction.Such as identification of fingerprint core
Piece is formed by image chip by CMOS.Identification of fingerprint chip is by fingerprint pressing above chip, and by photosensitive or electric
Magnetic induction and allow chip sense top fingerprint.CMOS be formed by image chip can apply in identification of fingerprint and
Image is taken in, in order to generate good image effect, so the encapsulating structure of necessary top is comparable thin.For example it requires
Only 150 to 200 μm of thickness being packaged into above chip.And to manufacture so thin encapsulating structure suitable for semiconductor technology now
Difficulty, and cost is also high.
Therefore the present invention wishes to propose the chip-packaging structure and its manufacturing method that a kind of brand-new top has guide-joining plate, with
Solve the defect in the above-mentioned prior art.
Invention content
So the purpose of the present invention is to solve the problem in the above-mentioned prior art, a kind of top tool is proposed in the present invention
There are the chip-packaging structure and its manufacturing method of guide-joining plate, the top of chip is attached to using guide-joining plate, it can be by guide-joining plate
That does is unusual thin, can be thinner than traditional encapsulation technology between 60 μm to 100 μm with current technology, and makes
Technology is also quite simple.On the other hand required guide-joining plate can be selected to adapt to the needs of used chip, and generated
Better effect.Especially identification of fingerprint and image chip are even more the needs for having this aspect.If with traditional packaged type,
Must by above chip the encapsulated layer of induction zone be made comparable thin, but it is extremely difficult in manufacturing technology, also, its feel
The ability answered is also than directly selecting inductive material appropriate poor.
In order to achieve the above objectives, propose that a kind of top has the chip-packaging structure of guide-joining plate in the present invention, including：One base
Plate；There are multiple weld pads on the substrate；An at least chip, lower surface are placed on the substrate；There are multiple weld pads on each chip, can lead to
It crosses conducting wire and connects multiple weld pads on the substrate；An at least guide-joining plate, the guide-joining plate are a laminar board-like material；Respectively connect
Piece is pasted on the upper surface of corresponding chip；Wherein, the material of the guide-joining plate is different from the material of subsequent encapsulating structure.
Wherein, the utility model chip-packaging structure further includes：
One encapsulating structure for encapsulating an at least chip and the substrate, and allows this at least a guide-joining plate is exposed to outer
Portion.
Also propose that a kind of manufacture top has the method for chip-packaging structure of guide-joining plate in the present invention, wherein in chip
Also not from whole wafer separately and before forming separate chip, a large amount of guide-joining plate is attached to the upper of the wafer simultaneously
Side, position correspond to the top of each chip after cutting；The semiconductor of subsequent cutting, separation, encapsulation etc. is carried out again
Technique；Wherein, which is a laminar board-like material；Each guide-joining plate is pasted on the upper surface of corresponding chip；Its
In, the material of the guide-joining plate is different from the material of subsequent encapsulating structure；And wherein, when encapsulation, the guide-joining plate can it is exposed extremely
It is external.
Wherein, the material of the guide-joining plate is the magnetically or optically transparent material of electricity.
Wherein, which is identification of fingerprint chip.
Wherein, which is CMOS chip, is used for image sensing or identification of fingerprint.
Beneficial effects of the present invention are：Guide-joining plate can be done is unusual thin, can be to 60 μm extremely with current technology
It is thinner than traditional encapsulation technology between 100 μm, and manufacturing technology is also quite simple.
Description of the drawings
The component combination diagram of Fig. 1 display present invention；
Fig. 2 shows the schematic cross-section of Fig. 1；
The another of component combination diagram of Fig. 3 display present invention illustrates example；
Fig. 4 shows the schematic cross-section of Fig. 3；
Wafer is placed in the schematic diagram of gluing bottom plate in Fig. 5 display present invention process；
Wafer cuts into the schematic diagram of multiple chips in Fig. 6 display present invention process；
Fig. 7 shows the schematic diagram of guide-joining plate and chip in present invention process；
Fig. 8 shows the schematic diagram that guide-joining plate is combined with chip in present invention process；
Fig. 9 shows the step flow chart of present invention process.
Reference sign
10 substrates
20 chips
30 guide-joining plates
40 encapsulating structures
50 wafers
70 gluing bottom plates
80 conducting wires
100 weld pads
200 weld pads.
Specific implementation mode
The now careful just structure composition of the present invention and the effect of can be generated and advantage, coordinates attached drawing, and according to the present invention one
Detailed description are as follows for preferred embodiment.
It please refers to Fig.1 to shown in Fig. 4, showing that the top of the present invention has the chip-packaging structure of guide-joining plate, including it is following
Component：
One substrate 10 has multiple weld pads 100 on the substrate 10.
An at least chip 20, lower surface are placed on the substrate 10, there is multiple weld pads 200 on each chip 20, can be by leading
Line 80 connects multiple weld pads 100 on the substrate 10.
An at least guide-joining plate 30, the guide-joining plate 30 are a laminar board-like material, and each guide-joining plate 30 is pasted corresponding
The upper surface of chip 20.
One encapsulating structure 40 for encapsulating an at least chip 20 and the substrate 10, and makes an at least guide-joining plate 30
It can be exposed to external.
Wherein, the material of the guide-joining plate 30 is different from the material of the encapsulating structure 40.
In one embodiment of this invention, the material of the guide-joining plate 30 is the transparent material of electromagnetism, such as plastic material
(PI, PET) or glass etc..The chip 20 can be identification of fingerprint chip.Therefore when finger is placed in the top of the guide-joining plate 30, hand
The fingerprint of finger can reflect the electromagnetic wave that the chip 20 is emitted, and so that the chip 20 receives the signal of fingerprint, to carry out
Relevant application, as fingerprint stores or recognizes.
In another embodiment of the invention, the material of the guide-joining plate 30 is the transparent material of light.The chip 20 can be
CMOS chip can be used as image sensing and be used, such as photography or identification of fingerprint.When for example as identification of fingerprint, when finger is placed in this
When the top of guide-joining plate 30, fingerprint can reflect the light wave of the chip 20, and so that the chip 20 receives the signal of fingerprint, with
Relevant application is carried out, as fingerprint stores or recognizes.
When CMOS chip use is in photography, it is necessary to can effectively receive external light wave, can be selected in the present invention saturating
The guide-joining plate 30 of bright material, so that external light almost can completely penetrate the guide-joining plate 30 to obtain good effect
Fruit.
Show there was only the structure of one chip 20 on the substrate 10 in Fig. 1 and 2.But the present invention can also be used multiple
The case where chip 20, there is the structure of multiple chips 20 as shown in Fig. 3 and 4 on the substrate 10.But it weld pad shown in attached drawing and leads
The structure that the link position and connection type of line are not intended to restrict the invention, other link positions and connection type are at this
Within the scope of invention.
In the present invention, it is in technologic one big advantage：It can be in wafer 50 not yet by each chip 20 from the wafer
50 when being individually separated into individual independent cores 20, is once placed directly within a large amount of guide-joining plate 30 respectively using the mode of unified technique
The top of corresponding chip 20, then makes encapsulating structure 40, therefore the comparable convenience in technique again.
In chip technology, it is necessary to a wafer 5 is combined with substrate, is then cut again and forms numerous chips,
These chips are packaged respectively again.And the present invention can not individually not separated from the wafer 50 also in technique in each chip 20
When forming individual independent chips 20, i.e., a large amount of guide-joining plate 30 is once attached on the wafer 50, and saves integrated artistic.
It is now described as follows as an example, an embodiment of technique, in the present embodiment, and upper in Fig. 5 to Fig. 8 display present invention
The identical component of one embodiment indicates that function is identical with identical reference numeral, so being no longer described in detail.As shown in figure 9,
Include the following steps in the present embodiment：
One wafer 50 is placed on a gluing bottom plate 70 (the blue tape being such as commonly called as) (step 100), as shown in Figure 5.
The wafer 50 is cut into multiple chips 20, but these chips 20 are still pasted on the gluing bottom plate 70, and it is big
Integrality (the step 110) of maintenance 50 shape of wafer is caused, as shown in Figure 6.
Multiple guide-joining plates 30 are placed on multiple chip 20, and generally maintain the relationship of alignment.And by each guide-joining plate
30 paste (step 120) on corresponding chip 20, as shown in Figures 7 and 8.
The gluing bottom plate 70 is torn, then multiple chip 20 is placed on substrate 10 and enters separation, welding, conducting wire connection
And program (the step 130) of encapsulation.This is general existing canned program, and the present invention will not be described again.
It is that, because being attached to the top of chip using guide-joining plate, can will connect using the advantages of packaging method of the present invention
Piece is done unusual thin, can be thinner than traditional encapsulation technology between 60 μm to 100 μm with current technology, and is made
It is also quite simple to make technology.On the other hand required guide-joining plate can be selected to adapt to the needs of used chip, and produced
Raw better effect.Especially identification of fingerprint and image chip are even more the needs for having this aspect.If with traditional encapsulation side
Formula, it is necessary to by above chip the encapsulated layer of induction zone be made comparable thin, but it is extremely difficult in manufacturing technology, and its
The ability of induction is also than directly selecting inductive material appropriate poor.
In conclusion the design of consideration of hommization of the present invention, quite meets actual demand.Its specific improvement prior art
Disadvantage obviously has the advantages that breakthrough progress compared to the prior art, the enhancement having effects that really, and is not easy to reach.
The present invention be not disclosed in domestic and external document in the market, had met patent statute.
Above-mentioned detailed description is illustrating for a possible embodiments of the invention, but the embodiment is not to limit
The scope of patent protection of the present invention is made, it is all without departing from equivalence enforcement made by technical spirit of the present invention or change, it should all be included in
In the scope of the claims of the present invention.
Claims (10)
1. a kind of top has the chip-packaging structure of guide-joining plate, which is characterized in that including：
One substrate；There are multiple weld pads on the substrate；
An at least chip, lower surface are placed on the substrate；There are multiple weld pads on each chip, can be connected by conducting wire on the substrate
Multiple weld pads；
An at least guide-joining plate, the guide-joining plate are a laminar board-like material；Each guide-joining plate pastes the upper table in corresponding chip
On face；
Wherein, the material of the guide-joining plate is different from the material of subsequent encapsulating structure.
2. top as described in claim 1 has the chip-packaging structure of guide-joining plate, which is characterized in that further include：
One encapsulating structure for encapsulating an at least chip and the substrate, and allows this at least a guide-joining plate is exposed to outer
Portion.
3. top as described in claim 1 has the chip-packaging structure of guide-joining plate, which is characterized in that the material of the guide-joining plate
For the transparent material of electromagnetism.
4. top as described in claim 1 has the chip-packaging structure of guide-joining plate, which is characterized in that the chip is distinguished for fingerprint
Know chip.
5. top as described in claim 1 has the chip-packaging structure of guide-joining plate, which is characterized in that the material of the guide-joining plate
For the transparent material of light.
6. top as described in claim 1 has the chip-packaging structure of guide-joining plate, which is characterized in that the chip is CMOS cores
Piece is used for image sensing or identification of fingerprint.
7. having the method for the chip-packaging structure of guide-joining plate above a kind of manufacture, which is characterized in that in chip also not from entire
On wafer separately and before forming separate chip, a large amount of guide-joining plate is attached to the top of the wafer, position simultaneously
Correspond to the top of each chip after cutting；The semiconductor technology of subsequent cutting, separation, encapsulation etc. is carried out again；
Wherein, which is a laminar board-like material；Each guide-joining plate is pasted in the upper surface of corresponding chip；
Wherein, the material of the guide-joining plate is different from the material of subsequent encapsulating structure；And
Wherein, when encapsulation, which can be exposed to external.
8. the method for claim 7, which is characterized in that the material of the guide-joining plate is the magnetically or optically transparent material of electricity.
9. the method for claim 7, which is characterized in that the chip is identification of fingerprint chip.
10. the method for claim 7, which is characterized in that the chip is CMOS chip, is distinguished for image sensing or fingerprint
Know.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710300747.2A CN108807296A (en) | 2017-04-28 | 2017-04-28 | Top has the chip-packaging structure and its manufacturing method of guide-joining plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710300747.2A CN108807296A (en) | 2017-04-28 | 2017-04-28 | Top has the chip-packaging structure and its manufacturing method of guide-joining plate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108807296A true CN108807296A (en) | 2018-11-13 |
Family
ID=64054213
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710300747.2A Withdrawn CN108807296A (en) | 2017-04-28 | 2017-04-28 | Top has the chip-packaging structure and its manufacturing method of guide-joining plate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108807296A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW506098B (en) * | 2001-10-19 | 2002-10-11 | Taiwan Ic Packaging Corp | Packaging method and structure of photodetective semiconductor element |
| TW549600U (en) * | 2002-10-31 | 2003-08-21 | Taiwan Ic Packaging Corp | Chip scale packaged image sensor |
| CN101494230A (en) * | 2008-01-21 | 2009-07-29 | 矽品精密工业股份有限公司 | Sensing type semiconductor package and manufacturing method thereof |
| CN206711888U (en) * | 2017-04-28 | 2017-12-05 | 叶秀慧 | Top has the chip-packaging structure of guide-joining plate |
-
2017
- 2017-04-28 CN CN201710300747.2A patent/CN108807296A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW506098B (en) * | 2001-10-19 | 2002-10-11 | Taiwan Ic Packaging Corp | Packaging method and structure of photodetective semiconductor element |
| TW549600U (en) * | 2002-10-31 | 2003-08-21 | Taiwan Ic Packaging Corp | Chip scale packaged image sensor |
| CN101494230A (en) * | 2008-01-21 | 2009-07-29 | 矽品精密工业股份有限公司 | Sensing type semiconductor package and manufacturing method thereof |
| CN206711888U (en) * | 2017-04-28 | 2017-12-05 | 叶秀慧 | Top has the chip-packaging structure of guide-joining plate |
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| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20181113 |
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| WW01 | Invention patent application withdrawn after publication |