CN206711888U - Top has the chip-packaging structure of guide-joining plate - Google Patents

Abstract

A kind of top has the chip-packaging structure of guide-joining plate, and the chip-packaging structure includes：One substrate；There are multiple weld pads on the substrate；An at least chip, its lower surface are placed on the substrate；There are multiple weld pads on each chip, multiple weld pads on the substrate can be connected by wire；An at least guide-joining plate, the guide-joining plate are a laminar board-like material；Each guide-joining plate is pasted on the upper surface of corresponding chip；Wherein, the material of the guide-joining plate is different from subsequently by the material of the structure of encapsulation.

Description

Chip package structure with bonding pads on top

technical field

The utility model relates to a chip packaging structure, in particular to a chip packaging structure with a conductive piece on the top.

Background technique

In the semiconductor process, some types of chips must be sensitive to light or electromagnetic induction, so the packaging structure above the chip must be made quite thin, so that the chip below can be sensitive to light or electromagnetic induction. For example, a fingerprint recognition chip or an image chip formed by CMOS. The fingerprint identification chip is to press the fingerprint on the chip, and through photosensitive or electromagnetic induction, the chip can sense the fingerprint on the top. The image chip formed by CMOS can be used in fingerprint recognition and image capture. In order to produce a good image effect, the upper packaging structure must be quite thin. For example, the thickness required to be packaged above the chip is only 150 to 200 μm. However, it is quite difficult and expensive to manufacture such a thin packaging structure with current semiconductor processes.

Therefore, the utility model hopes to provide a brand-new chip packaging structure with conductive pads on the top and its manufacturing method, so as to solve the above-mentioned defects in the prior art.

Utility model content

Therefore, the purpose of this utility model is to solve the above-mentioned problems in the prior art. In this utility model, a chip packaging structure with a conductive piece on the top and its manufacturing method are proposed. The conductive piece is attached to the top of the chip, The conductive sheet can be made very thin, with the current technology can be between 60 μm and 100 μm, which is thinner than the traditional packaging technology, and the manufacturing technology is also quite simple. On the other hand, you can choose the required lead strips to meet the needs of the chip used, and produce better results. In particular, fingerprint identification and image chips have this need. If the traditional packaging method is used, the packaging layer in the sensing area above the chip must be made quite thin, but it is quite difficult in manufacturing technology, and its sensing ability is also worse than directly selecting appropriate sensing materials.

In order to achieve the above object, the utility model proposes a chip packaging structure with a conductive sheet above, including: a substrate; a plurality of solder pads on the substrate; at least one chip, the lower surface of which is placed on the substrate; There are multiple soldering pads on the chip, which can be connected to multiple soldering pads on the substrate through wires; at least one conductive piece, the conductive piece is a thin plate-shaped material; each conductive piece is pasted on the corresponding chip on the upper surface; wherein, the material of the lead sheet is different from the material of the subsequent packaging structure.

Wherein, the utility model chip packaging structure also includes:

A packaging structure is used for packaging the at least one chip and the substrate, so that the at least one conductive piece can be exposed to the outside.

Wherein, the material of the conductive sheet is an electromagnetic or optically permeable material.

Wherein, the chip is a fingerprint recognition chip.

Wherein, the chip is a CMOS chip for image sensing or fingerprint recognition.

The beneficial effects of the utility model are: the conductive sheet can be made very thin, which can be between 60 μm and 100 μm with the current technology, which is thinner than the traditional packaging technology, and the manufacturing technology is also quite simple.

Description of drawings

Fig. 1 shows the assembly schematic diagram of the utility model;

Figure 2 shows a schematic cross-sectional view of Figure 1;

Fig. 3 shows another illustrative example of the assembly schematic diagram of the present utility model;

Figure 4 shows a schematic cross-sectional view of Figure 3;

Fig. 5 shows the schematic diagram of the wafer being placed on the adhesive base plate in the process of the present invention;

Fig. 6 shows the schematic diagram that wafer is cut into a plurality of chips in the process of the present invention;

Fig. 7 shows the schematic diagram of lead piece and chip in the utility model technology;

Fig. 8 shows the schematic diagram of the combination of the lead sheet and the chip in the process of the present invention;

Figure 9 shows a flow chart of steps of the process of the present invention.

Explanation of reference signs

10 Substrate

20 chips

30 lead strip

40 package structure

50 wafers

70 Adhesive backplane

80 wire

100 pads

200 solder pads.

detailed description

With regard to the structural composition and the functions and advantages of the utility model, a preferred embodiment of the utility model is described in detail as follows with reference to the accompanying drawings.

Please refer to Fig. 1 to Fig. 4, which shows the chip packaging structure with conductive pads above the utility model, including the following components:

A substrate 10 with a plurality of pads 100 on the substrate 10 .

At least one chip 20 , the lower surface of which is placed on the substrate 10 , each chip 20 has a plurality of bonding pads 200 , which can be connected to the plurality of bonding pads 100 on the substrate 10 through wires 80 .

At least one conductive strip 30 , the conductive strip 30 is a sheet-shaped plate material, and each conductive strip 30 is pasted on the upper surface of the corresponding chip 20 .

A packaging structure 40 is used to package the at least one chip 20 and the substrate 10 so that the at least one conductive pad 30 can be exposed to the outside.

Wherein, the material of the bonding pad 30 is different from the material of the packaging structure 40 .

In an embodiment of the present invention, the material of the conductive strip 30 is an electromagnetically permeable material, such as plastic material (PI, PET) or glass. The chip 20 can be a fingerprint recognition chip. Therefore, when a finger is placed on the contact plate 30 , the fingerprint of the finger can reflect the electromagnetic wave emitted by the chip 20 , so that the chip 20 can receive the signal of the fingerprint for related applications, such as fingerprint storage or recognition.

In another embodiment of the present invention, the material of the conductive sheet 30 is a light-permeable material. The chip 20 can be a CMOS chip and can be used for image sensing, such as photography or fingerprint recognition. For example, when used as a fingerprint identification, when the finger is placed on the top of the conductive sheet 30, the fingerprint can reflect the light wave of the chip 20, so that the chip 20 can receive the signal of the fingerprint for related applications, such as fingerprint storage or identification .

When the CMOS chip is used in photography, it must be able to effectively receive external light waves. In the utility model, the conductive sheet 30 of transparent material can be selected so that the external light can penetrate the conductive sheet 30 almost completely. get good results.

1 and 2 show the structure of only a single chip 20 on the substrate 10 . However, the present invention can also be used in the case of multiple chips 20 , as shown in FIGS. 3 and 4 , there are multiple chips 20 on the substrate 10 . However, the connection positions and connection methods of the pads and wires shown in the drawings are not intended to limit the structure of the present invention, and other connection positions and connection methods are within the scope of the present invention.

In the present utility model, a great advantage in technology is: when the wafer 50 has not separately separated each chip 20 from the wafer 50 into individual independent cores 20, a large amount of lead-in chips can be processed at one time by using a unified process. The tabs 30 are placed directly above the corresponding chips 20, and then the packaging structure 40 is fabricated, so the process is quite convenient.

In the chip process, a wafer 5 must be combined with a substrate, and then cut to form many chips, and then these chips are packaged separately. And the utility model can be about a large amount of conductive strips 30 once attached on this wafer 50 when each chip 20 has not been separately separated from this wafer 50 to form individual independent chips 20 in technology, and saves overall process .

Now give an example to illustrate as follows, Fig. 5 to Fig. 8 show an embodiment of technology in the present utility model, in this embodiment, with the assembly identical reference numeral of last embodiment, its function is identical, so does not Let me go into more detail. As shown in Figure 9, the present embodiment includes the following steps:

Place a wafer 50 on an adhesive substrate 70 (such as commonly known as blue tape) (step 100 ), as shown in FIG. 5 .

The wafer 50 is diced into a plurality of chips 20 , but these chips 20 are still stuck on the adhesive backplane 70 to substantially maintain the integrity of the shape of the wafer 50 (step 110 ), as shown in FIG. 6 .

A plurality of bonding pads 30 are placed on the plurality of chips 20 to substantially maintain an aligned relationship. And paste each conductive piece 30 on the corresponding chip 20 (step 120 ), as shown in FIG. 7 and FIG. 8 .

The adhesive bottom plate 70 is torn off, and then the plurality of chips 20 are placed on the substrate 10 to enter the process of separation, soldering, wire connection and packaging (step 130 ). This is a general existing packaging program, and will not be described in the present invention.

The advantage of applying the packaging method of the utility model is that, because the conductive sheet is attached on the top of the chip, the conductive sheet can be made very thin, and the current technology can reach between 60 μm and 100 μm, which is much thinner than the traditional packaging technology. Thinner, and the production technique is quite simple. On the other hand, you can choose the required lead sheet to meet the needs of the chip used, so as to produce better results. In particular, fingerprint identification and image chips have this need. If the traditional packaging method is used, the packaging layer in the sensing area above the chip must be made quite thin, but it is quite difficult in manufacturing technology, and its sensing ability is also worse than directly selecting appropriate sensing materials.

To sum up, the humanized and considerate design of the utility model quite meets the actual needs. It specifically improves the shortcomings of the prior art. Compared with the prior art, it has the advantages of breakthrough progress, indeed has the enhancement of efficacy, and is not easy to achieve. The utility model has not been disclosed in domestic and foreign documents and markets, and has complied with the provisions of the Patent Law.

The above detailed description is a specific description of a feasible embodiment of the utility model, but this embodiment is not used to limit the scope of patent protection of the utility model, and any equivalent implementation or change made without departing from the technical spirit of the utility model shall be considered Should be included in the patent scope of the present utility model.

Claims (6)

1. A chip package structure with a lead sheet above, characterized in that, comprising: A substrate; there are a plurality of welding pads on the substrate; At least one chip, the lower surface of which is placed on the substrate; each chip has a plurality of welding pads, which can be connected to the plurality of welding pads on the substrate through wires; At least one conductive piece, the conductive piece is a sheet-shaped plate-shaped material; each conductive piece is pasted on the upper surface of the corresponding chip; Wherein, the material of the conductive sheet is different from the material of the subsequent packaging structure. 2. The chip package structure with conductive strips above as claimed in claim 1, further comprising: A packaging structure is used for packaging the at least one chip and the substrate, so that the at least one conductive piece can be exposed to the outside. 3 . The chip package structure with conductive pads as claimed in claim 1 , wherein the conductive pads are made of electromagnetically permeable materials. 4 . 4. The chip package structure with conductive pads thereon as claimed in claim 1, wherein the chip is a fingerprint identification chip. 5 . The chip package structure with conductive pads as claimed in claim 1 , wherein the conductive pads are made of light-transmissible materials. 5 . 6 . The chip package structure with conductive pads as claimed in claim 1 , wherein the chip is a CMOS chip for image sensing or fingerprint recognition. 7 .