CN108538921A - A kind of thin film transistor (TFT) and preparation method thereof, array substrate - Google Patents

Abstract

Embodiments of the present invention provide a thin film transistor, a manufacturing method thereof, and an array substrate, which relate to the field of display technology and can improve the problem of parasitic capacitance. A thin film transistor, comprising: a bottom gate electrode, a first gate insulating layer, an active layer, a second gate insulating layer, a top gate electrode, an organic insulating layer, a source electrode, and a drain electrode arranged sequentially on a substrate; The bottom gate electrode, the first gate insulating layer, the second gate insulating layer and the top gate electrode are located between the source electrode and the drain electrode; the active layer includes The channel region between the insulating layer and the second gate insulating layer, the source region and the drain region respectively located on both sides of the channel region; the source region and the drain region are composed of the organic The insulating layer is supported; the source electrode is in contact with the source region through a via hole, and the drain electrode is in contact with the drain region through a via hole.

Description

A kind of thin film transistor and its preparation method, array substrate

technical field

The invention relates to the field of display technology, in particular to a thin film transistor, a preparation method thereof, and an array substrate.

Background technique

Organic light-emitting diode (Organic Light-Emitting Diode, OLED) display has the advantages of self-luminescence, fast response, viewing angle light, high brightness, light and thin, etc., and is considered to be the next generation display technology. Since OLED displays are driven by current, a large driving current is the basis for ensuring display quality and improving resolution.

Double-gate thin film transistor (Thin Film Transistor, TFT) has the advantages of large on-state current, strong gate control ability (better subthreshold characteristics), etc., and meets the requirements of OLED display for driving current, but there is a large parasitic capacitance.

At present, a TFT with a double gate structure, as shown in FIG. and the top gate electrode 60; the bottom gate insulating layer 31 and the top gate insulating layer 32 are tiled on the substrate.

Contents of the invention

Embodiments of the present invention provide a thin film transistor, a manufacturing method thereof, and an array substrate, which can improve the problem of parasitic capacitance.

In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:

In a first aspect, a thin film transistor is provided, comprising: a bottom gate electrode, a first gate insulating layer, an active layer, a second gate insulating layer, a top gate electrode, an organic insulating layer, and a source electrode arranged sequentially on a substrate, drain electrode; the bottom gate electrode, the first gate insulating layer, the second gate insulating layer and the top gate electrode are located between the source electrode and the drain electrode; the active layer includes A channel region between the first gate insulating layer and the second gate insulating layer, a source region and a drain region respectively located on both sides of the channel region; the source region and the drain The region is supported by the organic insulating layer; the source electrode is in contact with the source region through a via hole, and the drain electrode is in contact with the drain region through a via hole.

Optionally, the thin film transistor further includes a conductive layer disposed on the side of the bottom gate electrode close to the substrate and electrically connected to the bottom gate electrode, and a conductive layer on the same layer as the source electrode and the drain electrode. Auxiliary electrodes; the auxiliary electrodes are respectively electrically connected to the top gate electrode and the conductive layer; the orthographic projection of the conductive layer on the substrate covers the orthographic projection of the active layer on the substrate .

Further optionally, the conductive layer is a transparent conductive layer; the transparent conductive layer is in direct contact with the bottom gate electrode.

Optionally, the thin film transistor further includes an inorganic insulating layer disposed on the side of the organic insulating layer close to the source electrode and the drain electrode; the source electrode passes through the organic insulating layer and the inorganic insulating layer The via hole in the layer is in contact with the source region, and the drain electrode is in contact with the drain region through the via hole penetrating through the organic insulating layer and the inorganic insulating layer.

Optionally, the material of the organic insulating layer is a black organic insulating material.

Optionally, the thickness of the active layer is in the range of 30-80 nm.

In a second aspect, an array substrate is provided, including the thin film transistor described in the first aspect.

In a third aspect, a method for preparing a thin film transistor is provided, comprising: sequentially forming a first metal film, a first gate insulating film, a semiconductor film, a second gate insulating film, a second metal film, and a photoresist on a substrate; Use a mask to expose the photoresist, and after developing, make the shape of the remaining photoresist consistent with the pattern of the active layer to be formed; using the photoresist as a barrier, continuously process the second metal thin film, the photoresist, Etching the second gate insulating film, the semiconductor film, the first gate insulating film, and the first metal film; using photoresist as a barrier, using a wet etching process, respectively The gate insulating film, the first gate insulating film, the second metal film and the first metal film are etched for the second time, so that the second gate insulating film forms a second gate insulating layer, the first A gate insulating film forms a first gate insulating layer, the second metal film forms a top gate electrode, the first metal film forms a bottom gate electrode, and the second gate insulating layer, the first gate insulating layer, The top gate electrode and the bottom gate electrode are located between the source electrode and the drain electrode to be formed; conductorizing the part of the semiconductor film beyond the first gate insulating layer and the second gate insulating layer, forming an active layer, the active layer comprising a channel layer located between the first gate insulating layer and the second gate insulating layer, and conductorized source electrodes respectively located on both sides of the channel region region and drain region; remove the photoresist, and form an organic insulating layer through a patterning process; the source region and the drain region are supported by the organic insulating layer; form a source electrode and a drain electrode through a patterning process , the source electrode is in contact with the source region through a via hole, and the drain electrode is in contact with the drain region through a via hole.

Optionally, a wet etching process is used to etch the second gate insulating film, the first gate insulating film, the second metal film, and the first metal film respectively, so that The second gate insulating film forms a second gate insulating layer, the first gate insulating film forms a first gate insulating layer, the second metal film forms a top gate electrode, and the first metal film forms a bottom gate electrode, It includes: using hydrofluoric acid to etch the second gate insulating film and the first gate insulating film for the second time, so that the second gate insulating film forms a second gate insulating layer, the first gate insulating film thin film to form a first gate insulating layer; on the basis of forming the second gate insulating layer and the first gate insulating layer, the second metal film and the first metal film are etched, so that the The second metal film forms a top gate electrode, and the first metal film forms a bottom gate electrode.

Based on this, performing conductorization on the part of the semiconductor film beyond the first gate insulating layer and the second gate insulating layer to form an active layer includes: using hydrofluoric acid to treat the second gate insulating film and the second gate insulating layer When the first gate insulating film is etched for the second time, hydrogen ions in hydrofluoric acid enter the part of the semiconductor film beyond the first gate insulating layer and the second gate insulating layer to realize conductorization, Form the active layer.

Optionally, before forming the first metal thin film, the method further includes: forming a transparent conductive layer through a patterning process; forming the first metal thin film directly above the transparent conductive layer; forming the source At the same time as the electrode and the drain electrode, the method also includes: forming an auxiliary electrode; the auxiliary electrode is electrically connected to the top gate electrode through a via hole, and is electrically connected to the transparent conductive layer through a via hole; the transparent The orthographic projection of the conductive layer on the substrate covers the orthographic projection of the active layer on the substrate.

Embodiments of the present invention provide a thin film transistor, a manufacturing method thereof, and an array substrate, wherein the bottom gate electrode, the first gate insulating layer, the second gate insulating layer, and the top gate electrode are located between the source electrode and the drain electrode, so that The active layer extends below the source electrode and the drain electrode and is supported by the organic insulating layer, so that the source electrode and the drain electrode are respectively in contact with the active layer, so that the performance of the thin film transistor can be realized and the problem of parasitic capacitance can be improved.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

FIG. 1 is a schematic structural diagram of a thin film transistor provided by the prior art;

Fig. 2 is a top view schematic diagram 1 of a thin film transistor provided by the present invention;

Fig. 3 is a schematic sectional view of AA' in Fig. 2;

FIG. 4 is a schematic top view II of a thin film transistor provided by the present invention;

Fig. 5 is a schematic cross-sectional view of BB' in Fig. 4;

Fig. 6 is the second schematic cross-sectional view of AA' direction in Fig. 2;

Fig. 7 is the second schematic cross-sectional view of BB' direction in Fig. 4;

Fig. 8 is a schematic flow chart of a thin film transistor manufacturing method provided by the present invention;

9(a) to 9(f) are schematic diagrams of a process for preparing a thin film transistor provided by the present invention;

FIG. 10 is a schematic diagram after second etching is performed on the second gate insulating film and the first gate insulating film, and the portion of the semiconductor film beyond the second gate insulating film and the first gate insulating film is conductorized.

Reference signs:

10-substrate; 20-bottom gate electrode; 31-bottom gate insulating layer; 32-top gate insulating layer; 40-active layer; 41-channel region; 42-source region; 43-drain region; 51 -source electrode; 52-drain electrode; 60-top gate electrode; 71-first gate insulating layer; 72-second gate insulating layer; 81-organic insulating layer; 82-inorganic insulating layer; 90-(transparent) conductive layer 100-photoresist; 200-first metal film; 400-semiconductor film; 600-second metal film; 710-first gate insulating film; 720-second gate insulating film.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

An embodiment of the present invention provides a thin film transistor, as shown in FIG. 2 and FIG. 3 , comprising: a bottom gate electrode 20 , a first gate insulating layer 71 , an active layer 40 , a second gate insulating layer disposed on a substrate 10 in sequence. layer 72 , top gate electrode 60 , organic insulating layer 81 , source electrode 51 , and drain electrode 52 .

Wherein, the bottom gate electrode 20 , the first gate insulating layer 71 , the second gate insulating layer 72 and the top gate electrode 60 are located between the source electrode 51 and the drain electrode 52 .

The active layer 40 includes a channel region 41 located between the first gate insulating layer 71 and the second gate insulating layer 72, a source region 42 and a drain region 43 respectively located on both sides of the channel region 41; the source region 42 And the drain region 43 is supported by the organic insulating layer 81; the source electrode 51 is in contact with the source region 42 through the via hole (the dotted circle on the left side in Fig. The drain region 43 contacts.

Those skilled in the art understand that in order to reduce the contact resistance between the source electrode 51 and the source region 42, and the drain electrode 52 and the drain region 43, when forming the active layer 40, it is necessary to Perform conductorization (also referred to as metallization), so that a source region 42 and a drain region 43 are respectively formed on both sides of the channel region 41 .

The bottom gate electrode 20, the first gate insulating layer 71, the second gate insulating layer 72 and the top gate electrode 60 are located between the source electrode 51 and the drain electrode 52, that is, the bottom gate electrode 20, the first gate insulating layer 71, the second The orthographic projections of the gate insulating layer 72 and the top gate electrode 60 on the substrate 10 do not overlap with the orthographic projections of the source electrode 51 and the drain electrode 52 on the substrate 10 .

The source region 42 and the drain region 43 are supported by the organic insulating layer 81, that is, the source region 42 and the drain region 43 are beyond the bottom gate electrode 20, the first gate insulating layer 71, the second gate insulating layer 72 and the top gate electrode 60 , and extend to below the source electrode 51 and the drain electrode 52 respectively. Wherein, the sizes of the bottom gate electrode 20 , the first gate insulating layer 71 , the second gate insulating layer 72 and the top gate electrode 60 may be equal and overlapped.

In the case where there is only the organic insulating layer 81 between the source electrode 51 and the drain electrode 52 and the active layer 40, the source electrode 51 and the drain electrode 52 are respectively connected to the source of the active layer 40 through the via holes arranged on the organic insulating layer 81. The electrode region 42 is in contact with the drain region 43; in addition to the organic insulating layer 81, there are other insulating layers between the source electrode 51 and the drain electrode 52 and the active layer 40, the source electrode 51 and the drain electrode 52 are respectively The source region 42 and the drain region 43 of the active layer 40 are in contact with the via holes penetrating through the organic insulating layer 81 and other insulating layers.

Based on the structure of the TFT in the embodiment of the present invention, the size of the first gate insulating layer 71 and the second gate insulating layer 72 is determined by the set size of the channel region 41 .

An embodiment of the present invention provides a thin film transistor, by making the bottom gate electrode 20, the first gate insulating layer 71, the second gate insulating layer 72 and the top gate electrode 60 be located between the source electrode 51 and the drain electrode 52, so that the active The layer 40 extends to below the source electrode 51 and the drain electrode 52, and is supported by the organic insulating layer 81, so that the source electrode 51 and the drain electrode 52 are respectively in contact with the active layer 40, so that the performance of the thin film transistor can be realized, and the production can be improved. The problem of parasitic capacitance.

Optionally, as shown in FIG. 4 and FIG. 5 , the thin film transistor further includes a conductive layer 90 disposed on the side of the bottom gate electrode 20 close to the substrate 10 and electrically connected to the bottom gate electrode 20 , and connected to the source electrode 51 and the drain electrode 90 . Auxiliary electrode 53 on the same layer as electrode 52 ; auxiliary electrode 53 is electrically connected to top gate electrode 60 and conductive layer 90 respectively; the orthographic projection of conductive layer 90 on substrate 10 covers the orthographic projection of active layer 40 on substrate 10 .

That is, the top gate electrode 60 and the bottom gate electrode 20 are electrically connected through the conductive layer 90 and the auxiliary electrode 53 , so that the top gate electrode 60 and the bottom gate electrode 20 are equipotentially realized. The auxiliary electrode 53 is electrically connected to the conductive layer 90 through the via hole, and the auxiliary electrode 53 is electrically connected to the top gate electrode 60 through the via hole.

Wherein, since the active layer 40 extends to the source region 42 and the drain region 43 under the source electrode 51 and the drain electrode 52 are supported by the organic insulating layer 81, so that there is an The organic insulating layer 81 , therefore, when the conductive layer 90 is provided, the organic insulating layer 81 can also reduce the parasitic capacitance between the source electrode 51 and the drain electrode 52 and the conductive layer 90 .

It should be noted that the electrical connection between the bottom gate electrode 20 and the conductive layer 90 is not limited to the direct contact shown in FIG. 5 , but may be through a via hole.

In the embodiment of the present invention, the arrangement of the conductive layer 90, on the one hand, can cooperate with the auxiliary electrode 53 to electrically connect the top gate electrode 60 and the bottom gate electrode 20; on the other hand, it can be used as a light-shielding layer to block ambient light.

Further preferably, the conductive layer 90 is a transparent conductive layer; the transparent conductive layer is in direct contact with the bottom gate electrode 20 . That is, the bottom gate electrode 20 is directly formed on the transparent conductive layer.

Wherein, the material of the transparent conductive layer may be a transparent conductive oxide material, such as ITO (indium tin oxide), IZO (indium zinc oxide) and the like.

It should be noted that when the conductive layer 90 is a transparent conductive layer, it can absorb ambient light and short-wavelength light inside the panel. Therefore, the transparent conductive layer can also serve as a light-shielding layer. Wherein, when the conductive layer 90 is a metal conductive layer, the metal conductive layer realizes the effect of blocking ambient light by reflecting ambient light, and when the conductive layer 90 is a transparent conductive layer, it realizes the effect of blocking ambient light by absorbing ambient light.

In the embodiment of the present invention, compared with setting the conductive layer 90 as a metal conductive layer, the conductive layer 90 is set as a transparent conductive layer, and it is not necessary to consider the influence on the conductive layer 90 when forming the bottom gate electrode 20 by etching.

Optionally, as shown in FIGS. 6 and 7 , the thin film transistor further includes an inorganic insulating layer 82 disposed on the side of the organic insulating layer 81 close to the source electrode 51 and the drain electrode 52; the source electrode 51 passes through the organic insulating layer 81 The via hole with the inorganic insulating layer 82 is in contact with the source region 42 , and the drain electrode 52 is in contact with the drain region 43 through the via hole penetrating through the organic insulating layer 81 and the inorganic insulating layer 82 .

Wherein, the material of the inorganic insulating layer 82 may be, for example, SiO _x (silicon oxide) and/or SiN _x (silicon nitride) and the like.

Considering that the insulation of organic insulating materials is worse than that of inorganic insulation, in order to reduce the risk of short circuit between source electrode 51 and drain electrode 52 and top gate electrode 60, between organic insulating layer 81 and source electrode 51 and drain electrode 52 An inorganic insulating layer 82 is provided.

Optionally, the material of the organic insulating layer 81 is a black organic insulating material.

Compared with the transparent organic material used for the organic insulating layer 81 , when the material of the organic insulating layer 81 is a black organic insulating material, it can also play a light-shielding function and protect the active layer 40 from the side away from the substrate 10 .

Optionally, the thickness of the active layer 40 is in the range of 30-80 nm.

Because before forming the organic insulating layer 81, the source region 42 and the drain region 43 of the active layer 40 exceed the bottom gate electrode 20, the first gate insulating layer 71, the second gate insulating layer 72 and the top gate electrode 60 and are suspended State, when the thickness of the active layer 40 is relatively thin, there is a risk of breaking, therefore, its strength can be improved by appropriately increasing the thickness of the active layer 40, and when the thickness of the active layer 40 is set in the range of 30-80nm , can basically avoid the occurrence of breakage.

Optionally, the material of the active layer 40 is oxide. The oxide may be, for example, IGZO (Indium Gallium Zinc Oxide), ZnON (Nitrogen Doped Zinc Oxide), IZTO (Indium Zinc Tin Oxide) or the like.

Certainly, the material of the active layer 40 may also be silicon material.

Using oxide as the material of the active layer 40 can make the thin film transistor have higher mobility.

Based on the above description of the thin film transistor, optionally, the materials of the bottom gate electrode 20, the top gate electrode 60, the source electrode 51 and the drain electrode 52 can be selected from Ag (silver), Cu (copper), Al (aluminum), Mo (molybdenum) and other metals, or AlNd (aluminum neodymium), MoNb (molybdenum neodymium) and other alloys. The bottom gate electrode 20 , the top gate electrode 60 , the source electrode 51 and the drain electrode 52 may have a one-layer structure, or a multi-layer structure of two or more layers.

Wherein, when the top gate electrode 60 is made of Cu material, the organic insulating layer 81 also has the function of preventing Cu oxidation.

Optionally, the materials of the first gate insulating layer 71 and the second gate insulating layer 72 can be selected from _SiOx , _SiNx , SiON (silicon oxynitride), etc.; or, can also be selected from such as _AlOx (aluminum oxide), HfO _x (hafnium oxide), TaO _x (tantalum oxide) and other high dielectric constant insulating materials. The first gate insulating layer 71 and the second gate insulating layer 72 may have a one-layer structure, or a multi-layer structure of two or more layers.

Optionally, the material of the organic insulating layer 81 can be selected from polysiloxane-based materials, acrylic-based materials, polyimide-based materials and other materials with planarization effects. The organic insulating layer 81 may have a one-layer structure, or a multi-layer structure of two or more layers.

An embodiment of the present invention also provides an array substrate, including the above thin film transistor.

The array substrate can be used for LCD (Liquid Crystal Display, liquid crystal display), and can also be used for OLED (Organic Light-Emitting Diode, organic light-emitting diode) display.

The array substrate provided by the embodiment of the present invention has the same technical effect as that of the thin film transistor, which will not be repeated here.

The embodiment of the present invention also provides a method for preparing a thin film transistor, as shown in FIG. 8 , including:

S11. As shown in FIG. 9(a), sequentially form the first metal film 200, the first gate insulating film 710, the semiconductor film 400, the second gate insulating film 720, the second metal film 600, and photolithography on the substrate 10. Glue 100.

S12 , as shown in FIG. 9( b ), use a mask to expose the photoresist 100 , and after developing, make the shape of the remaining photoresist 100 consistent with the pattern of the active layer to be formed.

S13, as shown in FIG. 9(c), using the photoresist 100 as a barrier, continuously coat the second metal film 600, the second gate insulating film 720, the semiconductor film 400, the first gate insulating film 710, and the first metal film 200 Etching is performed.

S14, as shown in FIG. 9( d ), use photoresist as a barrier, and adopt a wet etching process to respectively separate the second gate insulating film 720 , the first gate insulating film 710 , the second metal film 600 and the first metal film The film 200 is etched for the second time, so that the second gate insulating film 720 forms the second gate insulating layer 72, the first gate insulating film 710 forms the first gate insulating layer 71, the second metal film 600 forms the top gate electrode 60, and the first gate insulating film 710 forms the top gate electrode 60. A metal thin film 200 forms the bottom gate electrode 20 , and the second gate insulating layer 72 , the first gate insulating layer 71 , the top gate electrode 60 and the bottom gate electrode 20 are located between the source electrode and the drain electrode to be formed.

In S14, the second gate insulating film 720 and the first gate insulating film 710 can be etched for the second time first, and then the second metal film 600 and the first metal film 200 can be etched for the second time; The second etching is first performed on the second metal film 600 and the first metal film 200 , and then the second etching is performed on the second gate insulating film 720 and the first gate insulating film 710 .

S15. As shown in FIG. 9(e), conductorize the portion of the semiconductor thin film 400 beyond the first gate insulating layer 71 and the second gate insulating layer 72 to form the active layer 40, the active layer 40 includes The channel region 41 between the first gate insulating layer 71 and the second gate insulating layer 72 , the source region 42 and the drain region 43 respectively located on both sides of the channel region 41 after conductorization.

Wherein, the size of the first gate insulating layer 71 and the second gate insulating layer 72 is determined by the set size of the channel region 41 .

S16 , as shown in FIG. 9( f ), remove the photoresist 100 , and form an organic insulating layer 81 through a patterning process; the source region 42 and the drain region 43 are supported by the organic insulating layer 81 .

The source region 42 and the drain region 43 are supported by the organic insulating layer 81, that is, the source region 42 and the drain region 43 are beyond the bottom gate electrode 20, the first gate insulating layer 71, the second gate insulating layer 72 and the top gate electrode 60 , and extend to below the source electrode 51 and the drain electrode 52 respectively. Wherein, the sizes of the bottom gate electrode 20 , the first gate insulating layer 71 , the second gate insulating layer 72 and the top gate electrode 60 may be equal and overlapped.

S17. Referring to FIG. 3 , a source electrode 51 and a drain electrode 52 are formed through one patterning process, the source electrode 51 is in contact with the source region 42 through a via hole, and the drain electrode 52 is in contact with the drain region 53 through a via hole.

In the case where there is only the organic insulating layer 81 between the source electrode 51 and the drain electrode 52 and the active layer 40, the source electrode 51 and the drain electrode 52 are respectively connected to the source of the active layer 40 through the via holes arranged on the organic insulating layer 81. The electrode region 42 is in contact with the drain region 43; in addition to the organic insulating layer 81, there are other insulating layers between the source electrode 51 and the drain electrode 52 and the active layer 40, the source electrode 51 and the drain electrode 52 are respectively The source region 42 and the drain region 43 of the active layer 40 are in contact with the via holes penetrating through the organic insulating layer 81 and other insulating layers.

The embodiment of the present invention provides a method for manufacturing a thin film transistor, by positioning the bottom gate electrode 20, the first gate insulating layer 71, the second gate insulating layer 72 and the top gate electrode 60 between the source electrode 51 and the drain electrode 52, and The active layer 40 extends to below the source electrode 51 and the drain electrode 52, and is supported by the organic insulating layer 81, so that the source electrode 51 and the drain electrode 52 are respectively in contact with the active layer 40, thereby realizing the performance of a thin film transistor, and The problem of generating parasitic capacitance can be improved. Wherein, in the process of forming the bottom gate electrode 20, the first gate insulating layer 71, the second gate insulating layer 72 and the top gate electrode 60, only one mask and exposure process is applied, so the difficulty of the process can be reduced, saving cost.

In the above S14, a wet etching process is adopted, and the second gate insulating film 720, the first gate insulating film 710, the second metal film 600 and the first metal film 200 are respectively etched for the second time, so that the second gate insulating film 720 to form the second gate insulating layer 72, the first gate insulating film 710 to form the first gate insulating layer 71, the second metal film 600 to form the top gate electrode 60, and the first metal film 200 to form the bottom gate electrode 20, which may specifically include:

S131. As shown in FIG. 10 , use hydrofluoric acid to etch the second gate insulating film 720 and the first gate insulating film 710 for the second time, so that the second gate insulating film 720 forms the second gate insulating layer 72 and the first gate insulating film 720. The gate insulating film 710 forms the first gate insulating layer 71 .

Specifically, the substrate may be put into a hydrofluoric acid etching solution, and the second gate insulating film 720 and the first gate insulating film 710 are corroded to produce lateral undercutting. Wherein, the depth of inward etching is determined by the set final channel length.

S132. Referring to FIG. 9(e), on the basis of forming the second gate insulating layer 72 and the first gate insulating layer 71, etch the second metal film 600 and the first metal film 200, so that the second metal The thin film 600 forms the top gate electrode 60 , and the first metal thin film 200 forms the bottom gate electrode 20 .

Specifically, when the second metal film 600 and the first metal film 200 are wet-etched, due to the loss of the protection of the second gate insulating layer 72 and the first gate insulating layer 71, the top gate electrode 60 and the bottom gate electrode 20 etched to the same size as the second gate insulating layer 72 and the first gate insulating layer 71 to realize a self-aligned structure.

Wherein, as shown in FIG. 10, when hydrofluoric acid is used to etch the second gate insulating film 720 and the first gate insulating film 710 for the second time, the hydrogen ions in the hydrofluoric acid enter the semiconductor film 400 beyond the first gate insulating film 400. Parts of the layer 71 and the second gate insulating layer 72 are conductorized to form the active layer 40 .

That is, while the second gate insulating layer 72 and the first gate insulating layer 71 are etched, the exposed material of the semiconductor thin film 400 is doped with hydrogen ions to realize conductorization.

On the one hand, the second gate insulating film 720 and the first gate insulating film 710 are etched a second time with hydrofluoric acid to form the first gate insulating layer 71 and the second gate insulating layer 72, and the semiconductor film The part of 400 beyond the first gate insulating layer 71 and the second gate insulating layer 72 is conductive to form the active layer 40. Compared with the high-power plasma channeling solution, the process difficulty and cost are lower; in addition On the one hand, the undercut formed during the wet etching process of the second gate insulating film 720 and the first gate insulating film 710 is performed with hydrofluoric acid, and the second metal film 600 and the first metal film 200 are etched for the second time. The self-aligned structure can be realized in the etching, and the parasitic capacitance (gate-source parasitic capacitance) can be reduced.

Optionally, before forming the first metal thin film 200 , the method further includes: forming the transparent conductive layer 90 through a patterning process; the first metal thin film 200 is directly formed on the transparent conductive layer 90 . On this basis, as shown in FIG. 5, while forming the source electrode 51 and the drain electrode 52, the method also includes forming an auxiliary electrode 53; the auxiliary electrode 53 is electrically connected to the top gate electrode 60 through a via hole, and through the via hole It is electrically connected with the transparent conductive layer 90 ; the orthographic projection of the transparent conductive layer 90 on the substrate 10 covers the orthographic projection of the active layer 40 on the substrate 10 .

That is, the top gate electrode 60 and the bottom gate electrode 20 are electrically connected through the transparent conductive layer 90 and the auxiliary electrode 53 , so that the top gate electrode 60 and the bottom gate electrode 20 are equipotentially realized.

Wherein, since the active layer 40 extends to the source region 42 and the drain region 43 below the source electrode 51 and the drain electrode 52 are supported by the organic insulating layer 81, so that between the source electrode 51 and the drain electrode 52 and the transparent conductive layer 90 There is an organic insulating layer 81 . Therefore, when the transparent conductive layer 90 is formed, the organic insulating layer 81 can also reduce the parasitic capacitance between the source electrode 51 and the drain electrode 52 and the transparent conductive layer 90 .

In the embodiment of the present invention, the formation of the transparent conductive layer 90, on the one hand, can cooperate with the auxiliary electrode 53 to electrically connect the top gate electrode 60 and the bottom gate electrode 20; on the other hand, it can be used as a light shielding layer to block the effect of ambient light On the other hand, when forming the bottom gate electrode 20 by etching, it is not necessary to consider the influence on the transparent conductive layer 90 .

Optionally, as shown in FIG. 6 and FIG. 7, the thin film transistor further includes forming an inorganic insulating layer 82 on the side of the organic insulating layer 81 close to the source electrode 51 and the drain electrode 52; the source electrode 51 passes through the organic insulating layer 81 and The via hole of the inorganic insulating layer 82 is in contact with the source region 42 , and the drain electrode 52 is in contact with the drain region 43 through the via hole penetrating through the organic insulating layer 81 and the inorganic insulating layer 82 .

Wherein, the material of the inorganic insulating layer 82 may be, for example, SiO _x (silicon oxide) and/or SiN _x (silicon nitride).

Considering that the insulation of organic insulating materials is worse than that of inorganic insulation, in order to reduce the risk of short circuit between source electrode 51 and drain electrode 52 and top gate electrode 60, between organic insulating layer 81 and source electrode 51 and drain electrode 52 The inorganic insulating layer 82 is formed.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (10)

1. a kind of thin film transistor (TFT), which is characterized in that including：Be set in turn in bottom gate thin film on substrate, the first gate insulation layer, Active layer, the second gate insulation layer, top-gated electrode, organic insulator and source electrode, drain electrode；

The bottom gate thin film, first gate insulation layer, second gate insulation layer and the top-gated electrode are located at source electricity Between pole and the drain electrode；

The active layer includes channel region between first gate insulation layer and second gate insulation layer, is located at The source area of the channel region both sides and drain region；The source area and the drain region are supported by the organic insulator；Institute Source electrode is stated by via and the source region contact, the drain electrode is contacted by via with the drain region.

2. thin film transistor (TFT) according to claim 1, which is characterized in that further include being set to the bottom gate thin film close to institute It states one side of substrate and the conductive layer being electrically connected with the bottom gate thin film and the auxiliary of the source electrode and the drain electrode same layer is electric Pole；

The auxiliary electrode is electrically connected with the top-gated electrode, the conductive layer respectively；The conductive layer is over the substrate Orthographic projection covers the orthographic projection of the active layer over the substrate.

3. thin film transistor (TFT) according to claim 2, which is characterized in that the conductive layer is transparency conducting layer；

The transparency conducting layer is in direct contact with the bottom gate thin film.

4. thin film transistor (TFT) according to claim 1, which is characterized in that further include that be set to the organic insulator close The inorganic insulation layer of the source electrode and the drain electrode side；

The source electrode passes through through the via of the organic insulator and the inorganic insulation layer and the source region contact, institute Drain electrode is stated by being contacted with the drain region through the via of the organic insulator and the inorganic insulation layer.

5. thin film transistor (TFT) according to claim 1, which is characterized in that the material of the organic insulator is that black is organic Insulating materials.

6. according to claim 1-5 any one of them thin film transistor (TFT)s, which is characterized in that the thickness of the active layer 30~ Within the scope of 80nm.

7. a kind of array substrate, which is characterized in that including claim 1-6 any one of them thin film transistor (TFT)s.

8. a kind of preparation method of thin film transistor (TFT), which is characterized in that including：

The first metallic film, the first grid insulating film, semiconductive thin film, the second grid insulating film, are sequentially formed on substrate Two metallic films, photoresist；

The photoresist is exposed using mask plate, and after development, makes the shape of the photoresist of reservation and active layer to be formed Pattern is consistent；

With photoresist be blocking, continuously to second metallic film, second grid insulating film, the semiconductive thin film, First grid insulating film and first metallic film perform etching；

It is blocking with photoresist, it is thin to second grid insulating film, first gate insulation respectively using wet-etching technology Film, second metallic film and first metallic film carry out second and etch, and second grid insulating film is made to be formed Second gate insulation layer, first grid insulating film form the first gate insulation layer, second metallic film forms top-gated electrode, First metallic film forms bottom gate thin film, and second gate insulation layer, first gate insulation layer, the top-gated electrode And the bottom gate thin film is between source electrode and drain electrode to be formed；

To part of the semiconductive thin film beyond first gate insulation layer and second gate insulation layer into column conductor, shape At active layer, the active layer include channel layer between first gate insulation layer and second gate insulation layer, point It Wei Yu not source area and drain region of the channel region both sides after conductor；

Photoresist is removed, and organic insulator is formed by a patterning processes；The source area and the drain region are by described Organic insulator supports；

Source electrode and drain electrode is formed by a patterning processes, the source electrode passes through via and the source region contact, institute Drain electrode is stated to contact with the drain region by via.

9. preparation method according to claim 8, which is characterized in that wet-etching technology is used, respectively to described second Grid insulating film, first grid insulating film, second metallic film and first metallic film carry out second and carve Erosion makes second grid insulating film form the second gate insulation layer, the first gate insulation layer of first grid insulating film formation, institute It states the second metallic film and forms top-gated electrode, first metallic film formation bottom gate thin film, including：

Second is carried out to second grid insulating film and first grid insulating film to etch, make described the using hydrofluoric acid Two grid insulating films form the second gate insulation layer, first grid insulating film forms the first gate insulation layer；

Forming second gate insulation layer and on the basis of first gate insulation layer, to second metallic film and described First metallic film performs etching, and second metallic film is made to form top-gated electrode, first metallic film formation bottom gate Electrode；

To part of the semiconductive thin film beyond first gate insulation layer and second gate insulation layer into column conductor, shape At active layer, including：

When carrying out second of etching to second grid insulating film and first grid insulating film using hydrofluoric acid, hydrofluoric acid In hydrogen ion enter the semiconductive thin film exceed first gate insulation layer and second gate insulation layer part, realize Conductor forms active layer.

10. preparation method according to claim 8 or claim 9, which is characterized in that before forming first metallic film, The method further includes：Transparency conducting layer is formed by a patterning processes；First metallic film is formed directly into described Above transparency conducting layer；

While forming the source electrode and the drain electrode, the method further includes：Form auxiliary electrode；The auxiliary electricity Pole is electrically connected by via with the top-gated electrode, is electrically connected with the transparency conducting layer by via；The transparency conducting layer Orthographic projection over the substrate covers the orthographic projection of the active layer over the substrate.