CN111682034A - Array substrate and preparation method thereof, and display device - Google Patents

Abstract

The invention provides an array substrate, a preparation method thereof and a display device. The array substrate comprises a substrate, an active layer, a grid electrode insulating layer, a conductor action layer, a dielectric layer and a source drain layer. The conductive layer is disposed on the substrate and covers the active layer, the gate insulating layer, and the gate layer. The conductive layer contains an active metal.

Description

Array substrate and preparation method thereof, and display device

technical field

The invention relates to the field of display equipment, in particular to an array substrate, a preparation method thereof, and a display device.

Background technique

With the advancement of display technology, thin film transistor liquid crystal display (TFT-LCD) has become the main product in the display market due to its advantages of lightness, thinness, low radiation and small size without occupying space. With the development of the industry, the industrial competition of LCD panel manufacturers is increasing day by day. How to improve the performance and reliability of thin film transistors and reduce manufacturing costs are important development goals.

Compared with silicon TFTs currently widely used in active driving matrices of liquid crystal displays, oxide semiconductor TFTs have the following advantages: (1) higher field-effect mobility; (2) high on-off ratio; (3) low fabrication temperature (4) It can make large-area amorphous thin films, with good uniformity and good and consistent electrical properties; (5) It is less affected by visible light and is more stable than amorphous silicon thin film transistors; (6) It can be made into transparent devices. In the field of flat panel display, oxide TFT technology almost meets all the requirements of many display modes including AMOLED drive, fast large-screen liquid crystal display, 3D display and so on. In terms of flexible display, the substrate material cannot withstand high temperature, and the preparation process temperature of oxide TFT is low, which is compatible with flexible substrates, so oxide TFT has great advantages.

The advent of new material IGZO has solved the shortcomings of traditional hydrogenated amorphous silicon very well. However, in the preparation process of IGZO TFT, plasma bombardment of IGZO with helium or argon is often used to conduct conductorization. After bombardment, with the annealing of the subsequent process, the conductorized area will combine with oxygen in the ILD, resulting in the resistance of IGZO. increase, affecting the performance of the display panel.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide an array substrate, a preparation method thereof, and a display device, so as to solve the problem in the prior art that the conductive region of IGZO will combine with oxygen in the ILD, thereby increasing the resistance of IGZO.

To achieve the above object, the present invention provides an array substrate, which includes a substrate, an active layer, a gate insulating layer, a conducting layer, a dielectric layer, and a source and drain layer. The active layer is disposed on the substrate, and includes a channel region and a conductive region connected to the channel region. The gate insulating layer is disposed on the active layer. The gate layer is disposed on the gate insulating layer. The conductive layer is disposed on the substrate and covers the conductive region of the active layer, the gate insulating layer and the gate layer. The conductive layer has an active metal, and the active metal abstracts the oxygen atoms in the conductive region to form a metal oxide. The dielectric layer is disposed on the conductive layer. The source and drain layers are disposed on the dielectric layer and connected to the active layer.

Further, the active metal includes at least one of magnesium and hafnium.

Further, the source and drain layers include source wiring and drain wiring. The source wiring and the drain wiring pass through the dielectric layer and the conductive layer, and are respectively connected to the conductive regions of the active layer.

Further, the active layer is an oxide semiconductor; the oxide semiconductor includes indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (IZTO), indium gallium zinc tin oxide At least one of oxides (IGZTO).

Further, the array substrate further includes a buffer layer and a light shielding layer. The buffer layer is disposed between the substrate and the active layer. The light shielding layer is disposed between the substrate and the buffer layer. One end of the source wiring is connected to the active layer, and the other end is connected to the light shielding layer through the dielectric layer, the conducting layer and the buffer layer.

Further, the array substrate further includes a passivation layer. The passivation layer is disposed on the dielectric layer, and has an opening corresponding to the source wiring.

The present invention also provides a method for preparing an array substrate, which includes the following steps:

A substrate is provided. An active layer is formed on the substrate. A gate insulating layer is formed on the active layer. A gate layer is formed on the gate insulating layer. A conductive layer is formed on the substrate. A dielectric layer is formed on the conductorization layer. A source and drain layer is formed on the dielectric layer.

Wherein, the conductive layer has an active metal, and the active metal abstracts the oxygen atoms in the conductive region to form a metal oxide.

Further, the active metal includes at least one of magnesium and hafnium.

Further, the step of forming the conductive layer on the substrate includes the following steps:

An active metal material layer is deposited on the substrate and covers the active layer, the gate insulating layer and the gate layer. The active metal material captures part of the oxygen atoms in the active layer through an annealing process, and conducts the active layer to form the conductive region and the channel region. At the same time, the active metal material is oxidized to form the The conductive layer is described.

The present invention also provides a display device comprising the above-mentioned array substrate.

The advantages of the present invention are:

An array substrate and a preparation method thereof of the present invention add a conductive layer with active metal, and the active metal is gradually oxidized during the conductive process of the active layer, which can prevent the active layer from being damaged. The damage to the gate layer caused by the conductorization process can also prevent the damage to the active layer caused by hydrogen and oxygen in the subsequent film layer process, prevent its resistance from increasing, and reduce the influence of hydrogen and oxygen on the electrical properties of the array substrate, thereby improving the array substrate. stability.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained from these drawings without creative effort.

FIG. 1 is a layered schematic diagram of an array substrate in an embodiment of the present invention;

Fig. 2 is the schematic flow sheet of the preparation method in the embodiment of the present invention;

3 is a schematic diagram of layers in step S20 in an embodiment of the present invention;

FIG. 4 is a layered schematic diagram in step S40 in an embodiment of the present invention;

FIG. 5 is a schematic diagram of layers in step S50 in an embodiment of the present invention;

6 is a schematic diagram of layers in step S60 in an embodiment of the present invention;

FIG. 7 is a schematic diagram of layers in step S70 in an embodiment of the present invention;

FIG. 8 is a schematic diagram of layers in step S80 in an embodiment of the present invention.

The parts in the figure are represented as follows:

an array substrate 100;

substrate 101; light shielding layer 102;

buffer layer 103; active layer 104;

Conductive region 1041; channel region 1042;

gate insulating layer 105; gate layer 106;

Conductive layer 107; Dielectric layer 108;

Source and drain layers 109; source traces 1091;

Drain trace 1092; passivation layer 110;

Opening 1101; source-drain contact hole 111.

Detailed ways

The preferred embodiments of the present invention are described below with reference to the accompanying drawings to prove that the present invention can be implemented. The embodiments of the present invention can fully introduce the present invention to those skilled in the art, so that its technical content is clearer and easier to understand. The present invention can be embodied in many different forms of embodiments of the invention, and the protection scope of the present invention is not limited to the embodiments mentioned herein.

In the drawings, structurally identical components are denoted by the same numerals, and structurally or functionally similar components are denoted by like numerals throughout. The size and thickness of each component shown in the drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component. In order to make the illustration clearer, the thicknesses of components are appropriately exaggerated in some places in the drawings.

Furthermore, the following description of various inventive embodiments is made with reference to the accompanying drawings to illustrate specific inventive embodiments in which the present invention may be practiced. Directional terms mentioned in the present invention, such as "up", "down", "front", "rear", "left", "right", "inside", "outside", "side", etc., only Reference is made to the directions of the accompanying drawings, therefore, the directional terms used are for better and clearer description and understanding of the present invention, rather than indicating or implying that the device or element referred to must have a specific orientation, in a specific orientation construction and operation, and therefore should not be construed as limiting the invention. Furthermore, the terms "first," "second," "third," etc. are used for descriptive purposes only and should not be construed to indicate or imply relative importance.

When certain elements are described as being "on" another element, the element can be directly on the other element; an intervening element may also be present and the element is on the intervening element, And the intermediate part is placed on the other part. When an element is described as being "mounted to" or "connected to" another element, both can be understood to be "mounted" or "connected" directly, or that one element is indirectly "mounted to" or "connected to" through an intervening element to" another component.

An embodiment of the present invention provides a display device, the display device includes an array substrate 100, the display device is a liquid crystal display device, and the array substrate 100 controls the deflection and light transmission of liquid crystals of the liquid crystal display device, Thereby, the display screen of the display device is controlled. The display device may be any product or component with a display function, such as a mobile phone, a tablet computer, and a notebook computer.

As shown in FIG. 1 , the array substrate 100 includes a substrate 101 , a light shielding layer 102 , a buffer layer 103 , an active layer 104 , a gate insulating layer 105 , a gate layer 106 , a conductive layer 107 , and a dielectric layer 108 and source and drain layers 109 .

The substrate 101 may be an insulating substrate such as a glass substrate or a quartz substrate, which is used to protect the overall structure of the array substrate 100 .

The light-shielding layer 102 is disposed on the substrate 101 and is made of a conductive light-shielding material, such as aluminum, silver, molybdenum, copper, titanium and other metal materials. The light shielding layer 102 can be a single-layer metal structure or a double-layer metal structure, and the thickness thereof is between 500 angstroms and 2000 angstroms. Since the active layer 104 is very sensitive to light, after the active layer 104 is irradiated with light, the threshold voltage in the array substrate 100 will be significantly negatively shifted. By disposing the light shielding layer 102 under the active layer 104, The light entering from the side of the substrate 101 is shielded for the active layer 104, so as to solve the phenomenon of negative shift of the threshold voltage in the display panel caused by the illumination.

The buffer layer 103 is disposed on the substrate 101 and covers the light shielding layer 102 , and its material includes one or more inorganic materials such as silicon oxide and silicon nitride, and its thickness is 1000 angstroms-5000 angstroms. The buffer layer 103 is used to insulate the light shielding layer 102 and the active layer 104, and also has a buffer function to prevent damage to devices in the display panel due to impact.

The active layer 104 is disposed on a surface of the buffer layer 103 away from the light shielding layer 102 and corresponds to the light shielding layer 102 . The active layer 104 is an oxide semiconductor, and the oxide semiconductor may be indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium tin zinc oxide (IZTO), and indium gallium zinc tin oxide (IGZTO) and other metal oxide materials. The active layer 104 has a channel region 1042 and a conductive region 1041 connected to the channel region 1042 . The conductive regions 1041 are located on two sides of the channel region 1042 respectively. The conductive region 1041 is used to connect with the source and drain layers 109 .

The gate insulating layer 105 is disposed on the active layer 104 and corresponds to the channel region 1042 , and is used for insulating and protecting the active layer 104 and the gate layer 106 . The material of the gate insulating layer 105 includes one or more inorganic materials such as silicon oxide and silicon nitride, and the thickness thereof is 100 angstroms to 1000 angstroms.

The gate layer 106 is disposed on the gate insulating layer 105 . The material of the gate layer 106 is a conductive metal, such as molybdenum, copper, aluminum, titanium, etc., which can be a single-layer alloy or a multi-layer metal structure, and its thickness is 1000 angstroms-10000 angstroms.

The conductive layer 107 is disposed on the buffer layer 103 and covers the active layer 104 , the gate insulating layer 105 and the gate layer 106 . The conductive layer 107 contains active metals, such as magnesium, hafnium, and the like. The conducting layer 107 is used for conducting the active layer 104 . During the conducting process, the active metal in the conducting layer 107 will capture the oxygen atoms in the conducting region 1041 in the active layer 104 , so that the active layer 104 is conducting. While conducting the active layer, the active metal itself is also oxidized after taking oxygen atoms, so the conducting layer 107 also includes metal oxides, such as magnesium oxide, hafnium oxide, and the like. The conductive layer 107 has a thickness of 20 angstroms to 500 angstroms. The conductive layer 107 also has the function of blocking the influence of hydrogen and oxygen on the active layer 104 in the subsequent process, thereby improving the electrical stability of the array substrate 100 .

The dielectric layer 108 is disposed on the conductive layer 107 for insulating and protecting the source and drain layers 109 . The dielectric layer 108 is an inorganic material layer, which can be insulating materials such as silicon oxide and silicon nitride, and has a thickness of 2000 angstroms to 10000 angstroms.

The source and drain layers 109 are disposed on the dielectric layer 108 , and have source traces 1091 and drain traces 1092 . One end of the source trace 1091 is electrically connected to the conductive region 1041 at one end of the active layer 104 through the dielectric layer 108 and the conductive layer 107 , and the other end of the source line 1091 passes through the dielectric layer 108 and the conductive layer 104 . The active layer 107 and the buffer layer 103 are connected to the light shielding layer 102 . The drain trace 1092 is connected to the conductive region 1041 at the other end of the active layer 104 through the dielectric layer 108 and the conductive layer 107 . The material of the source and drain layers 109 is also a conductive metal, such as molybdenum, copper, aluminum, titanium, etc., which can be a single-layer alloy or a multi-layer metal structure, and its thickness is 1000 angstroms-10000 angstroms.

The passivation layer 110 is disposed on the dielectric layer 108 and covers the source and drain layers 109 for insulating and protecting the source and drain layers 109 . The passivation layer 110 has an opening 1101, the opening 1101 corresponds to the source wiring 1091 of the source-drain layer 109, which is used to connect the pixel electrode in the subsequent process with the source wiring 1091 . The passivation layer 110 is an inorganic material layer, which can be insulating materials such as silicon oxide and silicon nitride, and has a thickness of 2000 angstroms to 10000 angstroms.

When a current and voltage are applied to the gate, it will generate an electric field, and the electric field will induce induced charges on the surface of the active layer 104 to change the width of the conductive channel in the active layer 104, thereby achieving control Source trace 1091 and drain trace 1092 current purpose. At the same time, by connecting the source trace 1091 to the light shielding layer 102, a stable voltage is generated on the light shielding layer 102, which can avoid the floating gate effect of the light shielding layer 102, thereby improving the working stability of the array substrate 100. sex.

The embodiment of the present invention also provides a method for preparing the above-mentioned array substrate 100. The preparation process is as shown in FIG. 2, and the specific preparation steps are as follows:

Step S10) providing a substrate 101: the substrate 101 may be an insulating substrate such as a glass substrate, a quartz substrate, or the like. At the same time, the substrate 101 is cleaned.

Step S20) forming a light-shielding layer 102: as shown in FIG. 3, depositing one or more layers of metal material on a surface of the substrate 101, patterning the metal material layer through an etching process, defining a light-shielding area, and forming the The light shielding layer 102 .

Step S30 ) forming a buffer layer 103 : depositing a layer of inorganic insulating material on the substrate 101 and the light shielding layer 102 to form the buffer layer 103 .

Step S40 ) forming the active layer 104 : as shown in FIG. 4 , deposit a layer of metal oxide, such as indium gallium zinc oxide (IGZO), indium gallium tin oxide, on a surface of the buffer layer 103 away from the light shielding layer 102 (IGTO), indium tin zinc oxide (IZTO) or indium gallium zinc tin oxide (IGZTO), and patterning them to form the active layer 104 .

Step S50) forming a gate insulating layer 105 and a gate layer 106: as shown in FIG. 5, a layer of inorganic material, such as silicon oxide or silicon nitride, is layered on the active layer 104, and then deposited on the inorganic material layer One or more layers of metal materials, an etching area is defined on the inorganic material layer and the metal material layer by a mask process, and patterned at the same time by a wet etching method to form the gate insulating layer 105 and the gate Pole layer 106 .

Step S60 ) forming a conductive layer 107 : as shown in FIG. 6 , deposit an active metal material layer on the buffer layer 103 , and the active metal material layer covers the active layer 104 and the gate insulating layer 105 and the gate layer 106 . The active metal material contains at least one of magnesium and hafnium. The active metal in the active metal material layer deprives the oxygen atoms in the active layer 104 through an annealing process at a temperature of 200-300° C., so as to conduct the active layer 104 to form the active layer 104 . Channel region 1042 and conductive region 1041. At the same time, the active metal material in the active metal material layer is also oxidized to form magnesium oxide and hafnium oxide, thereby forming the conductive layer 107 .

Step S70 ) forming a dielectric layer 108 : as shown in FIG. 7 , a layer of inorganic material is formed on the conductive layer 107 to form the dielectric layer 108 . Then, through a mask process, a source-drain contact hole 111 region is defined on the dielectric layer 108 , and an etching process is performed in the dielectric layer 108 , the conducting layer 107 and the buffer layer 103 . The source-drain contact holes 111 are formed.

Step S80 ) forming the source and drain layers 109 : as shown in FIG. 8 , depositing a metal material on the dielectric layer 108 shown in FIG. 8 , the metal material fills the source and drain contact holes 111 and the conductors of the active layer 104 Then, it is patterned through a photomask process and an etching process to form source wirings 1091 and drain wirings 1092 .

Step S90 ) forming a passivation layer 110 : depositing a layer of inorganic material on the dielectric layer 108 , and the inorganic material covers the source and drain layers 109 to form the passivation layer 110 . An opening 1101 is formed on the passivation layer 110 through a mask process and an etching process, and finally an array substrate 100 as shown in FIG. 1 is formed.

In the embodiment of the present invention, by depositing a conductive layer 107 with active metal, the active metal in the conductive layer 107 is gradually oxidized during the conductive process of the active layer 104. Xinghu once metal oxide, both It can prevent the damage to the gate layer 106 caused by the conductive process of the active layer 104 , and can also prevent the damage to the active layer 104 caused by hydrogen and oxygen in the subsequent film layer process, thereby reducing the influence of hydrogen and oxygen on the electrical properties of the array substrate 100 . , to improve the stability of the array substrate 100 .

Although the invention has been described herein with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the invention. It should therefore be understood that many modifications may be made to the exemplary embodiments and other arrangements can be devised without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood that the features described in the various dependent claims and herein may be combined in different ways than are described in the original claims. It will also be appreciated that features described in connection with a single embodiment may be used in other described embodiments.

Claims (10)

1. An array substrate, characterized in that, comprising: substrate; an active layer, disposed on the substrate, the active layer includes a channel region and a conductive region connected to the channel region; a gate insulating layer, disposed on the active layer; a gate layer, disposed on the gate insulating layer; a conductive layer, disposed on the substrate, and covering the conductive region of the active layer, the gate insulating layer and the gate layer; the conductive layer has active metal, the Metal oxides are formed after the active metal captures the oxygen atoms in the conducting region; a dielectric layer, disposed on the conductive layer; The source and drain layers are arranged on the dielectric layer and connected to the active layer. 2 . The array substrate of claim 1 , wherein the active metal comprises at least one of magnesium and hafnium. 3 . 3 . The array substrate of claim 1 , wherein the source and drain layers comprise source wiring and drain wiring; 3 . The source wiring and the drain wiring pass through the dielectric layer and the conductive layer, and are respectively connected to the conductive regions of the active layer. 4. The array substrate of claim 1, wherein the active layer is an oxide semiconductor; the oxide semiconductor comprises indium gallium zinc oxide, indium gallium tin oxide, indium tin zinc oxide, At least one of indium gallium zinc tin oxide. 5. The array substrate of claim 3, further comprising: a buffer layer, disposed between the substrate and the active layer; a light shielding layer, disposed between the substrate and the buffer layer; One end of the source wiring is connected to the active layer, and the other end is connected to the light shielding layer through the dielectric layer, the conducting layer and the buffer layer. 6. The array substrate of claim 3, further comprising: The passivation layer is disposed on the dielectric layer, and has an opening corresponding to the source wiring. 7. A method for preparing an array substrate, comprising the following steps: providing a substrate; forming an active layer on the substrate; forming a gate insulating layer on the active layer; forming a gate layer on the gate insulating layer; forming a conductive layer on the substrate, the conductive layer has an active metal, and the active metal captures the oxygen atoms in the conductive region to form a metal oxide; forming a dielectric layer on the conductive layer; A source and drain layer is formed on the dielectric layer. 8 . The method for preparing an array substrate according to claim 7 , wherein the active metal comprises at least one of magnesium and hafnium. 9 . 9 . The method for preparing an array substrate according to claim 7 , wherein the step of forming a conductive layer on the substrate comprises the following steps: 10 . depositing a layer of active metal material on the substrate and covering the active layer, the gate insulating layer and the gate layer; The active metal material captures part of the oxygen atoms in the active layer through an annealing process, and conducts the active layer to form the conductive region and the channel region. At the same time, the active metal material is oxidized to form the The conductive layer is described. 10. A display device, comprising the array substrate according to claims 1-6.

Images