CN108346442A - sense amplifier - Google Patents
sense amplifier Download PDFInfo
- Publication number
- CN108346442A CN108346442A CN201710060981.2A CN201710060981A CN108346442A CN 108346442 A CN108346442 A CN 108346442A CN 201710060981 A CN201710060981 A CN 201710060981A CN 108346442 A CN108346442 A CN 108346442A
- Authority
- CN
- China
- Prior art keywords
- transistor
- electrode
- sense amplifier
- grid
- input terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000013078 crystal Substances 0.000 claims description 14
- 230000003321 amplification Effects 0.000 claims description 13
- 238000003199 nucleic acid amplification method Methods 0.000 claims description 13
- 230000005611 electricity Effects 0.000 claims description 5
- 239000000126 substance Substances 0.000 claims 1
- 230000035945 sensitivity Effects 0.000 abstract description 5
- 238000010586 diagram Methods 0.000 description 8
- 230000001737 promoting effect Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000004088 simulation Methods 0.000 description 2
- 241000208340 Araliaceae Species 0.000 description 1
- 235000005035 Panax pseudoginseng ssp. pseudoginseng Nutrition 0.000 description 1
- 235000003140 Panax quinquefolius Nutrition 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 235000008434 ginseng Nutrition 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
Landscapes
- Amplifiers (AREA)
- Static Random-Access Memory (AREA)
Abstract
The present invention provides a kind of sense amplifiers, including reference current branch and memory cell current branch, the reference current branch has first input end and the first output end, the memory cell current branch has the second input terminal and second output terminal, the first input end is directly connected with first output end by the first feedback amplifier, and second input terminal is directly connected with the second output terminal by the second feedback amplifier；In the differential signal that first input end and the second input terminal input output signal is generated by sense amplifier, output signal passes through the first feedback amplifier or the second feedback amplifier, the voltage signal of input terminal one of in drop-down first input end and the second input terminal, to increase the differential voltage of two input terminals, be conducive to improve the anti-interference ability of sense amplifier and promote the speed ability of sense amplifier, to realize the design of High sensitivity amplifier.
Description
Technical field
The present invention relates to semiconductor integrated circuit fields, and in particular to a kind of sense amplifier.
Background technology
Sense amplifier (SA, Sense Amplifier) is composition portion important in NVM (nonvolatile memory) circuit
Point, for reading the data in storage array.Sense amplifier is widely used in various reservoir designs, and difference is small
Signal is converted into big signal, to differentiate " 1 " or " 0 " data being stored in memory (Bit Cell).
Sense amplifier generally comprises a reference current branch and a memory cell current branch, by comparing reference current
Branch exports " 0 " or " 1 " signal with memory cell current branch.
With the development of advanced technologies, supply voltage further declines, it is desirable that anti-interference energy of the sense amplifier to noise
Power further increases, and especially when designing high speed reading circuit, how to increase the differential input voltage of sense amplifier,
Be conducive to anti-interference and promote speed ability.
Therefore, how to increase the differential input voltage of sense amplifier, improve anti-interference ability and promote speed ability
It is those skilled in the art's urgent problem to be solved.
Invention content
The purpose of the present invention is to provide a kind of sense amplifiers, increase differential input voltage, enhance sense amplifier
Anti-interference ability promotes speed ability.
To achieve the above object, the present invention provides a kind of sense amplifier, including the reference current branch being connected to each other with
Memory cell current branch, the reference current branch have first input end and the first output end, the memory cell current
Branch has the second input terminal and second output terminal, which is characterized in that the first input end passes through the first feedback amplifier
Directly it is connected with first output end, second input terminal is directly defeated with described second by the second feedback amplifier
Outlet is connected, and first feedback amplifier is used to amplify the output signal of first output end, second feedback
Amplifying circuit is used to amplify the output signal of the second output terminal.
Optionally, first feedback amplifier includes the first phase inverter and the tenth two-transistor；Second feedback
Amplifying circuit includes the second phase inverter and the 13rd transistor.
Optionally, the input terminal of first phase inverter is connected to first output end, first phase inverter it is defeated
Outlet is connected to the grid of the tenth two-transistor；The drain electrode of tenth two-transistor is connected to the first input end,
The source electrode of tenth two-transistor is connected to ground terminal；The input terminal of second phase inverter is connected to second output
End, the output end of second phase inverter are connected to the grid of the 13rd transistor；The drain electrode of 13rd transistor
It is connected to second input terminal, the source electrode of the 13rd transistor is connected to ground terminal.
Optionally, the tenth two-transistor and the 13rd transistor are PMOS tube.
Optionally, the reference current branch and the memory cell current Mirroring of tributary symmetric design.
Optionally, the reference current branch includes four transistors；The first electrode of the first transistor and the second crystal
The first electrode of pipe is connected, the second electrode of the first transistor, the second electrode of the second transistor, third crystal
The second electrode of pipe is connected to second output terminal, and the grid of the first transistor is connected to enable signal；Second crystal
The grid of pipe, the grid of third transistor are connected to the first output end；The first electrode of the third transistor and the 4th crystal
The second electrode of pipe is connected；The grid of 4th transistor is connected to first input end.
Optionally, the memory cell current branch includes four transistors；The first electrode and the 6th of 5th transistor
The first electrode of transistor is connected, the second electrode of the 5th transistor, the second electrode of the 6th transistor, the 7th
The second electrode of transistor is connected to the first output end, and the grid of the 5th transistor is connected to enable signal；Described 6th
The grid of transistor, the 7th transistor grid be connected to second output terminal；The first electrode and the 8th of 7th transistor
The second electrode of transistor is connected；The grid of 8th transistor is connected to the second input terminal, the 8th transistor
First electrode is connected with the first electrode of the 4th transistor.
Optionally, the first electrode of the first transistor, the first electrode of second transistor, the 5th transistor first
Electrode, the 6th transistor first electrode be connected.
Optionally, the sense amplifier further includes the 9th transistor, and the grid of the 9th transistor is connected to enabled
Signal, the first electrode ground connection of the 9th transistor, second electrode and the 4th transistor of the 9th transistor
First electrode, the first electrode of the 8th transistor are connected.
Optionally, the first electrode be source electrode or drain electrode in one of electrode, the second electrode be source electrode or
Another electrode in drain electrode.
Optionally, the work schedule of the sense amplifier includes three phases：
Pre-charging stage：It charges with the second input terminal to the sense amplifier first input end；
The voltage differential stage：Differential voltage is formed between the first input end and the second input terminal of the sense amplifier
Difference；
Working stage：Sense amplifier is opened, output signal passes through the first feedback amplifier or the second feedback amplification electricity
Road is amplified so that the voltage differential of two input terminals is enhanced.
Optionally, in the pre-charging stage, first input end is equal with the voltage of the second input terminal, and maintains a certain
Predetermined level.
Optionally, in the working stage, the sense amplifier is opened using enable signal.
Compared with prior art, sense amplifier provided by the invention is set between first input end and the first output end
The first feedback amplifier is set, the second feedback amplifier is set between the second input terminal and second output terminal, described first
Feedback amplifier is used to amplify the output signal of first output end, and second feedback amplifier is described for amplifying
The output signal of second output terminal；It is generated by sense amplifier in the differential signal that first input end and the second input terminal input
Output signal, output signal pass through the first feedback amplifier or the second feedback amplifier, pull down first input end and second
The voltage signal of input terminal one of in input terminal is conducive to improve spirit to increase the differential voltage of two input terminals
The anti-interference ability of quick amplifier and the speed ability for promoting sense amplifier, to realize setting for High sensitivity amplifier
Meter.
Description of the drawings
Fig. 1 is the schematic diagram of sense amplifier.
The schematic diagram for the sense amplifier that Fig. 2 is provided by one embodiment of the invention.
The preferred circuit schematic diagram for the sense amplifier that Fig. 3 is provided by one embodiment of the invention.
The simulation waveform for the sense amplifier that Fig. 4 and Fig. 5 is provided by one embodiment of the invention.
Specific implementation mode
To keep present disclosure more clear and easy to understand, below in conjunction with Figure of description, present disclosure is done into one
Walk explanation.Certainly the invention is not limited to the specific embodiment, and general replacement well known to the skilled artisan in the art is also contained
Lid is within the scope of the present invention.
Secondly, the present invention has carried out detailed statement using schematic diagram, when present example is described in detail, for the ease of saying
Bright, schematic diagram is not partially enlarged in proportion to the general scale, should not be to this restriction as the present invention.
Fig. 1 be sense amplifier schematic diagram, as shown in Figure 1, the sense amplifier include a reference current branch and
One memory cell current branch exports " 0 " or " 1 " signal by comparing reference current branch and memory cell current branch.
In Fig. 1, the reference current branch includes four transistors M1, M2, M3 and M4, the memory cell current
Branch includes four transistors M5, M6, M7 and M8, and IO-TOP and IO-BOT is two input terminals, and Dob and Do is two outputs
End, VSS are ground terminal, and the inversion signal SAENb of enable signal exports enable signal SEN by phase inverter C, is provided to different
Transistor.In addition, further including the transistor M9 of the output end and transistor M4, M8 that connect the phase inverter C.In two input terminals
IO-TOP and IO-BOT output difference signals export " 0 " or " 1 " by comparing reference current branch and memory cell current branch
Signal.
But with the development of advanced technologies, supply voltage further declines, it is desirable that sense amplifier is to the anti-dry of noise
The ability of disturbing further increases, and especially when designing high speed reading circuit, how to increase the Differential Input of sense amplifier
Voltage is conducive to anti-interference and promotes speed ability.
Inventor after further research, proposes a kind of sense amplifier, between first input end and the first output end
First feedback amplifier is set, the second feedback amplifier is set between the second input terminal and second output terminal, described
One feedback amplifier is used to amplify the output signal of first output end, and second feedback amplifier is for amplifying institute
State the output signal of second output terminal；It is produced by sense amplifier in the differential signal that first input end and the second input terminal input
Raw output signal, output signal pass through the first feedback amplifier or the second feedback amplifier, pull down first input end and the
The voltage signal of input terminal one of in two input terminals is conducive to improve to increase the differential voltage of two input terminals
The anti-interference ability of sense amplifier and the speed ability for promoting sense amplifier, to realize setting for High sensitivity amplifier
Meter.
Referring to FIG. 2, the schematic diagram of its sense amplifier provided by one embodiment of the invention.As shown in Fig. 2, described
Sense amplifier, including the reference current branch 10 that is connected to each other and memory cell current branch 20, the reference current branch
10 there is first input end IO-TOP and the first output end DOb, the memory cell current branch 20 to have the second input terminal IO-
BOT and second output terminal DO, the first input end IO-TOP are directly defeated with described first by the first feedback amplifier 11
Outlet DOb is connected, the second input terminal IO-BOT by the second feedback amplifier 21 directly with the second output terminal
DO is connected, and first feedback amplifier 11 is used to amplify the output signal of the first output end DOb, and described second is anti-
Feedback amplifying circuit 21 is used to amplify the output signal of the second output terminal DO.
The reference current branch 10 is designed with 20 mirror symmetry of memory cell current branch.The reference current branch
Road includes four transistors；The first electrode of the first transistor T1 is connected with the first electrode of second transistor T2, and described
The second electrode of the second electrode of one transistor T1, the second electrode of the second transistor T2 and third transistor T3 connects
To second output terminal DO, the grid of the first transistor T1 is connected to enable signal SEN；The grid of the second transistor T2
Pole, third transistor T3 grid be connected to the first output end DOb；The first electrode of the third transistor T3 and the 4th crystal
The second electrode of pipe T4 is connected；The grid of the 4th transistor T4 is connected to first input end IO-TOP.
The memory cell current branch 20 includes four transistors；The first electrode of 5th transistor T5 and the 6th crystal
The first electrode of pipe T6 is connected, the second electrode of the 5th transistor T5, the second electrode of the 6th transistor T6 with
And the 7th the second electrode of transistor T7 be connected to the first output end DOb, the grid of the 5th transistor T5 is connected to enabled
Signal SEN；The grid of the 6th transistor T6, the grid of the 7th transistor T7 are connected to second output terminal DO；Described 7th
The first electrode of transistor T7 is connected with the second electrode of the 8th transistor T8；The grid of the 8th transistor T8 is connected to
Second input terminal IO-BOT, the first electrode of the 8th transistor T8 are connected with the first electrode of the 4th transistor T4
It connects.
The first of the first electrode of the first transistor T1, the first electrode of second transistor T2, the 5th transistor T5
Electrode, the 6th transistor T6 first electrode be connected.
The sense amplifier further includes the 9th transistor T9, and the grid of the 9th transistor T9 is connected to enable signal
The first electrode of SEN, the 9th transistor T9 are grounded, second electrode and the 4th transistor of the 9th transistor T9
The first electrode of T4, the first electrode of the 8th transistor T8 are connected.Wherein, the first electrode is in source electrode or drain electrode
One of electrode, the second electrode be source electrode or drain electrode in another electrode, if for example, the first electrode be source
Pole, then the second electrode is drain electrode；If the first electrode is drain electrode, the second electrode is source electrode.
In sense amplifier provided by the present invention, by first input end IO-TOP and the first output end DOb it
Between the first feedback amplifier 11 is set, between the second input terminal IO-BOT and second output terminal DO be arranged second feedback amplification
Circuit 21 generates small signal in the differential signal of first input end IO-TOP and the second input terminal IO-BOT by sense amplifier
Output signal, the output signal passes through the first feedback amplifier 11 or the second feedback amplifier 21, and drop-down is first defeated
The voltage signal for one of entering to hold in IO-TOP and the second input terminal IO-BOT input terminal, to increase two input terminals
Differential voltage is conducive to speed ability that is anti-interference and promoting sense amplifier, to realize setting for High sensitivity amplifier
Meter.
The effect of first feedback amplifier, 11 and second feedback amplifier 21 is amplification output signal, drop-down two
The voltage signal of input terminal one of in a input terminal, to increase the differential signal of two input terminals, to be conducive to
It improves the anti-interference of sense amplifier and promotes the speed ability of sense amplifier.The first feedback amplifier of the present invention couple 11
Or second feedback amplifier 21 actual circuit and be not specifically limited, be subject to and reach above-mentioned purpose.The present invention provides
The preferred physical circuit of one feedback amplifier and the second feedback amplifier, illustrates below by way of specific embodiment.
Referring to FIG. 3, the preferred circuit schematic diagram of its sense amplifier provided by one embodiment of the invention.Such as Fig. 3
It is shown, the sense amplifier, including the reference current branch 100 that is connected to each other and memory cell current branch 200, the ginseng
Examine current branch 100 has with first input end IO-TOP and the first output end DOb, the memory cell current branch 200
Second input terminal IO-BOT is straight by the first feedback amplifier 110 with second output terminal DO, the first input end IO-TOP
Connect and be connected with the first output end DOb, the second input terminal IO-BOT by the second feedback amplifier 210 directly with
The second output terminal DO is connected, and first feedback amplifier 110 is used to amplify the output of the first output end DOb
Signal, second feedback amplifier 210 are used to amplify the output signal of the second output terminal DO.
First feedback amplifier, 110 or second feedback amplifier 210 includes phase inverter and transistor, and described the
One feedback amplifier 110 includes the first phase inverter C1 and the tenth two-transistor P1, and second feedback amplifier 21 includes
Second phase inverter C2 and the 13rd transistor P2.The input terminal of the first phase inverter C1 is connected to the first output end DOb,
The output end of the first phase inverter C1 is connected to the grid of the tenth two-transistor P1, the leakage of the tenth two-transistor P1
Pole is connected to the first input end IO-TOP, and the source electrode of the tenth two-transistor P1 is connected to ground terminal VSS.Described second
The input terminal of phase inverter C2 is connected to the second output terminal DO, and the output end of the second phase inverter C2 is connected to the described tenth
The grid of three transistor P2, the drain electrode of the 13rd transistor P2 are connected to the second input terminal IO-BOT, and the described tenth
The source electrode of three transistor P2 is connected to ground terminal VSS.Preferably, the 12nd crystal P1 and the 13rd transistor P2 are equal
For PMOS tube.
The reference current branch 100 is designed with 200 mirror symmetry of memory cell current branch.The reference current
Branch 100 includes five transistors；The first electrode of the first transistor T1 is connected with the first electrode of second transistor T2, institute
State the second electrode, the second electrode of the second transistor T2 and the second electrode of third transistor T3 of the first transistor T1
It is connected to second output terminal DO, the grid of the first transistor T1 and the grid of the 5th transistor T5 are connected to enable signal
SEN；The grid of the second transistor T2, the grid of third transistor T3 are connected to the first output end DOb；The third crystal
The first electrode of pipe T3, the second electrode of the 4th transistor T4, the second electrode of the 5th transistor T5 are connected；Described
The grid of four transistor T4 is connected to first input end IO-TOP；The first first electrode of the 5th transistor T5 is connected to electricity
Source voltage VDD.
The memory cell current branch 200 includes five transistors；The first electrode of 6th transistor T6 is brilliant with the 7th
The first electrode of body pipe T7 is connected, the second electrode of the 6th transistor T6, the second electrode of the 7th transistor T7
And the 8th the second electrode of transistor T8 be connected to the first output end DOb, grid, the tenth crystal of the 6th transistor T6
The grid of pipe T10 is connected to enable signal SEN；The grid of the 7th transistor T7, the grid of the 8th transistor T8 are connected to
Second output terminal DO；First electrode, the second electrode of the 9th transistor T9 and the tenth crystal of the 8th transistor T8
The second electrode of pipe T10 is connected；The grid of the 9th transistor T9 is connected to the second input terminal IO-BOT, and the described 9th is brilliant
The first electrode of body pipe T9 is connected with the first electrode of the 4th transistor T4；The first electricity of the tenth transistor T10
Pole is connected to supply voltage VDD.
The first of the first electrode of the first transistor T1, the first electrode of second transistor T2, the 6th transistor T6
Electrode, the 7th transistor T7 first electrode be connected, and be connected to power vd D.
The sense amplifier further includes the 11st transistor T11, and the grid of the 11st transistor T11, which is connected to, to be made
The first electrode of energy signal SEN, the 11st transistor T11 are connected to ground terminal VSS, the 11st transistor T11's
Second electrode is connected with the first electrode of the 4th transistor T4, the first electrode of the 9th transistor T9.In addition,
In the present embodiment, the sense amplifier further includes a third phase inverter C3, is inputted in the input terminal of the third phase inverter C3
The inversion signal SAENb of enable signal exports enable signal SEN in the output end of the third phase inverter C3, with to described the
Grid, the tenth transistor of the grid of one transistor T1, the grid of the 5th transistor T5, the 6th transistor T6
The grid of the grid of T10 and the 11st transistor T11 provide enable signal SEN.Wherein, the first electrode is source electrode
Or electrode one of in drain electrode, the second electrode are another electrode in source electrode or drain electrode, if for example, described first
Electrode is source electrode, then the second electrode is drain electrode；If the first electrode is drain electrode, the second electrode is source electrode.
The work schedule of the sense amplifier includes three phases：
Pre-charging stage D1：It charges with the second input terminal to the sense amplifier first input end；
Voltage differential stage D2：Differential electrical is formed between the first input end and the second input terminal of the sense amplifier
Pressure difference；
Working stage D3：Sense amplifier is opened, output signal is amplified by the first feedback amplifier or the second feedback
Circuit is amplified so that the voltage differential of two input terminals is enhanced.
Specifically, in the pre-charging stage D1, to two input terminals of the sense amplifier：First input end IO-
TOP charges with the second input terminal IO-BOT, keeps the voltage of two input terminals equal, and maintains a predetermined level, example
Such as, the predetermined level is 0.8 times of voltage VDD.
In the voltage differential stage D2, the unlatching of memory (Bit Cell) and reference current (Reference
Two input terminals of normal work Current), sense amplifier gradually form differential electrical pressure difference, when to foot after a certain period of time,
Differential voltage reaches pre-designed value, opens sense amplifier immediately.The pre-designed value is to open the difference of sense amplifier
Component voltage value.
In the working stage D3, enable signal opens sense amplifier, and sense amplifier is started to work.Differential voltage
The size of (IO_BOT-IO_TOP) can determine the speed ability of sense amplifier.When given differential voltage, sensitive amplification
The inside of device makes output signal (DO/Dob) change by amplification.And this variation by the first feedback amplifier or
Second feedback amplifier is amplified (is amplified to PD_BOT/PD_TOP) again, pulls down one in two input terminal of sense amplifier
The voltage of a input terminal, to make the enhanced amplification of the voltage difference of two input terminals, to further increase the speed of sense amplifier
Spend performance.
The simulation waveform for the sense amplifier that Fig. 4 and Fig. 5 is provided by one embodiment of the invention.As shown in figure 4, storage
Device (Bit Cell) is high current, and the second ports input terminal IO_BOT are the cell accesses chosen, net current drop-down, the first input
It is reference voltage to hold the ports IO_TOP.Second input terminal IO_BOT port voltages are pulled down quickening amplification, are put in output signal DO
When greatly to a certain extent, the enhanced amplification of the second input terminal IO_BOT/ first input end IO_TOP differential voltages is formed just
Feedback, speed ability improve.
As shown in figure 5, memory (Bit Cell) is low current, the second ports input terminal IO_BOT are that the cell chosen leads to
Road, net current pull-up；The ports first input end IO_TOP are reference voltage.First input end IO_TOP port voltages, which are pulled down, to be added
Fast amplification, when output signal DOb signals are amplified to a certain degree, the second input terminal IO_BOT/ first input ends IO_
The enhanced amplification of TOP differential voltages, forms positive feedback, and speed ability improves.
In conclusion sense amplifier provided by the invention, is arranged first between first input end and the first output end
Feedback amplifier, is arranged the second feedback amplifier between the second input terminal and second output terminal, and first feedback is put
Big circuit is used to amplify the output signal of first output end, and second feedback amplifier is defeated for amplifying described second
The output signal of outlet；In the differential signal that first input end and the second input terminal input output letter is generated by sense amplifier
Number, output signal passes through the first feedback amplifier or the second feedback amplifier, pulls down first input end and the second input terminal
In one of input terminal voltage signal, to increase two input terminals differential voltage, be conducive to improve sensitive amplification
The anti-interference ability of device and the speed ability for promoting sense amplifier, to realize the design of High sensitivity amplifier.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair
Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims
Range.
Claims (13)
1. a kind of sense amplifier, which is characterized in that including the reference current branch that is connected to each other and memory cell current branch,
There is the reference current branch first input end and the first output end, the memory cell current branch to have the second input terminal
With second output terminal, the first input end is directly connected with first output end by the first feedback amplifier, institute
It states the second input terminal by the second feedback amplifier to be directly connected with the second output terminal, the first feedback amplification electricity
Road is used to amplify the output signal of first output end, and second feedback amplifier is for amplifying the second output terminal
Output signal.
2. sense amplifier as described in claim 1, which is characterized in that first feedback amplifier includes the first reverse phase
Device and the tenth two-transistor；Second feedback amplifier includes the second phase inverter and the 13rd transistor.
3. sense amplifier as claimed in claim 2, which is characterized in that the input terminal of first phase inverter is connected to described
First output end, the output end of first phase inverter are connected to the grid of the tenth two-transistor；12nd crystal
The drain electrode of pipe is connected to the first input end, and the source electrode of the tenth two-transistor is connected to ground terminal；Second reverse phase
The input terminal of device is connected to the second output terminal, and the output end of second phase inverter is connected to the 13rd transistor
Grid；The drain electrode of 13rd transistor is connected to second input terminal, and the source electrode of the 13rd transistor is connected to
Ground terminal.
4. sense amplifier as claimed in claim 3, which is characterized in that the tenth two-transistor and the 13rd crystal
Pipe is PMOS tube.
5. sense amplifier as described in claim 1, which is characterized in that the reference current branch and storage unit electricity
Flow Mirroring of tributary symmetric design.
6. sense amplifier as claimed in claim 5, which is characterized in that the reference current branch includes four transistors；
The first electrode of the first transistor is connected with the first electrode of second transistor, the second electrode of the first transistor, institute
The second electrode of the second electrode, third transistor of stating second transistor is connected to second output terminal, the first transistor
Grid is connected to enable signal；The grid of the second transistor, the grid of third transistor are connected to the first output end；It is described
The first electrode of third transistor is connected with the second electrode of the 4th transistor；The grid of 4th transistor is connected to
One input terminal.
7. sense amplifier as claimed in claim 6, which is characterized in that the memory cell current branch includes four crystal
Pipe；The first electrode of 5th transistor is connected with the first electrode of the 6th transistor, the second electrode of the 5th transistor,
Second electrode, the second electrode of the 7th transistor of 6th transistor are connected to the first output end, the 5th transistor
Grid be connected to enable signal；The grid of 6th transistor, the grid of the 7th transistor are connected to second output terminal；Institute
The first electrode for stating the 7th transistor is connected with the second electrode of the 8th transistor；The grid of 8th transistor is connected to
The first electrode of second input terminal, the 8th transistor is connected with the first electrode of the 4th transistor.
8. sense amplifier as claimed in claim 7, which is characterized in that the first electrode of the first transistor, the second crystalline substance
The first electrode of body pipe, the first electrode of the 5th transistor, the first electrode of the 6th transistor are connected.
9. sense amplifier as claimed in claim 8, which is characterized in that the sense amplifier further includes the 9th transistor,
The grid of 9th transistor is connected to enable signal, the first electrode ground connection of the 9th transistor, the 9th crystal
The second electrode of pipe is connected with the first electrode of the 4th transistor, the first electrode of the 8th transistor.
10. sense amplifier as claimed in claim 9, which is characterized in that the first electrode be source electrode or drain electrode in its
In an electrode, the second electrode be source electrode or drain electrode in another electrode.
11. such as sense amplifier according to any one of claims 1 to 10, which is characterized in that the work of the sense amplifier
Include three phases as sequential：
Pre-charging stage：It charges with the second input terminal to the sense amplifier first input end；
The voltage differential stage：Differential electrical pressure difference is formed between the first input end and the second input terminal of the sense amplifier；
Working stage：Sense amplifier is opened, output signal passes through the first feedback amplifier or the second feedback amplifier quilt
Amplification so that the voltage differential of two input terminals is enhanced.
12. sense amplifier as claimed in claim 11, which is characterized in that in the pre-charging stage, first input end with
The voltage of second input terminal is equal, and maintains a certain predetermined level.
13. sense amplifier as claimed in claim 11, which is characterized in that in the working stage, opened using enable signal
Open the sense amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710060981.2A CN108346442B (en) | 2017-01-25 | 2017-01-25 | Sensitive amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710060981.2A CN108346442B (en) | 2017-01-25 | 2017-01-25 | Sensitive amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108346442A true CN108346442A (en) | 2018-07-31 |
| CN108346442B CN108346442B (en) | 2020-12-15 |
Family
ID=62962425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710060981.2A Active CN108346442B (en) | 2017-01-25 | 2017-01-25 | Sensitive amplifier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108346442B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109559767A (en) * | 2018-11-28 | 2019-04-02 | 安徽大学 | The circuit structure of bitline leakage electric current is resisted using two sense amplifier technologies |
| CN113971970A (en) * | 2021-09-13 | 2022-01-25 | 华南理工大学 | Unipolar differential logic static random access memory cell and random access memory |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1455413A (en) * | 2002-05-02 | 2003-11-12 | 因芬尼昂技术股份公司 | Differencial current estimation circuit of estimating memory state of static random memory semiconductor memory cell unit and reading amplifying circuit |
| CN1505045A (en) * | 2002-11-29 | 2004-06-16 | ��ʽ���������Ƽ� | Semiconductor memory device and semiconductor integrated circuit |
| CN1971755A (en) * | 2005-11-21 | 2007-05-30 | 旺宏电子股份有限公司 | Differential sense amplifier circuit and method of enabling with clock signal through switching circuit |
| US7279939B2 (en) * | 2004-04-26 | 2007-10-09 | University Of Massachusetts | Circuit for differential current sensing with reduced static power |
| US20080048728A1 (en) * | 2006-08-25 | 2008-02-28 | Samsung Electronics Co., Ltd. | Stable sense amplifier |
| CN102543146A (en) * | 2012-01-19 | 2012-07-04 | 北京大学 | Flash sense amplifier |
| CN103973273A (en) * | 2013-01-24 | 2014-08-06 | 西安电子科技大学 | High-speed high-precision low-detuning fully differential dynamic comparator |
| CN105322946A (en) * | 2014-07-28 | 2016-02-10 | 株式会社索思未来 | Receiving circuit |
| CN105719680A (en) * | 2016-01-11 | 2016-06-29 | 安徽大学 | Novel high-speed self-starting sense amplifier circuit |
-
2017
- 2017-01-25 CN CN201710060981.2A patent/CN108346442B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1455413A (en) * | 2002-05-02 | 2003-11-12 | 因芬尼昂技术股份公司 | Differencial current estimation circuit of estimating memory state of static random memory semiconductor memory cell unit and reading amplifying circuit |
| CN1505045A (en) * | 2002-11-29 | 2004-06-16 | ��ʽ���������Ƽ� | Semiconductor memory device and semiconductor integrated circuit |
| US7279939B2 (en) * | 2004-04-26 | 2007-10-09 | University Of Massachusetts | Circuit for differential current sensing with reduced static power |
| CN1971755A (en) * | 2005-11-21 | 2007-05-30 | 旺宏电子股份有限公司 | Differential sense amplifier circuit and method of enabling with clock signal through switching circuit |
| US20080048728A1 (en) * | 2006-08-25 | 2008-02-28 | Samsung Electronics Co., Ltd. | Stable sense amplifier |
| CN102543146A (en) * | 2012-01-19 | 2012-07-04 | 北京大学 | Flash sense amplifier |
| CN103973273A (en) * | 2013-01-24 | 2014-08-06 | 西安电子科技大学 | High-speed high-precision low-detuning fully differential dynamic comparator |
| CN105322946A (en) * | 2014-07-28 | 2016-02-10 | 株式会社索思未来 | Receiving circuit |
| CN105719680A (en) * | 2016-01-11 | 2016-06-29 | 安徽大学 | Novel high-speed self-starting sense amplifier circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109559767A (en) * | 2018-11-28 | 2019-04-02 | 安徽大学 | The circuit structure of bitline leakage electric current is resisted using two sense amplifier technologies |
| CN109559767B (en) * | 2018-11-28 | 2021-11-16 | 安徽大学 | Circuit structure for resisting bit line leakage current by adopting two sensitive amplifier technologies |
| CN113971970A (en) * | 2021-09-13 | 2022-01-25 | 华南理工大学 | Unipolar differential logic static random access memory cell and random access memory |
Also Published As
| Publication number | Publication date |
|---|---|
| CN108346442B (en) | 2020-12-15 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104852727B (en) | The unclonable functional circuitry of physics of stability enhancing | |
| CN1971755B (en) | Differential sense amplifier circuit and method of enabling with clock signal through switching circuit | |
| CN104112466B (en) | A kind of sense amplifier applied to multiple programmable nonvolatile memory | |
| GB2203309A (en) | Sense amplifier for single-ended data sensing | |
| CN109448768A (en) | A kind of sensitive amplifier circuit with Low-offset | |
| CN104160453A (en) | Memory with redundant sense amplifier | |
| CN101834595A (en) | A three-valued adiabatic circuit and a T operation circuit of a single-power clock-controlled transmission gate | |
| CN1690721B (en) | high-speed sensing circuit and sensing method thereof | |
| CN108492840A (en) | sense amplifier | |
| CN108346442A (en) | sense amplifier | |
| KR20090026183A (en) | Sense Amplifier with Multiple Bits Sharing a Common Reference | |
| US20140269124A1 (en) | Memory with bit line current injection | |
| CN105913871A (en) | Multiple-time programmable non-volatile differential memory cells that can be integrated in registers | |
| CN102420002B (en) | Current mode sensitive amplifier | |
| CN104205650B (en) | Squelch detector apparatus and method based on phase inverter and switched capacitor | |
| CN103117080B (en) | Reading circuit | |
| CN104681055A (en) | High-speed current sensitive amplifier applied to static random access memory circuit | |
| US8223571B2 (en) | Generating and amplifying differential signals | |
| CN110120237B (en) | A STT-MRAM Sensing Circuit with Good Sensing Margin | |
| CN106898382B (en) | Reading circuit of memory and reading method thereof | |
| CN109257024A (en) | Sensitive amplifier circuit | |
| CN103871474B (en) | Read operation control signal generator and method of work thereof | |
| CN204697045U (en) | The data reading circuit of gas sensor and checkout gear | |
| CN104240746B (en) | Reading circuit and the memory storage with reading circuit | |
| Gupta et al. | Stability analysis of different dual-port SRAM cells in deep submicron region using N-Curve Method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |