CN101834595A - A three-valued adiabatic circuit and a T operation circuit of a single-power clock-controlled transmission gate - Google Patents

Abstract

The invention discloses a single-power clock clocked transmission gate ternary heat insulating circuit and a T computing circuit. The heat insulating circuit adopts a single-power clock technology to combine the high-information density characteristic of a multi-value logic circuit and the low-power consumption characteristic of a heat insulating circuit and is designed by utilizing a switch-signal algebraic system. The operation of the heat insulating circuit comprises two stages, wherein in the first stage, under the control of a clocked clock, a clocked NMOS (N-Mental-Oxide-Semiconductor) tube is used for sampling an input signal; and in the second stage, under the working rhythm of the single-power clock, a bootstrap-operation NMOS tube and a crossing storage structure are used for charging and discharging a load, and an NMOS tube grid leak parallel connection technology is utilized to ensure that the circuit realizes ternary input and output. The circuit has simpler structure and lower power consumption compared with a gate level circuit. When the working frequency is 16.7MHz, within 1.4 microseconds, the ternary heat insulating can averagely save the energy by about 66.4 percent compared with a DTCTGAL (Double Power Clock Ternary Clocked Transmission Gate Adiabatic Logic) circuit and averagely save the energy by about 85.1 percent compared with a ternary DPL (Double-Pass-Transistor Logic) circuit. The T computing circuit is designed on the basis of the heat insulating circuit, and any ternary logic circuit can be constructed through the T computing circuit.

Description

A three-valued adiabatic circuit and a T operation circuit of a single-power clock-controlled transmission gate

technical field

The invention relates to a three-value clock-controlled transmission gate adiabatic logic circuit, in particular to a single-power clock-controlled transmission gate three-value adiabatic circuit and a T operation circuit.

Background technique

Binary signal (0, 1) is widely used in digital circuits, and it is a signal representation with the least amount of information. In order to enhance the information processing capability of digital systems, the research on multi-valued logic circuits has become an important one of the directions. Due to the increase in the amount of information per wiring and the reduction in the number of input and output leads, the multi-valued logic circuit effectively improves the ability of a single line to carry information and the information density of an integrated circuit, thereby correspondingly increasing the time and space of a multi-valued logic circuit. The utilization rate and effectively reduce the production cost. However, most of the multi-valued logic circuits are implemented by binary elements at present, and its circuit structure is more complex and consumes more power than similar binary logic circuits.

The adiabatic circuit breaks through the limitations of the energy transmission mode in the traditional CMOS circuit. It uses the inductance in the power supply and the node capacitance in the circuit to form an LC oscillation circuit, so that the energy can be converted into each other in the form of magnetic energy and electrical energy, and effectively recycle the nodes in the circuit. The charge stored in the capacitor overcomes the disadvantage of low energy utilization rate caused by the one-time consumption of power supply → ground in traditional CMOS circuits, and greatly reduces energy loss. Among them, such as "Design of a DTCTGAL Circuit and Its Application" published by Journal of Semiconductors ("Design of a DTCTGAL Circuit and Its Application"), author: Wang Pengjun, Li Kunpeng, MeiFengna (Wang Pengjun , Li Kunpeng, Mei Fengna), who proposed a design scheme using dual-power clock technology to realize multi-valued adiabatic logic circuits. This design scheme effectively improves the integration of digital systems, and can significantly reduce the The power consumption of the multi-valued logic circuit, but with the increase of the number of clocks in this design scheme, the wiring complexity will increase, and the clock energy consumption of this design scheme is also relatively large.

Contents of the invention

The technical problem to be solved by the present invention is to provide a single-power clock clocked transmission gate ternary adiabatic circuit and T operation circuit that can significantly reduce the power consumption of the circuit, and has low wiring complexity and low clock energy consumption.

The technical scheme adopted by the present invention to solve the above-mentioned technical problems is: a single-power clock-controlled transmission gate ternary adiabatic circuit, which includes a first signal sampling circuit, a first complementary signal sampling circuit, a first interleaving memory structure unit, The first NMOS transistor and the second NMOS transistor, the signal input terminal of the first signal sampling circuit inputs the first input signal, and the first signal sampling circuit is connected to a clocked clock signal whose amplitude level corresponds to logic 2 , the clocked clock signal corresponding to the logic 2 of the amplitude level controls the first signal sampling circuit to sample the first input signal, and the signal output terminal of the first signal sampling circuit outputs the The sampling value corresponding to the first input signal, the signal input terminal of the first complementary signal sampling circuit inputs the first complementary input signal, and the first complementary signal sampling circuit is connected to the corresponding logic 2 of the amplitude level The clocked clock signal, the clocked clock signal whose amplitude level corresponds to logic 2 controls the first complementary signal sampling circuit to sample the complementary first input signal, and the first complementary signal The signal output end of the signal sampling circuit outputs the sampling value corresponding to the complementary first input signal, and the first interleaving memory structure unit has a first input end, a second input end, a first output end and a second At the output end, the first interleaved memory structure unit is connected to a power clock signal whose amplitude level corresponds to logic 2, and the gate of the first NMOS transistor is connected to the drain of the first NMOS transistor The common connection end is connected to the sampled value output by the signal output end of the first signal sampling circuit, and the common connection end is connected to the first input end of the first interleaved memory structure unit, the said The source of the first NMOS transistor is connected to the first output terminal of the first interleaved memory structure unit, and the gate of the second NMOS transistor is connected to the drain of the second NMOS transistor , its common connection end is connected to the sampling value output by the signal output end of the first complementary signal sampling circuit, and its common connection end is connected with the second input end of the first interleaved memory structure unit, so The source of the second NMOS transistor is connected to the second output end of the first interleaved memory structure unit, and the first output end of the first interleaved memory structure unit outputs the first output signal, so The second output terminal of the first interleaving memory structure unit outputs a complementary first output signal.

The first signal sampling circuit is mainly composed of a third NMOS transistor, the source of the third NMOS transistor is used as the signal input terminal of the first signal sampling circuit to input the first input signal, and the The gate of the third NMOS transistor is connected to the clocked clock signal whose amplitude level corresponds to logic 2, and the drain of the third NMOS transistor is output as the signal output terminal of the first signal sampling circuit The sampling value corresponding to the first input signal, the drain of the third NMOS transistor is respectively connected to the common connection end of the gate of the first NMOS transistor and the drain of the first NMOS transistor and The first input terminals of the first interleaving memory structure unit are connected; the first complementary signal sampling circuit is mainly composed of a fourth NMOS transistor, and the source of the fourth NMOS transistor is used as the first The signal input terminal of a complementary signal sampling circuit inputs the complementary first input signal, the gate of the fourth NMOS transistor is connected to the clocked clock signal whose amplitude level corresponds to logic 2, and the The drain of the fourth NMOS transistor is used as the signal output terminal of the first complementary signal sampling circuit to output the sampling value corresponding to the complementary first input signal, and the drain of the fourth NMOS transistor is respectively connected to the The gate of the second NMOS transistor is connected to the common connection end of the drain of the second NMOS transistor and the second input end of the first interleaved memory structure unit.

The first interleaving memory structure unit is mainly composed of a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a first PMOS transistor and a second PMOS transistor, and the fifth NMOS transistor The gate of the first interleaved memory structure unit is used as the first input terminal to be connected to the gate of the first NMOS transistor and the drain of the first NMOS transistor respectively, and input to the first NMOS transistor. The sampled value output by the signal output end of a signal sampling circuit, the drain of the fifth NMOS transistor is connected to the drain of the first PMOS transistor, and its common connection end is connected to the amplitude level Corresponding to the power clock signal of logic 2, the source of the fifth NMOS transistor is connected to the source of the first PMOS transistor, and its common connection terminal is used as the first interleaved memory structure unit of the first The output terminals are respectively connected to the source of the first NMOS transistor and the drain of the seventh NMOS transistor, and output the first output signal, and the source of the seventh NMOS transistor is connected to the power supply Ground, the gate of the seventh NMOS transistor is connected to the gate of the first PMOS transistor, and the gate of the first PMOS transistor is connected to the second gate of the first interleaved memory structure unit. The output terminal is connected, and the gate of the sixth NMOS transistor is used as the second input terminal of the first interleaved storage structure unit to be connected with the gate of the second NMOS transistor and the second NMOS transistor respectively. The drains of the transistors are connected to input the sampling value output by the signal output terminal of the first complementary signal sampling circuit, the drain of the sixth NMOS transistor is connected to the drain of the second PMOS transistor, Its common connection terminal is connected to the power clock signal corresponding to the logic 2 of the amplitude level, the source of the sixth NMOS transistor is connected to the source of the second PMOS transistor, and its common connection terminal is used as The second output end of the first interleaved memory structure unit is respectively connected to the source of the second NMOS transistor and the drain of the eighth NMOS transistor, and outputs the complementary first output signal, the source of the eighth NMOS transistor is connected to the power ground, the gate of the eighth NMOS transistor is connected to the gate of the second PMOS transistor, and the gate of the second PMOS transistor The pole is connected with the first output terminal of the first interleaving memory structure unit.

The first input signal, the complementary first input signal, the first output signal and the complementary first output signal are all 0, or 1, or 2, and the first When the input signal is 0, the first complementary input signal is 2, the first output signal is 0, and the first complementary output signal is 2; when the first input signal is 1 , the first complementary input signal is 1, the first output signal is 1, the first complementary output signal is 1; when the first input signal is 2, the complementary The first input signal is 0, the first output signal is 2, and the complementary first output signal is 0.

A single-power clock-controlled T operation circuit, which mainly consists of a transmission gate ternary adiabatic circuit, a ternary adiabatic word operation circuit, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, Composed of a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor and a sixteenth NMOS transistor, the transmission gate ternary adiabatic circuit includes a first signal sampling circuit, a first complementary signal sampling circuit, a first The interleaved storage structure unit, the first NMOS transistor and the second NMOS transistor, the signal input terminal of the first signal sampling circuit inputs the first input signal, and the first signal sampling circuit is connected to the logic corresponding to the amplitude level The clocked clock signal of 2, the clocked clock signal whose amplitude level corresponds to logic 2 controls the first signal sampling circuit to sample the first input signal, and the first signal sampling circuit The signal output end of the first input signal outputs the sampling value corresponding to the first input signal, the signal input end of the first complementary signal sampling circuit inputs the complementary first input signal, and the first complementary signal sampling circuit accesses the amplitude The value level corresponds to the clocked clock signal of logic 2, and the clocked clock signal corresponding to the amplitude level of logic 2 controls the first complementary signal sampling circuit to sample the complementary first input signal, The signal output terminal of the first complementary signal sampling circuit outputs the sampling value corresponding to the complementary first input signal, and the first interleaved memory structure unit has a first input terminal, a second input terminal, a second input terminal, and a second input terminal. An output terminal and a second output terminal, the first interleaved memory structure unit accesses a power clock signal whose amplitude level corresponds to logic 2, the gate of the first NMOS transistor is connected to the first NMOS transistor The drains of the transistors are connected, and its common connection end is connected to the sampling value output by the signal output end of the first signal sampling circuit, and its common connection end is connected to the first input of the first interleaved memory structure unit. terminal, the source of the first NMOS transistor is connected to the first output terminal of the first interleaved memory structure unit, the gate of the second NMOS transistor is connected to the second NMOS The drains of the transistors are connected, and its common connection end is connected to the sampling value output by the signal output end of the first complementary signal sampling circuit, and its common connection end is connected with the second cross memory structure unit of the first described first. The input terminals are connected, the source of the second NMOS transistor is connected to the second output terminal of the first interleaved memory structure unit, and the first output terminal of the first interleaved memory structure unit outputs The first output signal, the second output terminal of the first interleaving memory structure unit outputs a complementary first output signal;

The three-value adiabatic word operation circuit includes two first word operation circuit units and a second word operation circuit unit with the same circuit structure, and the first word operation circuit unit and the second word operation circuit unit are mainly composed of The second signal sampling circuit, the second complementary signal sampling circuit and the second interleaved memory structure unit are composed, the signal input terminal of the second signal sampling circuit inputs the second input signal, and the second signal sampling circuit is connected to The amplitude level corresponds to the clock control clock signal of logic 2, and the clock control signal of the amplitude level corresponds to logic 2 controls the second signal sampling circuit to sample the second input signal, and the The signal output end of the second signal sampling circuit outputs the sampling value corresponding to the second input signal, the signal input end of the second complementary signal sampling circuit inputs a complementary second input signal, and the second complementary The signal sampling circuit is connected to a clocked clock signal whose amplitude level corresponds to logic 2, and the clocked clock signal whose amplitude level corresponds to logic 2 controls the second complementary signal sampling circuit to the complementary first Two input signals are sampled, and the signal output terminal of the second complementary signal sampling circuit outputs the sampling value corresponding to the complementary second input signal, and the second interleaving memory structure unit has a first input terminal, The second input terminal, the first output terminal and the second output terminal, the second interleaved memory structure unit accesses the power clock signal whose amplitude level corresponds to logic 2, and the second interleaved memory structure unit’s The first input terminal inputs the sampling value output by the signal output terminal of the second signal sampling circuit, and the second input terminal of the second interleaving memory structure unit inputs the signal output of the second complementary signal sampling circuit The sampling value output by the end, the first output end of the second interleaved storage structure unit in the first word operation circuit unit is the complementary signal output end of the first word operation circuit unit, and the complementary first Two output signals, the second output end of the second interleaved memory structure unit in the first word operation circuit unit is the signal output end of the first word operation circuit unit, and outputs the second output signal, so The first output end of the second interleaved memory structure unit in the second word operation circuit unit is the signal output end of the second word operation circuit unit, and outputs a third output signal, and the first output signal of the second word operation circuit unit is The second output end of the second interleaved memory structure unit in the two word operation circuit unit is the complementary signal output end of the second word operation circuit unit, and outputs a complementary third output signal;

The drain of the ninth NMOS transistor, the drain of the tenth NMOS transistor and the drain of the twelfth NMOS transistor are connected, and the common connection terminal thereof is connected to the gate of the first NMOS transistor. pole is connected with the common connection terminal of the drain of the first NMOS transistor, and the gate of the ninth NMOS transistor is connected with the second interleaved memory structure unit in the first word operation circuit unit connected to the second output terminal of the first word operation circuit unit, and connected to the second output signal output by the second output terminal of the second interleaving memory structure unit in the first word operation circuit unit, the tenth NMOS transistor The source is connected to the drain of the eleventh NMOS transistor, and the gate of the tenth NMOS transistor is connected to the first interleaved memory structure unit of the first word operation circuit unit. One output terminal is connected to the complementary second output signal output by the first output terminal of the second interleaving memory structure unit in the first word operation circuit unit, and the eleventh NMOS transistor The gate of the gate is connected to the second output end of the second interleaving memory structure unit in the second word operation circuit unit, and connected to the first word operation circuit unit in the second word operation unit. The complementary third output signal output by the second output end of the two interleaving memory structure units, the gate of the twelfth NMOS transistor is connected with the second interleaving memory in the second word operation circuit unit The first output end of the memory structure unit is connected, and the third output signal output by the first output end of the second interleaving memory structure unit in the second word operation circuit unit is connected, and the first The sources of the nine NMOS transistors, the source of the eleventh NMOS transistor and the source of the twelfth NMOS transistor are respectively connected to the signal output terminals of the first signal sampling circuit; The drain of the thirteenth NMOS transistor, the drain of the fourteenth NMOS transistor and the drain of the sixteenth NMOS transistor are connected, and the common connection end is connected with the gate of the second NMOS transistor It is connected with the common connection end of the drain of the second NMOS transistor, and the gate of the thirteenth NMOS transistor is connected with the second interleaving memory structure unit in the first word operation circuit unit connected to the second output terminal of the first word operation circuit unit, and access the second output signal output by the second output terminal of the second interleaving memory structure unit in the first word operation circuit unit, and the fourteenth NMOS transistor The source is connected to the drain of the fifteenth NMOS transistor, and the gate of the fourteenth NMOS transistor is connected to the second interleaved memory structure unit in the first word operation circuit unit connected to the first output end of the first word operation circuit unit, and access the complementary second output signal output by the first output end of the second interleaving memory structure unit in the first word operation circuit unit, and the fifteenth The gate of the NMOS transistor and the second intersection in the second word operation circuit unit The second output end of the storage structure unit is connected to the complementary third output signal output by the second output end of the second interleaved memory structure unit in the second word operation circuit unit, so The gate of the sixteenth NMOS transistor is connected to the first output end of the second interleaved memory structure unit in the second word operation circuit unit, and connected to the second word operation circuit The third output signal output by the first output terminal of the second interleaving memory structure unit in the unit, the source of the thirteenth NMOS transistor, the source of the fifteenth NMOS transistor and the The sources of the sixteenth NMOS transistors are respectively connected to the signal output terminals of the first complementary signal sampling circuit.

The first signal sampling circuit is mainly composed of three third NMOS transistors, and the sources of the three third NMOS transistors are respectively used as signal input terminals of the first signal sampling circuit to input the first Input signal, the gates of the three described third NMOS transistors are connected, and connected to the clocked clock signal whose amplitude level corresponds to logic 2, and the drains of the three described third NMOS transistors are respectively As the signal output terminal of the first signal sampling circuit outputs the sampling value corresponding to the first input signal, the drains of the three third NMOS transistors are respectively connected to the source of the ninth NMOS transistor , the source of the eleventh NMOS transistor is connected to the source of the twelfth NMOS transistor; the first complementary signal sampling circuit is mainly composed of three fourth NMOS transistors, and the three fourth NMOS transistors The sources of the fourth NMOS transistors are respectively used as the signal input terminals of the first complementary signal sampling circuit to input the complementary first input signal, the gates of the three fourth NMOS transistors are connected, and The clocking clock signal corresponding to the logic 2 of the amplitude level is connected, and the drains of the three fourth NMOS transistors are respectively used as the signal output terminals of the first complementary signal sampling circuit to output the complementary The sampling value corresponding to the first input signal, the drains of the three fourth NMOS transistors are respectively connected to the source of the thirteenth NMOS transistor, the source of the fifteenth NMOS transistor and the The source of the sixteenth NMOS transistor is connected.

The second signal sampling circuit is mainly composed of a seventeenth NMOS transistor, and the source of the seventeenth NMOS transistor is used as the signal input terminal of the second signal sampling circuit to input the second input signal , the gate of the seventeenth NMOS transistor is connected to the clocking clock signal whose amplitude level corresponds to logic 2, and the drain of the seventeenth NMOS transistor is used as the second signal sampling circuit The signal output terminal of the said second input signal outputs the sampling value corresponding to said 17th NMOS transistor, and the drain of said 17th NMOS transistor is connected with the first input terminal of said second interleaved memory structure unit; said The second complementary signal sampling circuit is mainly composed of an eighteenth NMOS transistor, and the source of the eighteenth NMOS transistor is input to the complementary second input as the signal input terminal of the second complementary signal sampling circuit signal, the gate of the eighteenth NMOS transistor is connected to the clocking clock signal whose amplitude level corresponds to logic 2, and the drain of the eighteenth NMOS transistor is used as the second complementary signal The signal output end of the sampling circuit outputs the sampling value corresponding to the complementary second input signal, and the drain of the eighteenth NMOS transistor is connected to the second input end of the second interleaving memory structure unit .

The first interleaving memory structure unit is mainly composed of a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a first PMOS transistor and a second PMOS transistor, and the fifth NMOS transistor The gate of the first interleaved memory structure unit is connected to the gate of the first NMOS transistor and the drain of the first NMOS transistor respectively, and the fifth The drain of the NMOS transistor is connected to the drain of the first PMOS transistor, and its common connection terminal is connected to the power clock signal whose amplitude level corresponds to logic 2, and the source of the fifth NMOS transistor It is connected with the source of the first PMOS transistor, and its common connection terminal is used as the first output end of the first interleaved memory structure unit to be connected with the source of the first NMOS transistor and the The drains of the seventh NMOS transistor are connected to output the first output signal, the source of the seventh NMOS transistor is connected to the power ground, the gate of the seventh NMOS transistor is connected to the first The gate of the PMOS transistor is connected, the gate of the first PMOS transistor is connected with the second output terminal of the first interleaved memory structure unit, and the gate of the sixth NMOS transistor is used as the The second input terminal of the first interleaved memory structure unit is respectively connected to the gate of the second NMOS transistor and the drain of the second NMOS transistor, and the drain of the sixth NMOS transistor is connected to the drain of the second NMOS transistor. The drains of the second PMOS transistor are connected, and its common connection end is connected to the power clock signal whose amplitude level corresponds to logic 2, and the source of the sixth NMOS transistor is connected to the second PMOS transistor. The source of the PMOS transistor is connected, and its common connection terminal is used as the second output end of the first interleaved memory structure unit to be connected with the source of the second NMOS transistor and the drain of the eighth NMOS transistor respectively. are connected to each other, and output the complementary first output signal, the source of the eighth NMOS transistor is connected to the power ground, the gate of the eighth NMOS transistor is connected to the gate of the second PMOS transistor The poles are connected, and the gate of the second PMOS transistor is connected to the first output terminal of the first interleaved memory structure unit;

The circuit structure of the second interleaving storage structure unit is the same as that of the first interleaving storage structure unit, and the fifth NMOS transistor in the second interleaving storage structure unit is directly connected to the The signal output terminal of the second signal sampling circuit is connected, and the sampling value output by the signal output terminal of the second signal sampling circuit is connected, and the sixth NMOS transistor in the second interleaving memory structure unit is directly connected to the said second interleaved memory structure unit. connected to the signal output terminal of the second complementary signal sampling circuit, and connected to the sampled value output by the signal output terminal of the second complementary signal sampling circuit.

Compared with the prior art, the present invention has the advantage of adopting single-power clock technology, combining the high information density characteristics of multi-valued logic circuits and the low power consumption characteristics of adiabatic circuits, and utilizing the switch-signal algebraic system to perform ternary The design of the adiabatic circuit, the operation of the ternary adiabatic circuit of the present invention is divided into two stages, the first stage samples the input signal through the clocked NMOS tube under the control of the clocked clock; Under this condition, the load is charged and discharged through the NMOS tube of bootstrap operation and the cross memory structure, and the gate-drain parallel connection technology of the NMOS tube is used to realize the three-valued input and output of the circuit. The circuit structure is simpler than the gate-level circuit, and the power consumption is lower. Low, when the operating frequency is 16.7MHz, within 1.4 μs, the transmission gate ternary adiabatic circuit of the present invention saves about 66.4% of energy consumption on average compared with the existing DTCTGAL circuit; saves energy consumption on average compared with the existing ternary DPL circuit About 85.1%; T operation circuit is designed on the basis of transmission gate ternary adiabatic (TCTGAL) circuit, and any three-valued logic circuit can be constructed through T operation circuit, which can promote the development of multi-valued logic circuits.

Description of drawings

Fig. 1 a is the ternary adiabatic circuit diagram of single power clock clocked transmission gate of the present invention;

Figure 1b is a symbol for the circuit shown in Figure 1a;

Fig. 2 is the analog waveform schematic diagram of the single-power clock clocked transmission gate ternary adiabatic circuit of the present invention;

Fig. 3 a is the single power clock clocking T operation circuit diagram of the present invention;

Fig. 3b is the symbol of the circuit shown in Fig. 3a;

Figure 3c is a waveform diagram of the clocked clock signal and the power clock signal in Figure 3a;

Fig. 4 a is the three-valued adiabatic character operation circuit diagram one of the present invention;

Fig. 4 b is the circuit diagram two of the ternary adiabatic word operation of the present invention;

Figure 4c is a waveform diagram of the clocked clock signal and the power clock signal in Figure 4a and Figure 4b;

Fig. 5 is the analog waveform schematic diagram of T operation circuit of the present invention;

Fig. 6 is a schematic diagram of the comparison of transient energy consumption simulation waveforms between the transmission gate ternary adiabatic circuit of the present invention and the existing ternary DPL circuit and DTCTGAL circuit.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

The present invention utilizes switch-signal theory, on the basis of binary clocked transmission gate adiabatic logic (Clocked Transmission Gate Adiabatic Logic, CTGAL) circuit, adopts single power clock technology, proposes a new type of single power clock clocked transmission gate ternary Adiabatic logic (Ternary Clocked Transmission Gate Adiabatic Logic, TCTGAL) circuit, and realize the three-value adiabatic word operation circuit and T operation circuit, and finally through PSPICE simulation verification that the T operation circuit proposed by the present invention has correct logic function and remarkable low power consumption characteristic.

Embodiment one:

控制下，利用钟控NMOS管完成对输入信号的采样；第二级在幅值电平对应逻辑2的功率时钟信号Φ的工作节奏下，利用采样值和交叉存贮结构单元完成对输出负载赋值和能量回收，且输出信号和互补的输出信号可有效消除悬空。其中，Φ与

相位差180°，幅值均为V_DD，代表逻辑2，此外V_DD/2代表逻辑1，接电源地代表逻辑0。Based on the research on the adiabatic logic circuit of the binary clock-controlled transmission gate, the present invention proposes a three-valued adiabatic circuit of the single-power clock-controlled transmission gate. The three-valued adiabatic circuit of the transmission gate is divided into two stages of operation: the first stage Level corresponds to the clocked clock signal of logic 2

Under the control, the clocked NMOS transistor is used to complete the sampling of the input signal; the second stage uses the sampled value and the cross storage structure unit to complete the assignment of the output load under the working rhythm of the power clock signal Φ whose amplitude level corresponds to logic 2 And energy recovery, and the output signal and complementary output signal can effectively eliminate the floating. Among them, Φ and

The phase difference is 180°, and the amplitudes are both V _DD , representing logic 2, and V _DD /2 representing logic 1, and connecting to power ground represents logic 0.

控制第一互补信号采样电路2对互补的第一输入信号inb1进行采样，第一互补信号采样电路2的信号输出端输出互补的第一输入信号inb1对应的采样值Y1，第一交叉存贮结构单元3具有第一输入端31、第二输入端32、第一输出端33和第二输出端34，第一交叉存贮结构单元3接入幅值电平对应逻辑2的功率时钟信号Φ，第一NMOS晶体管M1的栅极与第一NMOS晶体管M1的漏极相连接，其公共连接端接入第一输入信号in1对应的采样值X1，其公共连接端并与第一交叉存贮结构单元3的第一输入端31相连接，第一NMOS晶体管M1的源极与第一交叉存贮结构单元3的第一输出端33相连接，第二NMOS晶体管M2的栅极与第二NMOS晶体管M2的漏极相连接，其公共连接端接入互补的第一输入信号inb1对应的采样值Y1，其公共连接端并与第一交叉存贮结构单元3的第二输入端32相连接，第二NMOS晶体管M2的源极与第一交叉存贮结构单元3的第二输出端34相连接，第一交叉存贮结构单元3的第一输出端33输出第一输出信号out1，第一交叉存贮结构单元3的第二输出端34输出互补的第一输出信号outb1，第一交叉存贮结构单元3的第一输出端33为该传输门三值绝热电路的信号输出端，第一交叉存贮结构单元3的第二输出端34为该传输门三值绝热电路的互补信号输出端。在此，第一NMOS晶体管M1和第二NMOS晶体管M2均为栅漏并接的NMOS晶体管，这两个栅漏并接的NMOS晶体管主要起到降压限幅的作用，可使得输出信号的波形幅值控制在合理的范围之内。The transmission gate ternary adiabatic circuit of the present invention is shown in Figure 1a, and its symbol is shown in Figure 1b, which includes a first signal sampling circuit 1, a first complementary signal sampling circuit 2, a first interleaving memory structure unit 3, a first An NMOS transistor M1 and a second NMOS transistor M2, the signal input terminal of the first signal sampling circuit 1 inputs the first input signal in1, and the first signal sampling circuit 1 is connected to a clocked clock signal whose amplitude level corresponds to logic 2 The amplitude level corresponds to the clocked clock signal of logic 2 Control the first signal sampling circuit 1 to sample the first input signal in1, the signal output terminal of the first signal sampling circuit 1 outputs the sampling value X1 corresponding to the first input signal in1, and the signal input terminal of the first complementary signal sampling circuit 2 inputs The complementary first input signal inb1, the first complementary signal sampling circuit 2 accesses the clocking clock signal whose amplitude level corresponds to logic 2 The amplitude level corresponds to the clocked clock signal of logic 2

Control the first complementary signal sampling circuit 2 to sample the complementary first input signal inb1, the signal output terminal of the first complementary signal sampling circuit 2 outputs the sampling value Y1 corresponding to the complementary first input signal inb1, the first interleaved storage structure The unit 3 has a first input terminal 31, a second input terminal 32, a first output terminal 33 and a second output terminal 34, and the first interleaving storage structure unit 3 accesses a power clock signal Φ whose amplitude level corresponds to logic 2, The gate of the first NMOS transistor M1 is connected to the drain of the first NMOS transistor M1, and its common connection end is connected to the sampling value X1 corresponding to the first input signal in1, and its common connection end is connected to the first interleaved memory structure unit 3 connected to the first input terminal 31, the source of the first NMOS transistor M1 is connected to the first output terminal 33 of the first interleaving memory structure unit 3, the gate of the second NMOS transistor M2 is connected to the second NMOS transistor M2 The drains are connected, and its common connection end is connected to the sampling value Y1 corresponding to the complementary first input signal inb1, and its common connection end is also connected to the second input end 32 of the first interleaving memory structure unit 3, and the second The source electrode of NMOS transistor M2 is connected with the second output terminal 34 of the first interleaving storage structure unit 3, and the first output terminal 33 of the first interleaving storage structure unit 3 outputs the first output signal out1, and the first interleaving storage structure unit 3 outputs the first output signal out1. The second output terminal 34 of structural unit 3 outputs the complementary first output signal outb1, and the first output terminal 33 of the first interleaving storage structural unit 3 is the signal output terminal of this transmission gate ternary adiabatic circuit, and the first interleaving storage The second output terminal 34 of the structural unit 3 is a complementary signal output terminal of the transmission gate ternary adiabatic circuit. Here, both the first NMOS transistor M1 and the second NMOS transistor M2 are NMOS transistors with parallel connection of gate and drain, and these two NMOS transistors with parallel connection of gate and drain mainly play the role of step-down and limiter, which can make the waveform of the output signal The amplitude is controlled within a reasonable range.

第三NMOS晶体管M3的漏极作为第一信号采样电路1的信号输出端输出第一输入信号in1对应的采样值X1，第三NMOS晶体管M3的漏极分别与第一NMOS晶体管M1的栅极与第一NMOS晶体管M1的漏极的公共连接端及第一交叉存贮结构单元3的第一输入端31相连接；第一互补信号采样电路2主要由一个第四NMOS晶体管M4组成，第四NMOS晶体管M4的源极作为第一互补信号采样电路2的信号输入端输入互补的第一输入信号inb1，第四NMOS晶体管M4的栅极接入幅值电平对应逻辑2的钟控时钟信号第四NMOS晶体管M4的漏极作为第一互补信号采样电路2的信号输出端输出互补的第一输入信号inb1对应的采样值Y1，第四NMOS晶体管M4的漏极分别与第二NMOS晶体管M2的栅极与第二NMOS晶体管M2的漏极的公共连接端及第一交叉存贮结构单元3的第二输入端32相连接。In this specific embodiment, the first signal sampling circuit 1 is mainly composed of a third NMOS transistor M3, the source of the third NMOS transistor M3 is used as the signal input terminal of the first signal sampling circuit 1 to input the first input signal in1, and the second The gate of the three NMOS transistors M3 is connected to the clocking clock signal whose amplitude level corresponds to logic 2

The drain of the third NMOS transistor M3 is used as the signal output terminal of the first signal sampling circuit 1 to output the sampling value X1 corresponding to the first input signal in1, and the drain of the third NMOS transistor M3 is respectively connected to the gate of the first NMOS transistor M1 and The common connection terminal of the drain of the first NMOS transistor M1 is connected with the first input terminal 31 of the first interleaving memory structure unit 3; the first complementary signal sampling circuit 2 is mainly made up of a fourth NMOS transistor M4, and the fourth NMOS The source of the transistor M4 is used as the signal input terminal of the first complementary signal sampling circuit 2 to input the complementary first input signal inb1, and the gate of the fourth NMOS transistor M4 is connected to a clocked clock signal whose amplitude level corresponds to logic 2 The drain of the fourth NMOS transistor M4 is used as the signal output terminal of the first complementary signal sampling circuit 2 to output the sampling value Y1 corresponding to the complementary first input signal inb1, and the drain of the fourth NMOS transistor M4 is connected to the second NMOS transistor M2 respectively. The gate is connected to the common connection terminal of the drain of the second NMOS transistor M2 and the second input terminal 32 of the first interleaved memory structure unit 3 .

In this specific embodiment, the first interleaving memory structure unit 3 is mainly composed of the fifth NMOS transistor M5, the sixth NMOS transistor M6, the seventh NMOS transistor M7, the eighth NMOS transistor M8, the first PMOS transistor P1 and the second PMOS transistor M5. Composed of transistor P2, the gate of the fifth NMOS transistor M5 is connected to the gate of the first NMOS transistor M1 and the drain of the first NMOS transistor M1 respectively as the first input terminal 31 of the first interleaved memory structure unit 3, and the input The sampled value X1 corresponding to the first input signal in1, the drain of the fifth NMOS transistor M5 is connected to the drain of the first PMOS transistor P1, and its common connection end is connected to a power clock signal Φ whose amplitude level corresponds to logic 2, The source electrode of the fifth NMOS transistor M5 is connected to the source electrode of the first PMOS transistor P1, and its common connection terminal is used as the first output end 33 of the first interleaved memory structure unit 3, respectively connected to the source electrode of the first NMOS transistor M1 and The drain of the seventh NMOS transistor M7 is connected to output the first output signal out1, the source of the seventh NMOS transistor M7 is connected to the power ground GND, the gate of the seventh NMOS transistor M7 is connected to the gate of the first PMOS transistor P1 connected, the gate of the first PMOS transistor P1 is connected with the second output terminal 34 of the first interleaving storage structure unit 3, and the gate of the sixth NMOS transistor M6 is used as the second input terminal of the first interleaving storage structure unit 3 32 are respectively connected to the gate of the second NMOS transistor M2 and the drain of the second NMOS transistor M2, input the sampling value Y1 corresponding to the complementary first input signal inb1, the drain of the sixth NMOS transistor M6 and the second PMOS transistor The drains of P2 are connected, and its common connection end is connected to the power clock signal Φ with an amplitude level corresponding to logic 2. The source of the sixth NMOS transistor M6 is connected to the source of the second PMOS transistor P2, and its common connection end As the second output terminal 34 of the first interleaved memory structure unit 3, it is respectively connected with the source electrode of the second NMOS transistor M2 and the drain electrode of the eighth NMOS transistor M8, and outputs a complementary first output signal outb1, and the eighth NMOS transistor M8 The source of the transistor M8 is connected to the power ground GND, the gate of the eighth NMOS transistor M8 is connected to the gate of the second PMOS transistor P2, and the gate of the second PMOS transistor P2 is connected to the first gate of the first interleaved memory structure unit 3. The output terminal 33 is connected.

In this specific embodiment, the first input signal in1, the complementary first input signal inb1, the first output signal out1, and the complementary first output signal outb1 are all 0, or 1, or 2, when the first input signal in1 When it is 0, the complementary first input signal inb1 is 2, the first output signal out1 is 0, and the complementary first output signal outb1 is 2; when the first input signal in1 is 1, the complementary first input signal inb1 is 1, the first output signal out1 is 1, the complementary first output signal outb1 is 1; when the first input signal in1 is 2, the complementary first input signal inb1 is 0, the first output signal out1 is 2, the complementary The first output signal outb1 is 0.

Figure 2 shows the simulation waveform of the transmission gate ternary adiabatic circuit, where the clocked clock signal is The power clock signal is Φ, and the first input signal in1 is respectively "2100220112...". In order to analyze the working characteristics of the transmission gate ternary adiabatic circuit, a clock cycle is divided into six time periods, namely T ₁ , T ₂ , ..., T ₆ .

电平下降，这时第三NMOS晶体管M3和第四NMOS晶体管M4均截止，输出采样值X1的输出端和输出采样值Y1的输出端处的电平基本保持不变。According to the analysis in Figure 2, the period T ₁ -T ₃ is the first-stage operation of the transmission gate ternary adiabatic circuit, which realizes the sampling of the first input signal in1 and the complementary first input signal inb1, so it can be called the sampling period , where during _T1 , when the first input signal in1=2 and the complementary first input signal inb1=0, the level at the signal input terminal and the clocking clock signal The level of the signal rises, while the level at the complementary signal input terminal and the level of the power clock signal Φ remain low. Therefore, both the third NMOS transistor M3 and the fourth NMOS transistor M4 are turned on, and the output sampled value X1 The level of the output terminal rises following the level at the signal input terminal, and the level of the output terminal that outputs the sampled value Y1 follows the level at the complementary signal input terminal and remains at zero level, because the gate-drain parallel connection of the first NMOS transistor M1 is When the voltage at the output terminal of the output sampled value X1 is higher than the threshold of the first NMOS transistor M1, there is a partial loss, so that the voltage at the output terminal of the output sampled value X1 is less than V _DD -V _TN (V _TN is the third NMOS transistor M3 threshold voltage); when the first input signal in1=1 and the complementary first input signal inb1=1, the levels at the output terminal of the output sample value X1 and the output terminal of the output sample value Y1 follow the first input signal in1 respectively and the complementary first input signal inb1 and charged to about V _DD /2. Since the power clock signal Φ is at zero level, the levels at the first output terminal and at the second output terminal both remain constant at zero level. Wherein, in order to reduce the voltage loss on the first NMOS transistor M1, the threshold conduction angle of the first NMOS transistor M1 can be reduced. During _T2 , the transmission gate ternary adiabatic circuit holds the sampled values of the first input signal and the sampled values of the complementary first input signal. During T ₃ , the clocked clock signal

When the level drops, both the third NMOS transistor M3 and the fourth NMOS transistor M4 are turned off, and the levels at the output terminal for outputting the sampled value X1 and the output terminal for outputting the sampled value Y1 remain basically unchanged.

保持低电平，功率时钟信号Φ电平开始升高，此时第三NMOS晶体管M3和第四NMOS晶体管M4均截止，使得输出采样值X1的输出端和输出采样值Y1的输出端均处于浮动状态。当第一输入信号in1＝2和互补的第一输入信号inb1＝0时，输出采样值X1的输出端处为浮动高电平，第五NMOS晶体管M5导通，第一输出端处的电平跟随功率时钟信号Φ上升，且当功率时钟信号Φ电平超过第一PMOS晶体管P1的阈值电压|V_TP|时，第一PMOS晶体管P1导通，从而使功率时钟信号Φ通过第五NMOS晶体管M5和第一PMOS晶体管P1组成的互补传输门对第一输出端进行充电，此时若第一输出端处的电平超过第八NMOS晶体管M8的阈值时，第八NMOS晶体管M8导通，使第二输出端处的电平箝位于电源地(0V)；当第一输入信号in1＝1和互补的第一输入信号inb1＝1时，第五NMOS晶体管M5和第六NMOS晶体管M6导通，第一输出端处的电平和第二输出端处的电平跟随功率时钟信号Φ上升，由于此时第一输出端处的电平受到第一信号采样电路输出采样值X1的输出端处的电平及第二输出端处的电平受到第一互补信号采样电路输出采样值Y1的输出端处的电平的制约，使得第一输出端处和第二输出端处的电平均为V_DD/2左右，M₃，M₄截止。T₅期间为保持期，电路输出保持在一定值不变，并由于此时第三NMOS晶体管M3和第四NMOS晶体管M4均截止，故输出采样值X1的输出端和输出采样值Y1的输出端处的电平保持原来的浮动状态。T₆期间为能量恢复期，第一输出端处的电平通过第五NMOS晶体管M5和第一PMOS晶体管P1组成的互补的传输门跟随功率时钟信号Φ下降到0V，电荷回收至功率时钟信号Φ。The period T ₄ -T ₆ is the second-stage operation of the transmission gate ternary adiabatic circuit, and the output follows the power clock signal Φ to realize energy injection and energy recovery. Among them, the _T4 period is the energy injection period (that is, the logic assignment period), and the clock control clock signal

Keeping the low level, the level of the power clock signal Φ begins to rise, and at this time the third NMOS transistor M3 and the fourth NMOS transistor M4 are both cut off, so that the output terminal of the output sample value X1 and the output terminal of the output sample value Y1 are floating state. When the first input signal in1=2 and the complementary first input signal inb1=0, the output terminal of the output sample value X1 is at a floating high level, the fifth NMOS transistor M5 is turned on, and the level at the first output terminal is Following the rise of the power clock signal Φ, and when the level of the power clock signal Φ exceeds the threshold voltage |V _TP | of the first PMOS transistor P1, the first PMOS transistor P1 is turned on, so that the power clock signal Φ passes through the fifth NMOS transistor M5 The complementary transmission gate formed with the first PMOS transistor P1 charges the first output terminal. At this time, if the level at the first output terminal exceeds the threshold value of the eighth NMOS transistor M8, the eighth NMOS transistor M8 is turned on, so that the first output terminal The levels at the two output terminals are clamped at the power ground (0V); when the first input signal in1=1 and the complementary first input signal inb1=1, the fifth NMOS transistor M5 and the sixth NMOS transistor M6 are turned on, and the second The level at the first output terminal and the level at the second output terminal follow the rise of the power clock signal Φ, because at this time the level at the first output terminal is affected by the level at the output terminal of the first signal sampling circuit outputting the sampled value X1 and the level at the second output end is restricted by the level at the output end of the first complementary signal sampling circuit outputting the sampling value Y1, so that the levels at the first output end and the second output end are both V _DD /2 Left and right, M ₃ , M ₄ cut off. During _T5 is the holding period, the circuit output remains constant at a certain value, and since the third NMOS transistor M3 and the fourth NMOS transistor M4 are all cut off at this time, the output terminal of the output sampled value X1 and the output terminal of the output sampled value Y1 The level at the place remains the original floating state. The period _T6 is the energy recovery period, and the level at the first output end drops to 0V following the power clock signal Φ through the complementary transmission gate composed of the fifth NMOS transistor M5 and the first PMOS transistor P1, and the charge is recovered to the power clock signal Φ .

Since the transmission gate ternary adiabatic circuit has a symmetrical structure, the first input signal in1=2 and the complementary first input signal inb1=0 are the same as when the first input signal in1=0 and the complementary first input signal inb1= 2 works the same way. In Figure 2, for ease of representation, V(in1) represents the level at the signal input terminal, V(x1) represents the level at the output terminal that outputs the sampling value corresponding to the first input signal, and V(inb1) represents the complementary signal The level at the input terminal, V(y1) indicates the level at the output terminal that outputs the sampling value corresponding to the complementary first input signal, V(out1) indicates the level at the first output terminal, and V(outb1) indicates Indicates the level at the second output.

Embodiment two:

As a multi-valued logical operation operator, T operation constitutes a complete system of multi-valued algebra (T operator algebra), which provides a new way for the research of multi-valued logic theory and application, and can use T operation circuit to construct T operation network to realize Arbitrary multi-valued logic circuit, so the present invention proposes a new T operation circuit clocked by a single power clock.

A single-power clock-controlled T operation circuit proposed by the present invention is shown in Fig. 3a, and its symbol is shown in Fig. 3b. circuit (including the first word operation circuit unit 5 and the second word operation circuit unit 6, as shown in Fig. 4a and Fig. 4b respectively), the ninth NMOS transistor M9, the tenth NMOS transistor M10, the eleventh NMOS transistor M11, the tenth The second NMOS transistor M12, the thirteenth NMOS transistor M13, the fourteenth NMOS transistor M14, the fifteenth NMOS transistor M15 and the sixteenth NMOS transistor M16 are composed.

幅值电平对应逻辑2的钟控时钟信号

控制第二互补信号采样电路52对互补的第二输入信号进行采样，第二互补信号采样电路的信号输出端输出互补的第二输入信号inb2对应的采样值Y2，第二交叉存贮结构单元53具有第一输入端54、第二输入端55、第一输出端56和第二输出端57，第二交叉存贮结构单元53接入幅值电平对应逻辑2的功率时钟信号Φ，第二交叉存贮结构单元53的第一输入端54输入第二输入信号in2对应的采样值X2，第二交叉存贮结构单元53的第二输入端55输入互补的第二输入信号inb2对应的采样值Y2，第二交叉存贮结构单元53的第一输出端56为第一文字运算电路单元5的互补信号输出端，输出互补的第二输出信号第二交叉存贮结构单元53的第二输出端57为第一文字运算电路单元5的信号输出端，输出第二输出信号⁰x⁰。图4b给出了第二文字运算电路单元6的电路图，第二文字运算电路单元6中的第二交叉存贮结构单元63的第一输出端66为第二文字运算电路单元6的信号输出端，输出第三输出信号²x²，第二文字运算电路单元6中的第二交叉存贮结构单元63的第二输出端67为第二文字运算电路单元6的互补信号输出端，输出互补的第三输出信号

图4c给出了第一文字运算电路单元和第二文字运算电路单元中的钟控时钟信号与功率时钟信号的波形示意图。三值绝热文字运算电路的真值表如表1所示，其中，

符号“∩”和“∪”分别表示取小运算和取大运算符号，如x∩y＝min(x，y)和x∪y＝max(x，y)。In this specific embodiment, the ternary adiabatic word operation circuit includes two first word operation circuit unit 5 and second word operation circuit unit 6 with the same circuit structure, as shown in Fig. 4a and Fig. 4b respectively. The first literal operation circuit unit 5 shown in Fig. 4 a is mainly made up of the second signal sampling circuit 51, the second complementary signal sampling circuit 52 and the second interleaved storage structure unit 53, and the signal input terminal of the second signal sampling circuit 51 inputs the first Two input signals in2, the second signal sampling circuit 51 accesses the clocked clock signal whose amplitude level corresponds to logic 2 The amplitude level corresponds to the clocked clock signal of logic 2 Control the second signal sampling circuit 51 to sample the second input signal in2, the signal output terminal of the second signal sampling circuit 51 outputs the sampling value X2 corresponding to the second input signal in2, and the signal input terminal of the second complementary signal sampling circuit 52 inputs For the complementary second input signal inb2, the second complementary signal sampling circuit 52 accesses a clocked clock signal whose amplitude level corresponds to logic 2

The amplitude level corresponds to the clocked clock signal of logic 2

Control the second complementary signal sampling circuit 52 to sample the complementary second input signal, the signal output terminal of the second complementary signal sampling circuit outputs the sampled value Y2 corresponding to the complementary second input signal inb2, the second interleaving memory structure unit 53 With a first input terminal 54, a second input terminal 55, a first output terminal 56 and a second output terminal 57, the second interleaved memory structure unit 53 accesses a power clock signal Φ whose amplitude level corresponds to logic 2, and the second The first input terminal 54 of the interleaved storage structure unit 53 inputs the sampling value X2 corresponding to the second input signal in2, and the second input terminal 55 of the second interleaved storage structure unit 53 inputs the sampling value corresponding to the complementary second input signal inb2 Y2, the first output end 56 of the second interleaved storage structure unit 53 is the complementary signal output end of the first word operation circuit unit 5, and outputs the second complementary output signal The second output terminal 57 of the second interleaving memory structure unit 53 is the signal output terminal of the first word operation circuit unit 5, and outputs a second output signal ⁰ x ⁰ . Fig. 4 b has provided the circuit diagram of the second word operation circuit unit 6, and the first output end 66 of the second interleaved memory structure unit 63 in the second word operation circuit unit 6 is the signal output end of the second word operation circuit unit 6 , output the third output signal ² x ² , the second output end 67 of the second interleaved memory structure unit 63 in the second word operation circuit unit 6 is the complementary signal output end of the second word operation circuit unit 6, and the output complementary third output signal

FIG. 4c shows a schematic diagram of the waveforms of the clock control clock signal and the power clock signal in the first word operation circuit unit and the second word operation circuit unit. The truth table of the three-valued adiabatic word operation circuit is shown in Table 1, where,

The symbols "∩" and "∪" respectively represent the symbol of taking the small operation and taking the big operation, such as x∩y=min(x, y) and x∪y=max(x, y).

Table 1 The truth table of the three-valued adiabatic word operation circuit

及第二文字运算电路单元6中的第二交叉存贮结构单元63的第二输出端67输出的互补的第三输出信号

第十二NMOS晶体管M12的栅极与第二文字运算电路单元6中的第二交叉存贮结构单元63的第一输出端66相连接，接入第二文字运算电路单元6中的第二交叉存贮结构单元63的第一输出端66输出的第三输出信号²x²，第九NMOS晶体管M9的源极、第十一NMOS晶体管M11的源极和第十二NMOS晶体管M12的源极分别与第一信号采样电路1的信号输出端相连接；第十三NMOS晶体管M13的漏极、第十四NMOS晶体管M14的漏极和第十六NMOS晶体管M16的漏极相连接，其公共连接端与第二NMOS晶体管M2的栅极与第二NMOS晶体管M2的漏极的公共连接端相连接，第十三NMOS晶体管M13的栅极与第一文字运算电路单元5中的第二交叉存贮结构单元53的第二输出端57相连接，接入第一文字运算电路单元5中的第二交叉存贮结构单元53的第二输出端57输出的第二输出信号⁰x⁰，第十四NMOS晶体管M14的源极与第十五NMOS晶体管M15的漏极相连接，第十四NMOS晶体管M14的栅极和第十五NMOS晶体管M15的栅极分别与第一文字运算电路单元5中的第二交叉存贮结构单元53的第一输出端56及第二文字运算电路单元6中的第二交叉存贮结构单元63的第二输出端67相连接，分别接入第一文字运算电路单元5中的第二交叉存贮结构单元53的第一输出端56输出的互补的第二输出信号

及第二文字运算电路单元6中的第二交叉存贮结构单元63的第二输出端67输出的互补的第三输出信号

第十六NMOS晶体管M16的栅极与另一个第二交叉存贮结构单元6的第一输出端66相连接，接入第二文字运算电路单元6中的第二交叉存贮结构单元63的第一输出端66输出的第三输出信号²x²，第十三NMOS晶体管M13的源极、第十五NMOS晶体管M15的源极和第十六NMOS晶体管M16的源极分别与第一互补信号采样电路2的信号输出端相连接。In this specific embodiment, the drain of the ninth NMOS transistor M9, the drain of the tenth NMOS transistor M10 and the drain of the twelfth NMOS transistor M12 are connected, and the common connection terminal thereof is connected to the gate of the first NMOS transistor M1 It is connected with the common connection end of the drain of the first NMOS transistor M1, and the gate of the ninth NMOS transistor M9 is connected with the second output end 57 of the second interleaved storage structure unit 53 in the first word operation circuit unit 5, The second output signal ⁰ x ⁰ output by the second output terminal 57 of the second interleaving memory structure unit 53 in the first word operation circuit unit 5 is connected, the source electrode of the tenth NMOS transistor M10 and the source electrode of the eleventh NMOS transistor M11 The drain is connected, and the gate of the tenth NMOS transistor M10 and the gate of the eleventh NMOS transistor M11 are respectively connected to the first output end 56 and the second interleaved memory structure unit 53 in the first word operation circuit unit 5. The second output end 67 of the second interleaving memory structure unit 63 in the word operation circuit unit 6 is connected, and the first output end 56 of the second interleave memory structure unit 5 in the first word operation circuit unit 5 is connected respectively. The complementary second output signal of the

And the complementary third output signal of the second output terminal 67 output of the second interleaving memory structure unit 63 in the second word operation circuit unit 6

The gate of the twelfth NMOS transistor M12 is connected with the first output end 66 of the second interleaving memory structure unit 63 in the second word operation circuit unit 6, and is connected to the second interleave in the second word operation circuit unit 6. The third output signal ² x ² output by the first output terminal 66 of the storage structure unit 63, the source of the ninth NMOS transistor M9, the source of the eleventh NMOS transistor M11 and the source of the twelfth NMOS transistor M12 are respectively Connected to the signal output terminal of the first signal sampling circuit 1; the drain of the thirteenth NMOS transistor M13, the drain of the fourteenth NMOS transistor M14 and the drain of the sixteenth NMOS transistor M16 are connected, and the common connection terminal The gate of the second NMOS transistor M2 is connected with the common connection end of the drain of the second NMOS transistor M2, and the gate of the thirteenth NMOS transistor M13 is connected with the second interleaving memory structure unit in the first word operation circuit unit 5 The second output terminal 57 of 53 is connected to the second output signal ⁰ x ⁰ output by the second output terminal 57 of the second interleaving memory structure unit 53 in the first word operation circuit unit 5, and the fourteenth NMOS transistor M14 The source of the source is connected to the drain of the fifteenth NMOS transistor M15, and the gate of the fourteenth NMOS transistor M14 and the gate of the fifteenth NMOS transistor M15 are respectively connected to the second interleaved memory in the first word operation circuit unit 5. The first output end 56 of the structure unit 53 and the second output end 67 of the second interleaved storage structure unit 63 in the second word operation circuit unit 6 are connected, respectively connected to the second crossover in the first word operation circuit unit 5. The complementary second output signal output by the first output terminal 56 of the storage structure unit 53

And the complementary third output signal of the second output terminal 67 output of the second interleaving memory structure unit 63 in the second word operation circuit unit 6

The gate of the sixteenth NMOS transistor M16 is connected to the first output end 66 of another second interleaving storage structure unit 6, and connected to the second interleaving storage structure unit 63 in the second word operation circuit unit 6. The third output signal ² x ² output by an output terminal 66, the source of the thirteenth NMOS transistor M13, the source of the fifteenth NMOS transistor M15 and the source of the sixteenth NMOS transistor M16 are respectively sampled with the first complementary signal The signal output terminals of circuit 2 are connected together.

表示，实际上Φ对于T运算电路而言是钟控时钟信号，而对于文字运算电路单元而言则是功率时钟信号，图3c给出了图3a中的钟控时钟信号和功率时钟信号的波形示意图。Here, since the power clock signal is delayed by half a clock period than the clocked clock signal, in order to ensure that the phase of the clocked clock signal is consistent with the input signal, and to ensure that the phase of the power clock signal is consistent with the output signal, the The clock control clock signal connected to the T operation circuit is represented by Φ, while the power clock signal connected is represented by

Indicates that actually Φ is a clocked clock signal for the T operation circuit, but it is a power clock signal for the word operation circuit unit. Figure 3c shows the waveforms of the clocked clock signal and the power clock signal in Figure 3a schematic diagram.

三个第四NMOS晶体管M4的栅极相连接，并接入幅值电平对应逻辑2的钟控时钟信号，三个第四NMOS晶体管M4的漏极分别作为第一互补信号采样电路2的信号输出端输出三个互补的第一输入信号各自对应的采样值，三个第四NMOS晶体管M4的漏极分别与第十三NMOS晶体管M13的源极、第十五NMOS晶体管M15的源极和第十六NMOS晶体管M16的源极相连接。In this specific embodiment, the first signal sampling circuit 1 is mainly composed of three third NMOS transistors M3, and the sources of the three third NMOS transistors M3 are respectively used as three signal input terminals of the first signal sampling circuit 1 to input The first input signal in ₀ , in ₁ , in ₂ , the gates of the three third NMOS transistors M3 are connected, and connected to the clocking clock signal whose amplitude level corresponds to logic 2, and the gates of the three third NMOS transistors M3 The drains are respectively used as the signal output terminals of the first signal sampling circuit 1 to output the sampling values corresponding to the three first input signals in ₀ , in ₁ , and in ₂ respectively, and the drains of the three third NMOS transistors M3 are connected to the ninth NMOS transistor M3 respectively. The source of the transistor M9, the source of the eleventh NMOS transistor M11 and the source of the twelfth NMOS transistor M12 are connected; the first complementary signal sampling circuit 2 is mainly composed of three fourth NMOS transistors M4, and the three fourth The sources of the NMOS transistor M4 serve as the three signal input terminals of the first complementary signal sampling circuit 2 to respectively input complementary first input signals

The gates of the three fourth NMOS transistors M4 are connected to each other, and the clocking clock signal whose amplitude level corresponds to logic 2 is connected, and the drains of the three fourth NMOS transistors M4 are respectively used as signals of the first complementary signal sampling circuit 2 The output outputs three complementary first input signals The drains of the three fourth NMOS transistors M4 are respectively connected to the sources of the thirteenth NMOS transistor M13 , the fifteenth NMOS transistor M15 and the sixteenth NMOS transistor M16 for corresponding sampled values.

第十七NMOS晶体管M17的漏极作为第二信号采样电路51的信号输出端输出第二输入信号in2对应的采样值X2，第十七NMOS晶体管M17的漏极与第二交叉存贮结构单元53的第一输入端54相连接；第二互补信号采样电路52主要由一个第十八NMOS晶体管M18组成，第十八NMOS晶体管M18的源极作为第二互补信号采样电路53的信号输入端输入互补的第二输入信号inb2，第十八NMOS晶体管M18的栅极接入幅值电平对应逻辑2的钟控时钟信号

第十八NMOS晶体管M18的漏极作为第二互补信号采样电路的信号输出端输出互补的第二输入信号inb2对应的采样值Y2，第十八NMOS晶体管M18的漏极与第二交叉存贮结构单元53的第二输入端55相连接。In this specific embodiment, taking the first word operation circuit unit 5 as an example, the second signal sampling circuit in the first word operation circuit unit 5 is mainly composed of a seventeenth NMOS transistor M17, the source of the seventeenth NMOS transistor M17 As the signal input terminal of the second signal sampling circuit 51, the second input signal in2 is input, and the gate of the seventeenth NMOS transistor M17 is connected to a clocked clock signal whose amplitude level corresponds to logic 2.

The drain of the seventeenth NMOS transistor M17 is used as the signal output terminal of the second signal sampling circuit 51 to output the sampled value X2 corresponding to the second input signal in2, and the drain of the seventeenth NMOS transistor M17 is connected to the second interleaved memory structure unit 53 The first input terminal 54 of the second complementary signal sampling circuit 52 is mainly composed of an eighteenth NMOS transistor M18, and the source of the eighteenth NMOS transistor M18 is used as the signal input terminal of the second complementary signal sampling circuit 53 to input complementary The second input signal inb2, the gate of the eighteenth NMOS transistor M18 is connected to the clocking clock signal whose amplitude level corresponds to logic 2

The drain of the eighteenth NMOS transistor M18 is used as the signal output terminal of the second complementary signal sampling circuit to output the sampled value Y2 corresponding to the complementary second input signal inb2, and the drain of the eighteenth NMOS transistor M18 is connected to the second interleaved storage structure The second input 55 of the unit 53 is connected.

In this specific embodiment, the specific circuit structure of the first interleaved memory structure unit 3 is as described in Embodiment 1, and the first output end of the first interleaved memory structure unit 3 is output by the signal output end of the T operation circuit. Output signal, the second output end of the first interleaved storage structure unit 3 is the output signal that the complementary signal output end of the T operation circuit outputs complementary, the second interleaved storage structure unit 53 (with the first word operation circuit unit 5 in the first The circuit structure of two interleaving storage structure unit 53 is example) and the circuit structure of the first interleaving storage structure unit 3, the fifth NMOS transistor M5 in the second interleaving storage structure unit 53 is directly connected with the second signal sampling circuit 51 Connected to the signal output terminal of the second signal sampling circuit 51, the sampling value X2 corresponding to the second input signal in2 output by the signal output terminal of the second signal sampling circuit 51 is connected, and the sixth NMOS transistor M6 in the second interleaving memory structure unit 53 is directly connected to the first The signal output terminals of the two complementary signal sampling circuits 52 are connected to each other to access the sampling value Y2 corresponding to the complementary second input signal inb2 output by the signal output terminals of the second complementary signal sampling circuit 52 .

In order to verify that the transmission gate ternary adiabatic circuit and the T operation circuit of the present invention have correct logic functions and remarkable low power consumption characteristics, computer simulation and analysis are carried out.

Using TSMC 0.25μm CMOS process device parameters, the width-to-length ratio of the NMOS transistor is W/L=0.36μm/0.24μm, the width-to-length ratio of the PMOS transistor is W/L=0.72μm/0.24μm, and the logic value is 0, 1, 2 The corresponding voltage values are 0V, 1.25V, 2.5V respectively. Figure 5 provides the transient characteristic curves of the ternary adiabatic word operation circuit and the T operation circuit, the signal sampling frequency is 16.7MHz, wherein x represents the gate control signal, and ⁰ x ⁰ is the signal output terminal output of the first word operation circuit unit 5 The second output signal of the second output signal, ² x ² is the third output signal output by the signal output end of the second word operation circuit unit 6, in ₀ , in ₁ , in ₂ are input signals of the T operation circuit, and T is the input signal of the T operation circuit output signal. If x=0, then ⁰ x ⁰ , ¹ x ¹ , ² x ² outputs are 2, 0, 0, in ₀ are strobed respectively, T=in ₀ ; if x=1, then ⁰ x ⁰ , ¹ x ¹ , ² x ² outputs are 0, 2, 0 respectively, in ₁ is strobed, T=in ₁ ; if x=2, then ⁰ x ⁰ , ¹ x ¹ , ² x ² outputs are 0, 0, 2, in ₂ is gated, T=in ₂ , where Thus, the gating control signal x=(0, 1, 2) corresponds to gating the first input signal (in ₀ , in ₁ , in ₂ ), which is sufficient to prove that the T operation circuit of the present invention has a correct logic function .

Fig. 6 has provided transmission gate ternary adiabatic (TCTGAL) circuit of the present invention and " Design of a DTCTGAL Circuit and Its Application " (" DTCTGAL circuit design and its application ") of Journal of Semiconductors (Journal of Semiconductors) (author: Wang The DTCTGAL (Double Power Clock Ternary Clocked Transmission GateAdiabatic Logic) circuit disclosed in Pengjun, Li Kunpeng, Mei Fengna (Wang Pengjun, Li Kunpeng, Mei Fengna)), the "Double Power Clock Ternary Clocked Transmission Gate Adiabatic Logic" circuit in "Journal of Zhejiang University" applied to multi-valued logic logic network synthesis "(Authors: Hang Guoqiang, Ren Hongbo) disclosed the transient energy consumption simulation waveform diagram of the ternary DPL (Double Pass-transistor Logic) circuit. Wherein, the transient energy consumption curve of the TCTGAL circuit of the present invention rises slowly in a wave form, the rising part of the curve reflects the energy injected into the circuit, the falling part indicates that the energy is recovered by the power supply, and the gradually rising phenomenon of the concave bottom of the curve reflects the energy consumption of the circuit ; The energy consumption of the ternary DPL circuit keeps rising with time. When the operating frequency is 16.7MHz, the TCTGAL circuit of the present invention saves about 66.4% of energy consumption on average compared with the DTCTGAL circuit and about 85.1% of the average energy consumption compared with the ternary DPL circuit within 1.4 μs.

Claims (8)

1. single-power clock clocked transmission gate ternary heat insulating circuit, it is characterized in that comprising first signal sample circuit, the first complementary signal sample circuit, the first intersection storage structure unit, first nmos pass transistor and second nmos pass transistor, the signal input part of described first signal sample circuit is imported first input signal, described first signal sample circuit inserts the clock clock signal of amplitude level counterlogic 2, the clock clock signal of described amplitude level counterlogic 2 is controlled described first signal sample circuit described first input signal is sampled, the signal output part of described first signal sample circuit is exported the sampled value of the described first input signal correspondence, the first complementary input signal of signal input part input of the described first complementary signal sample circuit, the described first complementary signal sample circuit inserts the clock clock signal of amplitude level counterlogic 2, the clock clock signal of described amplitude level counterlogic 2 is controlled the described first complementary signal sample circuit first input signal of described complementation is sampled, the signal output part of the described first complementary signal sample circuit is exported the sampled value of the first input signal correspondence of described complementation, the described first intersection storage structure unit has first input end, second input, first output and second output, the described first intersection storage structure unit inserts the power clock signal of amplitude level counterlogic 2, the grid of described first nmos pass transistor is connected with the drain electrode of described first nmos pass transistor, its public connecting end inserts the sampled value of the signal output part output of described first signal sample circuit, its public connecting end also is connected with described first first input end that intersects the storage structure unit, the source electrode of described first nmos pass transistor is connected with described first first output that intersects the storage structure unit, the grid of described second nmos pass transistor is connected with the drain electrode of described second nmos pass transistor, its public connecting end inserts the sampled value of the signal output part output of the described first complementary signal sample circuit, its public connecting end also is connected with described first second input that intersects the storage structure unit, the source electrode of described second nmos pass transistor is connected with described first second output that intersects the storage structure unit, described first first output that intersects the storage structure unit is exported first output signal, and described first second output that intersects the storage structure unit is exported the first complementary output signal.

2. a kind of single-power clock clocked transmission gate ternary heat insulating circuit according to claim 1, it is characterized in that described first signal sample circuit mainly is made up of the 3rd nmos pass transistor, the source electrode of described the 3rd nmos pass transistor is imported described first input signal as the signal input part of described first signal sample circuit, the grid of described the 3rd nmos pass transistor inserts the clock clock signal of described amplitude level counterlogic 2, the drain electrode of described the 3rd nmos pass transistor is exported the sampled value of the described first input signal correspondence as the signal output part of described first signal sample circuit, and the drain electrode of described the 3rd nmos pass transistor is connected with the public connecting end and described first first input end that intersects the storage structure unit of the drain electrode of described first nmos pass transistor with the grid of described first nmos pass transistor respectively; The described first complementary signal sample circuit mainly is made up of the 4th nmos pass transistor, the source electrode of described the 4th nmos pass transistor is imported first input signal of described complementation as the signal input part of the described first complementary signal sample circuit, the grid of described the 4th nmos pass transistor inserts the clock clock signal of described amplitude level counterlogic 2, the drain electrode of described the 4th nmos pass transistor is exported the sampled value of the first input signal correspondence of described complementation as the signal output part of the described first complementary signal sample circuit, and the drain electrode of described the 4th nmos pass transistor is connected with the public connecting end and described first second input that intersects the storage structure unit of the drain electrode of described second nmos pass transistor with the grid of described second nmos pass transistor respectively.

3. a kind of single-power clock clocked transmission gate ternary heat insulating circuit according to claim 1 and 2, it is characterized in that described first intersects the storage structure unit mainly by the 5th nmos pass transistor, the 6th nmos pass transistor, the 7th nmos pass transistor, the 8th nmos pass transistor, the one PMOS transistor and the 2nd PMOS transistor are formed, the grid of described the 5th nmos pass transistor is connected with the grid of described first nmos pass transistor and the drain electrode of described first nmos pass transistor respectively as described first first input end that intersects the storage structure unit, import the sampled value of the signal output part output of described first signal sample circuit, the drain electrode of described the 5th nmos pass transistor is connected with a described PMOS transistor drain, its public connecting end inserts the power clock signal of described amplitude level counterlogic 2, the source electrode of described the 5th nmos pass transistor is connected with the transistorized source electrode of a described PMOS, its public connecting end is connected with the source electrode of described first nmos pass transistor and the drain electrode of described the 7th nmos pass transistor respectively as described first first output that intersects the storage structure unit, and export described first output signal, the source electrode of described the 7th nmos pass transistor connects power supply ground, the grid of described the 7th nmos pass transistor is connected with the transistorized grid of a described PMOS, the transistorized grid of a described PMOS is connected with described first second output that intersects the storage structure unit, the grid of described the 6th nmos pass transistor is connected with the grid of described second nmos pass transistor and the drain electrode of described second nmos pass transistor respectively as described first second input that intersects the storage structure unit, import the sampled value of the signal output part output of the described first complementary signal sample circuit, the drain electrode of described the 6th nmos pass transistor is connected with described the 2nd PMOS transistor drain, its public connecting end inserts the power clock signal of described amplitude level counterlogic 2, the source electrode of described the 6th nmos pass transistor is connected with the transistorized source electrode of described the 2nd PMOS, its public connecting end is connected with the source electrode of described second nmos pass transistor and the drain electrode of described the 8th nmos pass transistor respectively as described first second output that intersects the storage structure unit, and export first output signal of described complementation, the source electrode of described the 8th nmos pass transistor connects power supply ground, the grid of described the 8th nmos pass transistor is connected with the transistorized grid of described the 2nd PMOS, and the transistorized grid of described the 2nd PMOS is connected with described first first output that intersects the storage structure unit.

4. a kind of single-power clock clocked transmission gate ternary heat insulating circuit according to claim 3, first output signal that it is characterized in that first input signal of described first input signal, described complementation, described first output signal and described complementation is 0 or 1 or 2, described first input signal is 0 o'clock, first input signal of described complementation is 2, described first output signal is 0, and first output signal of described complementation is 2; Described first input signal is 1 o'clock, and first input signal of described complementation is 1, and described first output signal is 1, and first output signal of described complementation is 1; Described first input signal is 2 o'clock, and first input signal of described complementation is 0, and described first output signal is 2, and first output signal of described complementation is 0.

5. single-power clock clock T computing circuit, it is characterized in that mainly by transmission gate tri-valued, thermal-insulating circuit, tri-valued, thermal-insulating literal computing circuit, the 9th nmos pass transistor, the tenth nmos pass transistor, the 11 nmos pass transistor, the tenth bi-NMOS transistor, the 13 nmos pass transistor, the 14 nmos pass transistor, the 15 nmos pass transistor and the 16 nmos pass transistor are formed, described transmission gate tri-valued, thermal-insulating circuit comprises first signal sample circuit, the first complementary signal sample circuit, the first intersection storage structure unit, first nmos pass transistor and second nmos pass transistor, the signal input part of described first signal sample circuit is imported first input signal, described first signal sample circuit inserts the clock clock signal of amplitude level counterlogic 2, the clock clock signal of described amplitude level counterlogic 2 is controlled described first signal sample circuit described first input signal is sampled, the signal output part of described first signal sample circuit is exported the sampled value of the described first input signal correspondence, the first complementary input signal of signal input part input of the described first complementary signal sample circuit, the described first complementary signal sample circuit inserts the clock clock signal of amplitude level counterlogic 2, the clock clock signal of described amplitude level counterlogic 2 is controlled the described first complementary signal sample circuit first input signal of described complementation is sampled, the signal output part of the described first complementary signal sample circuit is exported the sampled value of the first input signal correspondence of described complementation, the described first intersection storage structure unit has first input end, second input, first output and second output, the described first intersection storage structure unit inserts the power clock signal of amplitude level counterlogic 2, the grid of described first nmos pass transistor is connected with the drain electrode of described first nmos pass transistor, its public connecting end inserts the sampled value of the signal output part output of described first signal sample circuit, its public connecting end also is connected with described first first input end that intersects the storage structure unit, the source electrode of described first nmos pass transistor is connected with described first first output that intersects the storage structure unit, the grid of described second nmos pass transistor is connected with the drain electrode of described second nmos pass transistor, its public connecting end inserts the sampled value of the signal output part output of the described first complementary signal sample circuit, its public connecting end also is connected with described first second input that intersects the storage structure unit, the source electrode of described second nmos pass transistor is connected with described first second output that intersects the storage structure unit, described first first output that intersects the storage structure unit is exported first output signal, and described first second output that intersects the storage structure unit is exported the first complementary output signal;

Described tri-valued, thermal-insulating literal computing circuit comprises two the first literal computing circuit unit and the second literal computing circuit unit that circuit structure is identical, described first literal computing circuit unit and the described second literal computing circuit unit are all mainly by the secondary signal sample circuit, the second complementary signal sample circuit and the second intersection storage structure unit are formed, the signal input part of described secondary signal sample circuit is imported second input signal, described secondary signal sample circuit inserts the clock clock signal of amplitude level counterlogic 2, the clock clock signal of described amplitude level counterlogic 2 is controlled described secondary signal sample circuit described second input signal is sampled, the signal output part of described secondary signal sample circuit is exported the sampled value of the described second input signal correspondence, the second complementary input signal of signal input part input of the described second complementary signal sample circuit, the described second complementary signal sample circuit inserts the clock clock signal of amplitude level counterlogic 2, the clock clock signal of described amplitude level counterlogic 2 is controlled the described second complementary signal sample circuit second input signal of described complementation is sampled, the signal output part of the described second complementary signal sample circuit is exported the sampled value of the second input signal correspondence of described complementation, the described second intersection storage structure unit has first input end, second input, first output and second output, the described second intersection storage structure unit inserts the power clock signal of amplitude level counterlogic 2, described second first input end that intersects the storage structure unit is imported the sampled value of the signal output part output of described secondary signal sample circuit, described second second input that intersects the storage structure unit is imported the sampled value of the signal output part output of the described second complementary signal sample circuit, described second first output that intersects the storage structure unit in the described first literal computing circuit unit is the complementary signal output of the described first literal computing circuit unit, second output signal that output is complementary, described second second output that intersects the storage structure unit in the described first literal computing circuit unit is the signal output part of the described first literal computing circuit unit, export second output signal, described second first output that intersects the storage structure unit in the described second literal computing circuit unit is the signal output part of the described second literal computing circuit unit, export the 3rd output signal, described second second output that intersects the storage structure unit in the described second literal computing circuit unit is the complementary signal output of the described second literal computing circuit unit, the 3rd output signal that output is complementary;

The drain electrode of described the 9th nmos pass transistor, the drain electrode of described the tenth nmos pass transistor is connected with the drain electrode of described the tenth bi-NMOS transistor, its public connecting end is connected with the public connecting end of the drain electrode of described first nmos pass transistor with the grid of described first nmos pass transistor, the grid of described the 9th nmos pass transistor is connected with described second second output that intersects the storage structure unit in the described first literal computing circuit unit, insert second output signal of second output output of the described second intersection storage structure unit in the described first literal computing circuit unit, the source electrode of described the tenth nmos pass transistor is connected with the drain electrode of described the 11 nmos pass transistor, the grid of described the tenth nmos pass transistor is connected with described second first output that intersects the storage structure unit in the described first literal computing circuit unit, insert described second in the described first literal computing circuit unit and intersect second output signal of complementation of first output output of storage structure unit, the grid of described the 11 nmos pass transistor is connected with described second second output that intersects the storage structure unit in the described second literal computing circuit unit, insert described second in the described second literal computing circuit unit and intersect the 3rd output signal of complementation of second output output of storage structure unit, the grid of described the tenth bi-NMOS transistor is connected with described second first output that intersects the storage structure unit in the described second literal computing circuit unit, insert the 3rd output signal of first output output of the described second intersection storage structure unit in the described second literal computing circuit unit, the source electrode of described the 9th nmos pass transistor, the source electrode of the source electrode of described the 11 nmos pass transistor and described the tenth bi-NMOS transistor is connected with the signal output part of described first signal sample circuit respectively; The drain electrode of described the 13 nmos pass transistor, the drain electrode of described the 14 nmos pass transistor is connected with the drain electrode of described the 16 nmos pass transistor, its public connecting end is connected with the public connecting end of the drain electrode of described second nmos pass transistor with the grid of described second nmos pass transistor, the grid of described the 13 nmos pass transistor is connected with described second second output that intersects the storage structure unit in the described first literal computing circuit unit, insert second output signal of second output output of the described second intersection storage structure unit in the described first literal computing circuit unit, the source electrode of described the 14 nmos pass transistor is connected with the drain electrode of described the 15 nmos pass transistor, the grid of described the 14 nmos pass transistor is connected with described second first output that intersects the storage structure unit in the described first literal computing circuit unit, insert described second in the described first literal computing circuit unit and intersect second output signal of complementation of first output output of storage structure unit, the grid of described the 15 nmos pass transistor is connected with described second second output that intersects the storage structure unit in the described second literal computing circuit unit, insert described second in the described second literal computing circuit unit and intersect the 3rd output signal of complementation of second output output of storage structure unit, the grid of described the 16 nmos pass transistor is connected with described second first output that intersects the storage structure unit in the described second literal computing circuit unit, insert the 3rd output signal of first output output of the described second intersection storage structure unit in the described second literal computing circuit unit, the source electrode of described the 13 nmos pass transistor, the source electrode of described the 15 nmos pass transistor is connected with the signal output part of the described first complementary signal sample circuit respectively with the source electrode of described the 16 nmos pass transistor.

6. a kind of single-power clock clock T computing circuit according to claim 5, it is characterized in that described first signal sample circuit mainly is made up of three the 3rd nmos pass transistors, the source electrode of three described the 3rd nmos pass transistors is imported described first input signal as the signal input part of described first signal sample circuit respectively, the grid of three described the 3rd nmos pass transistors is connected, and insert the clock clock signal of described amplitude level counterlogic 2, the sampled value of the described first input signal correspondence is exported in the drain electrode of three described the 3rd nmos pass transistors respectively as the signal output part of described first signal sample circuit, the drain electrode of three described the 3rd nmos pass transistors respectively with the source electrode of described the 9th nmos pass transistor, the source electrode of described the 11 nmos pass transistor is connected with the source electrode of described the tenth bi-NMOS transistor; The described first complementary signal sample circuit mainly is made up of three the 4th nmos pass transistors, the source electrode of three described the 4th nmos pass transistors is imported first input signal of described complementation respectively as the signal input part of the described first complementary signal sample circuit, the grid of three described the 4th nmos pass transistors is connected, and insert the clock clock signal of described amplitude level counterlogic 2, the sampled value of the first input signal correspondence of described complementation is exported in the drain electrode of three described the 4th nmos pass transistors respectively as the signal output part of the described first complementary signal sample circuit, the drain electrode of three described the 4th nmos pass transistors respectively with the source electrode of described the 13 nmos pass transistor, the source electrode of described the 15 nmos pass transistor is connected with the source electrode of described the 16 nmos pass transistor.

7. according to claim 5 or 6 described a kind of single-power clock clock T computing circuits, it is characterized in that described secondary signal sample circuit mainly is made up of the 17 nmos pass transistor, the source electrode of described the 17 nmos pass transistor is imported described second input signal as the signal input part of described secondary signal sample circuit, the grid of described the 17 nmos pass transistor inserts the clock clock signal of described amplitude level counterlogic 2, the drain electrode of described the 17 nmos pass transistor is exported the sampled value of the described second input signal correspondence as the signal output part of described secondary signal sample circuit, and the drain electrode of described the 17 nmos pass transistor is connected with described second first input end that intersects the storage structure unit; The described second complementary signal sample circuit mainly is made up of the 18 nmos pass transistor, the source electrode of described the 18 nmos pass transistor is imported second input signal of described complementation as the signal input part of the described second complementary signal sample circuit, the grid of described the 18 nmos pass transistor inserts the clock clock signal of described amplitude level counterlogic 2, the drain electrode of described the 18 nmos pass transistor is exported the sampled value of the second input signal correspondence of described complementation as the signal output part of the described second complementary signal sample circuit, and the drain electrode of described the 18 nmos pass transistor is connected with described second second input that intersects the storage structure unit.

8. a kind of single-power clock clock T computing circuit according to claim 7, it is characterized in that described first intersects the storage structure unit mainly by the 5th nmos pass transistor, the 6th nmos pass transistor, the 7th nmos pass transistor, the 8th nmos pass transistor, the one PMOS transistor and the 2nd PMOS transistor are formed, the grid of described the 5th nmos pass transistor is connected with the grid of described first nmos pass transistor and the drain electrode of described first nmos pass transistor respectively as described first first input end that intersects the storage structure unit, the drain electrode of described the 5th nmos pass transistor is connected with a described PMOS transistor drain, its public connecting end inserts the power clock signal of described amplitude level counterlogic 2, the source electrode of described the 5th nmos pass transistor is connected with the transistorized source electrode of a described PMOS, its public connecting end is connected with the source electrode of described first nmos pass transistor and the drain electrode of described the 7th nmos pass transistor respectively as described first first output that intersects the storage structure unit, and export described first output signal, the source electrode of described the 7th nmos pass transistor connects power supply ground, the grid of described the 7th nmos pass transistor is connected with the transistorized grid of a described PMOS, the transistorized grid of a described PMOS is connected with described first second output that intersects the storage structure unit, the grid of described the 6th nmos pass transistor is connected with the grid of described second nmos pass transistor and the drain electrode of described second nmos pass transistor respectively as described first second input that intersects the storage structure unit, the drain electrode of described the 6th nmos pass transistor is connected with described the 2nd PMOS transistor drain, its public connecting end inserts the power clock signal of described amplitude level counterlogic 2, the source electrode of described the 6th nmos pass transistor is connected with the transistorized source electrode of described the 2nd PMOS, its public connecting end is connected with the source electrode of described second nmos pass transistor and the drain electrode of described the 8th nmos pass transistor respectively as described first second output that intersects the storage structure unit, and export first output signal of described complementation, the source electrode of described the 8th nmos pass transistor connects power supply ground, the grid of described the 8th nmos pass transistor is connected with the transistorized grid of described the 2nd PMOS, and the transistorized grid of described the 2nd PMOS is connected with described first first output that intersects the storage structure unit;

It is identical that described second circuit structure and described first that intersects the storage structure unit intersects the circuit structure of storage structure unit, the 5th nmos pass transistor in the described second intersection storage structure unit directly is connected with the signal output part of described secondary signal sample circuit, insert the sampled value of the signal output part output of described secondary signal sample circuit, the 6th nmos pass transistor in the described second intersection storage structure unit directly is connected with the signal output part of the described second complementary signal sample circuit, inserts the sampled value of the signal output part output of the described second complementary signal sample circuit.

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