CN102916687A - Ternary clock generator based on CMOS (complementary metal oxide semiconductor) technology - Google Patents

Abstract

The invention relates to design of a CMOS (complementary metal oxide semiconductor) of a ternary clock generator. As known to all, a ternary clock has the characteristic of multiple trigger edges and is favorable for reducing system power consumption when used for a digital circuit; but the survey found that the ternary clock is generated only by means of simulation through a signal source by simulation software at present, and no simple and practical circuits for generating the ternary clock exist domestic and overseas. The invention also relates to an encoding method which includes of taking a binary clock output from a quartz crystal oscillator as an input signal to encode the ternary clock of an output signal, then designing the ternary clock generator according to an encoding scheme and the transmission voltage switching theory, thereby filling the gap in the circuits for generating the ternary clock and improving practicality of the ternary clock. As simulation test proved, the ternary clock generator has correct functions. According to analysis results, the ternary clock generator is simple in structure, high in performance, favorable for improving practicability of the digital circuit, and capable of generating high-quality of ternary clock serving as the clock signal of a digital system so as to reduce power consumption of the system.

Description

Ternary clock generator based on CMOS technique

Technical field

The invention belongs to the design field of the ternary clock generator of integrated circuit.The present invention is based on the ternary clock generator of CMOS technique, and the high two-value clock of frequency stability that utilizes quartz oscillator to produce meets the ternary clock generator of real requirement as input signal design.This ternary clock generator can be applicable to digital circuitry, and the ternary clock signal of its output drives signal as the clock of sequential logical circuit.Because ternary clock has more triggerings edge in one-period, so digital circuitry can reduce the clock frequency of system, and then be conducive to reduce the power consumption of system in the situation that adopt ternary clock when keeping data processing speed constant.

Background technology

Because what ternary (digital) signal carried contains much information, so three value digital systems have plurality of advantages than the bi-level digital system.As, for certain logic function, the less and required signal transmssion line of the area of its integrated circuit is still less; For certain data volume, its memory cell that needs is [1] also still less.In addition, in three-valued logic, a lot of logics and arithmetical operation meeting are carried out sooner, just can finish [2] with operating procedure still less.Similarly, the ternary clock signal also has within a clock cycle than the more hopping edge of traditional two-value clock.The three value dual-edge triggers based on ternary clock that utilize these characteristics and design have the characteristics [3] such as circuit structure is simple and low in energy consumption.And the d type flip flop that triggers edge control that has that document [4] proposes also drives signal with ternary clock as clock.In document [5], also be used as the clock of trigger and put several control signals because ternary clock has comprised the amount of information of Duoing than the two-value clock.Can find out from above-mentioned research, the ternary clock signal has obtained practicable application and has demonstrated its superiority in digital circuit.Yet above-mentioned research has common characteristics, and the ternary clock that namely is used to all is to produce with the simulation software simulation, but not is produced by the circuit of reality.Make a general survey of Research Literature both domestic and external and find, there is no at present Research Literature and mention the Method and circuits that produces ternary clock, also, the ternary clock generator of a simple and stable practicality also is a vacancy at present.And clock is most important signal in the digital system, and the effect in sequence circuit is control and coordinates whole digital system and normally work.The two-value clock signal can produce [6] by the quartz crystal multivibrator, and ternary clock can only produce by the simulation software simulation at present.This will limit the practical application based on the digital system of ternary clock.For solving the problem in this practical application, the present invention utilizes the high two-value clock of the frequency stability of quartz oscillator generation as input signal, application transport voltage switch theoretical [7] designs the ternary clock generator from switching stage, circuit in the hope of design is simple, stability and high efficiency and practicality, to solve the problem of present shortage ternary clock generator.

List of references

[1]Dhande，A.P.，and Ingole，V.T.：Design of 3-Valued R-S & D flip-flops based on simple ternary gates，International journal of software engineering & knowledge engineering，2005，15，(2)，pp.411-417

[2]Moaiyeri，M.H.，Doostaregan，A.，Navi，K.：Design of energy-efficient and robust ternary circuits for nanotechnology，IET Circuits，Devices & Systems，2011，5，(4)，pp.285-296

[3] Hu Junfeng, Shen Jizhong, Yao Maoqun etc. Design of low power multivalued double-edge-triggered flip-flop [J]. journal of Zhejiang university (engineering version), 2005,39 (11): 1699-1702.

[4]E.Sipos，C.Miron：Master-Slave Ternary D Flip-Flap-Flops with Triggered Edges Control.IEEE International Conference on Automation Quality and Testing Robotics(AQTR)，Cluj-Napoca，Romania，May 2010，Vol.2，pp.1-6

[5]WU Xun-wei，SHEN Ji-zhong，CHEN Xie-xiong.CMOS multivalued flip-flops based on new presetting scheme and transmission function theory[J].Proc.IWST，Beijing，1994：74～77.

[6]

D.M.：Nonlinear analysis of a quartz multivibrator with a complementary switch，IEE Proceedings G Electronic Circuits and Systems，1985，132，(2)，pp.33-38

[7]Wu，X.，Prosser，F.：Design of ternary CMOS circuits based on transmission function theory，International Journal of Electronics，1988，65，(5)，pp.891-905

Summary of the invention

The objective of the invention is to invent a ternary clock generator that can produce efficient work simple in structure and meet real requirement.This ternary clock generator will satisfy following 5 requirements:

1) ternary clock of output meets the principle that takes full advantage of ternary (digital) signal;

2) circuit structure is simple, easily realization, and circuit working is stable with efficient;

3) the ternary clock signal satisfies the requirement about clock signal, namely high frequency and range stability should be arranged;

4) can produce the ternary clock signal that satisfies the requirement of high frequency environment for use;

5) the ternary clock signal that produces can satisfy the actual power requirement that uses.

Have the ternary clock generator of above characteristics for invention, the technical scheme of its design comprises following five steps:

A, define by the waveform of the principle that takes full advantage of ternary (digital) signal to ternary clock;

B, according to the definition of ternary clock the logical value of ternary clock is carried out binary-coding;

C, the binary-coding of all ternary clocks is analyzed, by the feasibility that coding is realized, found out practical coding;

D, by the transmission voltage switching theorem, the encoding scheme of above-mentioned practicality is set up the Mathematical Modeling of ternary clock generator;

E, according to the Mathematical Modeling of setting up, the CMOS technique that the application transport voltage switch is theoretical and ripe is designed the ternary clock generator.

Description of drawings

Fig. 1 is three kinds of typical waveforms of ternary clock.The two-value clock that Fig. 2 utilizes quartz oscillator to produce produces the cmos circuit figure of ternary clock, i.e. ternary clock generator cmos circuit figure as input signal.Fig. 3 is the ternary clock transient waveform figure that the ternary clock generator produces.Fig. 4 is based on the design flow diagram of the ternary clock generator of CMOS technique.

Embodiment

Below in conjunction with accompanying drawing technical scheme of the present invention is described further.

The definition of 1 ternary clock waveform

Because ternary clock (TCLK) has three kinds of level, namely { 0,1,2}, its typical waveform are just like Fig. 1 (a), (b) with three kinds of forms (c) for TCLK ∈.Can find out from three kinds of clock waveforms, in the one-period of ternary clock, all exist ascent stage and the decline stage of clock level.In the ternary clock waveform shown in Fig. 1 (a), its decline stage is directly to jump to 0 by 2; And in Fig. 1 (b), the ascent stage of ternary clock is directly to jump to 2 by 0.In fact, both of these case all still belongs to the characteristics of two-value clock in clock signal, does not also take full advantage of the characteristics that ternary (digital) signal contains much information.And in the waveform shown in Fig. 1 (c), the ascent stage of clock and decline stage all are three values, and this takes full advantage of the advantage that contains much information of ternary (digital) signal.In the ternary clock shown in Fig. 1 (c), have in the clock cycle that saltus step and twice time saltus step have four edges on twice.In the situation that clock frequency is identical, its edge number is than many one times of two-value clock.Therefore, the ternary clock generator of the present invention's design is take the ternary clock signal shown in the output map 1 (c) as design object.Specifically, the duration of 1 level of 1 level of 0 level in the ternary clock, ascent stage, 2 level and decline stage respectively accounted for for 1/4th cycles.

Three kinds of logical values of 2 pairs of ternary clocks are carried out binary coding

Present two-value clock signal as control bi-level digital circuit working is nearly all produced by quartz oscillator and provides.This is that it can produce the high periodic signal of frequency stability because of the distinctive physical property of quartz crystal.In order to obtain the high ternary clock of frequency stability, also must utilize this characteristic of quartz crystal.Therefore the present invention will utilize quartz oscillator to design the ternary clock generator, and namely { 0,2} designs the ternary clock generator as input signal with two-value clock CLK ∈.

Can be found out by the waveform shown in Fig. 1 (c), ternary clock has one of four states in one-period, for the convenience of problem analysis, regards 1 level and 1 level of decline stage of ascent stage as two different states here, be labeled as respectively+1 and-1.Because preamble mentions, therefore the present invention can be the one of four states coding of output signal with binary signal with the input signal of two-value clock as the ternary clock generator, this one of four states is respectively 0 ,+1,2 and-1.Because status number is 4, so need to come this one of four states is encoded with 2 binary signal BA.In theory, 4 states of 2 binary signal BA codings have 24 kinds of encoding schemes.But consider that output signal is that an order is fixed as 0 →+1 → 2 →-1 → 0 periodic signal, input signal is a two-value clock square wave, the circuit of design will be simple and easy to realize and the ternary clock exported does not have the requirements such as burr (burr is caused by the transition state in the circuit), therefore, have 4 kinds for the practicable scheme of these 4 output state codings with 2 binary signal BA, the specific coding scheme is as shown in table 1.

The binary coding of three kinds of logical values of table 1 ternary clock

3 set up the Mathematical Modeling of ternary clock generator by encoding scheme

Four kinds of encoding schemes of table 1 can be used for designing the ternary clock generator, and the ternary clock generator of design all has similar structure.The concrete ins and outs of ternary clock Generator Design are described as example take the scheme 0 of table 1 here.

Scheme 0 by table 1 can be found out, controlled the output of ternary clock logical zero by BA=02, operating characteristic by metal-oxide-semiconductor just need to have one in the control signal of BA=02 situation output high level so, so just can control with a metal-oxide-semiconductor logical zero of output ternary clock, its advantage is that the output internal resistance reaches minimum, only has the conducting resistance of a metal-oxide-semiconductor.According to above description, can list the switching stage function expression of the signal OUT0 of the control output logic 0 that is formed by two input signal BA, shown in (1).The ternary clock logical one is by BA=20 or 00 control output, and namely the ternary clock logical one is controlled output by A=0.If also control output logic 1 with a NMOS pipe, the switching stage function expression of this control signal OUT1 is suc as formula shown in (2) so.And ternary clock logic 2 is controlled output by BA=22, if control output logic 2 with a PMOS pipe, this just needs the control signal OUT2 of an output low level, and the switching stage logical function expression formula of this control signal OUT2 is suc as formula shown in (3).According to formula (1), (2) and (3) and transmission voltage switching theorem, can export the switching stage function expression of ternary clock TCLK, shown in (4).Here have any to pay special attention to, formula (1), (2) and (3) are based on the function expression of the switching stage of two-value.And formula (4) is the function expression of the switching stage of three values.These four Mathematical Modelings that the switching stage function expression is exactly the ternary clock generator.

OUT0＝A*B ^0.5#0* ^0.5B (1)

OUT1＝1*A ^0.5#0* ^0.5A (2)

$\mathrm{OUT}2=\stackrel{\‾}{B}{*}^{0.5}A\#2*A^{0.5}---\left(3\right)$

TCLK＝0* ^1.5(OUT0)#1* ^1.5(OUT1)#2*(OUT2) ^0.5 (4)

4 design the ternary clock generator according to the application of mathematical model correlation theory

Realize the Mathematical Modeling of ternary clock generator, at first will realize 2 binary codings in the table 1, this need to have 2 binary signal BA.Because existing input signal A is a two-value clock signal of being exported by quartz oscillator, therefore, also need obtain the 2nd binary signal B.Two-value clock signal A is that order to occur be 0 → 2 → 0 periodic square wave to a level value.By finding out in the encoding scheme of table 1, signal B also is a periodic square wave, and its frequency is signal A half, and therefore can carry out two divided-frequency to signal A can obtain signal B.According to Mathematical Modeling and the transmission voltage switching theorem of ternary clock generator, namely can realize the ternary clock generator with metal-oxide-semiconductor again, the cmos circuit figure of ternary clock generator as shown in Figure 2.In Fig. 2, the frequency-halving circuit module can consist of with a d type flip flop commonly used.The circuit of formation control signal OUT0, OUT1 and OUT2 consists of with common metal-oxide-semiconductor.Form ternary clock signal TCLK and need to adopt the metal-oxide-semiconductor with multistage unlatching threshold value, but according to the characteristic of metal-oxide-semiconductor transmission voltage, can not adopt the metal-oxide-semiconductor for the two-stage threshold value of ternary circuit here, and adopt common metal-oxide-semiconductor.Specifically, the logical zero of ternary clock and 1 is by common NMOS management and control system output, and logic 2 is exported by common control pmos system.Concrete cmos circuit figure as shown in Figure 2.Adopt common metal-oxide-semiconductor to realize that the ternary clock generator mainly contains two large advantages: the first, the manufacturing process of integrated circuit can reduce greatly, has saved manufacturing cost; The second, owing to having adopted the metal-oxide-semiconductor of single threshold value, reduced the threshold value of part metal-oxide-semiconductor, the switching speed of circuit can greatly improve, and therefore the frequency response of circuit also can be improved greatly.

In a word, the clock signal CLK of quartz crystal multivibrator is linked to each other with the input signal A of cmos circuit shown in Figure 2, can form the ternary clock generator, its output signal is exactly the ternary clock signal that meets designing requirement.

Experimental verification and analysis:

1 simulation result and analysis based on the ternary clock generator of CMOS technique

The below analyzes the work behavior of ternary clock generator.Because consisting of the triggering edge of the d type flip flop of frequency divider among Fig. 2 determines, be that trailing edge triggers, therefore, the state transitions behavior of two binary signals that the output signal B of frequency divider and two-value clock CLK=A form also will be determined, namely 00 → 02 → 20 → 22 → 00, be the periodically circuit of logical value of output that an error-free attitude can self-starting.Like this, scheme 0 output that the ternary clock generator also will periodically be pressed table 1 and these states are the ternary clock logical value one to one, can obtain so the periodic ternary clock signal shown in Fig. 1 (c).

Be the correctness of the work of simulation ternary clock generator, the below adopts the CMOS technological parameter of HSPICE software and TSMC180nm that the ternary clock generator is simulated, and the output loading of ternary clock generator is 30fF during simulation.Simulate the transient waveform of gained as shown in Figure 3, the CLK among the figure, namely A is the two-value clock of simulation quartz crystal multivibrator output, and B is the output waveform behind the clock CLK two divided-frequency, and TCLK is the ternary clock of ternary clock generator output.By transient waveform shown in Figure 3 as can be known, the ternary clock generator can produce the periodic ternary clock that meets designing requirement, and its frequency is input two-value clock frequency half.The analog result of Fig. 3 shows, the ternary clock generator of the present invention's design has correct logic function, can reliablely and stablely work.Should be noted, although the frequency of ternary clock of output only is the two-value clock half, within the identical time, can provide the triggering edge with the trigger sensitivity of two-value clock equal number.Because the quartz crystal with various resonance frequencys has been made into the product of standardization and seriation, so the ternary clock generator that proposes according to the present invention, the ternary clock of various different frequencies all can obtain easily.

The below analyzes amplitude and the frequency stability of the ternary clock that the ternary clock generator produces, and whether satisfies it as the instructions for use of clock signal with the ternary clock of clear and definite its generation.The requirement of clock signal is should have high range stability also will have high frequency stability.By switching stage circuit shown in Figure 2 as can be known, because the logical value of the ternary clock of output is that formation is directly exported through the metal-oxide-semiconductor of a conducting in the ternary (digital) signal source, output level is more stable and the output internal resistance is also minimum, so the stability of its amplitude is higher, and can provide larger power output.Because the frequency of oscillation of quartz crystal has high frequency stability, and the frequency of ternary clock depends on the frequency of the two-value clock of input, so the frequency stability of ternary clock is the same with the quartz crystal multivibrator almost, has high frequency stability.This shows, the ternary clock generator of the present invention's design has satisfied the instructions for use of clock signal aspect fixed ampllitude and frequency stabilization two fully, and larger power output can be provided.

2 sum up

The advantage that the present invention contains much information by taking full advantage of ternary (digital) signal has been determined the waveform morphology of ternary clock, has proposed to produce a kind of design of ternary clock, and then according to the transmission voltage switching theorem it has been carried out the design of switching stage.The ternary clock generator architecture of the present invention design is simple, and except in order to the d type flip flop of realizing divide-by-two function, remaining circuit has partly used 11 common metal-oxide-semiconductors altogether in the circuit.According to the HSPICE analog result as can be known, the ternary clock generator has correct logic function, the circuit stable and reliable operation.The ternary clock of output meets the requirement that clock signal has high amplitude and frequency stability, and its frequency is the same with the frequency of two-value clock, has controllability and accuracy.In addition, the saltus step of the two-value clock of the saltus step of the ternary clock of generation and input has clear and definite corresponding relation, and this is the basis of providing convenience synchronously between ternary clock and the two-value clock.The service condition of the ternary clock generator of the present invention's design is low, and the outside only need provide a quartz oscillator commonly used and ternary (digital) signal source to get final product, and very easily carries out practical application.The design of the generation ternary clock that the present invention proposes also can be used for the two-value clock is converted to ternary clock.Be pointed out that at last the ternary clock of other forms such as Fig. 1 (a) and waveform (b), also can produce with the method for designing that the present invention proposes.

Claims (1)

1. based on the ternary clock generator of CMOS technique, the two-value clock of quartz oscillator output is changed into the ternary clock that meets designing requirement.Design ternary clock generator comprises following five steps:

A, define by the waveform of the requirement that takes full advantage of ternary (digital) signal to ternary clock;

B, according to the definition of ternary clock the logical value of ternary clock is carried out binary-coding;

C, the binary-coding of all ternary clocks is analyzed, by the realizability of coding, found out practical coding;

D, by the transmission voltage switching theorem, the encoding scheme of above-mentioned practicality is set up the Mathematical Modeling of ternary clock generator;

E, according to the Mathematical Modeling of setting up, the CMOS technique that the application transport voltage switch is theoretical and ripe is designed the ternary clock generator.

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