CN109559767B - Circuit structure for resisting bit line leakage current by adopting two sensitive amplifier technologies - Google Patents
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Abstract
本发明公开了一种采用两个灵敏放大器技术抵抗位线泄漏电流的电路结构，能够有效的抵抗由于位线泄漏电流引起的SRAM读取效率的降低和读失败，增强SRAM的稳定性同时降低了读延迟，提高了SRAM的读取速度。相比于现有技术中的SA电路，本方案提供的电路结构拥有更加稳定的性能，读数据所需要的时间在不同的位线泄漏电流下，变化不是很大，有很好的稳定性；并且在读取数据的时间上相比于现有技术中的SA电路，抗泄漏电流能力提高了412.8％，读取时间减少了290％。
The invention discloses a circuit structure that adopts two sense amplifier technologies to resist bit line leakage current, which can effectively resist the reduction of SRAM read efficiency and read failure caused by bit line leakage current, enhance the stability of SRAM and reduce the The read latency increases the read speed of the SRAM. Compared with the SA circuit in the prior art, the circuit structure provided by this solution has more stable performance, and the time required to read data does not vary greatly under different bit line leakage currents, and has good stability; In addition, compared with the SA circuit in the prior art, the anti-leakage current capability is improved by 412.8% in the time of reading data, and the reading time is reduced by 290%.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a circuit structure for resisting bit line leakage current by adopting two sensitive amplifier technologies.
Background
The scaled-down Complementary Metal Oxide Semiconductor (CMOS) process technology improves the performance of a CMOS transistor while reducing its area. But with the thinning of the CMOS transistor gate oxide, this will increase the gate leakage current. The reduction of the process also causes the threshold voltage of the CMOS tube to be reduced, and the lower the threshold voltage is, the larger the sub-threshold leakage current is. The increasing leakage current will affect the operation of the SRAM. The leakage current on the bit line will cause a prolonged read time and, in a serious case, will cause errors in reading data.
To effectively solve the problem caused by the bit line leakage current, the circuit structure solutions can be summarized as the following two methods:
(1) bit line leakage current compensation
The effect of leakage current on data reading can be reduced by adding a compensation circuit on both bit lines. As shown in fig. 1, the structure of the BLC circuit; the method mainly comprises the steps that two bit lines are precharged and are charged to a high level, then word lines are opened, and due to the fact that leakage current and working current exist on the bit lines, the voltage of the low end of the bit lines is lower, and the voltage of the high end of the bit lines is higher. The influence of the leakage current on the reading speed is reduced to the minimum, and the reading speed is accelerated. However, there is a disadvantage in that a read error is caused when the leakage current is larger than the operating current.
(2) Changing cell structure
Another method is to reduce leakage by changing the structure of the cell, and the area occupied by the memory cell is the largest in the entire SRAM. Read and write separation or the use of single ended input output is sometimes employed to reduce leakage. As shown in fig. 2, a single-ended 5T structure is used, and the single-ended 5T is modified on a conventional 4T memory cell, whose complementary bit line is generated by an inverter. As the ends of the memory '0' and the memory '1' in the memory cell are actually connected with only one bit line, the leakage current generated on the bit line is small, and meanwhile, in order to solve the influence of the leakage current on the bit line of the 5T cell, a bit line auxiliary circuit is added. After the bit line drops to a certain voltage due to the leakage current, the bit line is compared with a set reference voltage, and if the bit line is greater than the reference voltage, secondary charging is performed to compensate the voltage drop. Although the area using 5T is smaller than 6T, the use of the second precharge increases the read time and also increases the power consumption.
Disclosure of Invention
The invention aims to provide a circuit structure for resisting bit line leakage current by adopting two sensitive amplifier technologies, which can effectively resist the reduction of SRAM reading efficiency and reading failure caused by the bit line leakage current, enhance the stability of the SRAM, reduce the reading delay and improve the reading speed of the SRAM.
The purpose of the invention is realized by the following technical scheme:
a circuit structure for resisting bitline leakage current using two sense amplifier technology, comprising: the circuit comprises a first sensitive amplifier, a second sensitive amplifier, a first output selection circuit, a second output selection circuit and a voltage follower circuit, wherein the first output selection circuit and the second output selection circuit are composed of transmission gates; the first sensitive amplifier, the first output selection circuit, the voltage follower circuit, the second output selection circuit and the second sensitive amplifier are sequentially connected, and the output selection circuit formed by the transmission gates is also connected with the second sensitive amplifier;
comparing the voltages of the two bit lines by the first sense amplifier, wherein the output voltage difference signal controls the first output selection circuit to select one end with higher voltage of the bit line to be connected with the voltage follower circuit, the bit line has higher voltage, namely smaller leakage current, and meanwhile, the first output selection circuit also inputs the selected voltage of the bit line into a differential input tube of the second sense amplifier; and then, the voltage of the followed bit line generates two following voltages through the voltage following circuit and is selected through the second output selection circuit, one following voltage is output to the other differential input tube of the second sense amplifier, and the second sense amplifier compares the bit line voltage with the following voltage to generate an output signal to finish data reading.
Compared with the SA circuit in the prior art, the circuit structure provided by the invention has more stable performance, the time required for reading data does not change greatly under different bit line leakage currents, and the circuit structure has good stability; compared with the SA circuit in the prior art, the leakage current resistance is improved by 412.8% in the time of reading data, and the reading time is reduced by 290%.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a BLC circuit according to the background art of the present invention;
fig. 2 is a schematic structural diagram of a 5T leakage compensation circuit according to the background art of the present invention;
fig. 3 is a schematic diagram of a circuit structure for resisting bit line leakage current by using two sense amplifier technologies according to an embodiment of the present invention, (a) a conventional voltage-type sense amplifier SA1, (b) a conventional voltage-type sense amplifier SA2, (c) a designed voltage follower circuit, (d) an output selection circuit composed of transmission gates, and (e) a whole structure diagram of a designed circuit for resisting bit line leakage current by using two sense amplifier technologies;
FIG. 4 is a schematic diagram of the operation of the voltage follower circuit;
FIG. 5 is a timing waveform diagram of a circuit configuration according to an embodiment of the present invention; where P and PR are signals of the voltage follower circuit, PRE is a precharge signal, WL is a word line signal, SEN is an enable signal of the first sense amplifier (SA1), SEN1 is an enable signal of the second sense amplifier (SA 2). (simulation conditions: Corner: TT; Temperature: 27 ℃; VDD: 0.8V);
FIG. 6 is a graph of the time required to read data at different bit line leakage currents in a conventional SRAM circuit using a prior art SA circuit and using the circuit structure provided by the present invention, in a 16nm FinFET process provided by an embodiment of the present invention;
FIG. 7 is a graph comparing the maximum leakage capability experienced by a conventional SRAM circuit using a prior art SA circuit and a circuit structure provided by the present invention at different process corners for a 16nm FinFET process provided by an embodiment of the present invention;
fig. 8 is a diagram of the maximum bitline leakage current that can be tolerated in a conventional SRAM circuit at different process corners using a prior art SA circuit and using the circuit structure provided by the present invention in a 16nm finfet process according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a circuit structure (hereinafter referred to as a 2SA circuit structure) for resisting bit line leakage current by using two sense amplifier technologies, as shown in fig. 3, the circuit structure mainly includes: the circuit comprises a first sensitive amplifier, a second sensitive amplifier, a first output selection circuit, a second output selection circuit and a voltage follower circuit, wherein the first output selection circuit and the second output selection circuit are composed of transmission gates; the first sense amplifier (SA1), the first output selection circuit, the voltage follower circuit, the second output selection circuit and the second sense amplifier (SA2) are sequentially connected, and the first output selection circuit is further connected with the second sense amplifier.
The two sense amplifiers are both conventional Sense Amplifiers (SA), and the structures thereof are shown in fig. 3(a) -3 (b), the conventional SA amplifies an input voltage difference formed in a circuit by adopting an input-output separation structure, and meanwhile, the output does not affect the input, so that the bit line voltage does not change due to the reading of the SA. The voltage follower circuit is shown in fig. 3(C), and is composed of 8 PMOS transistors (P0-P7) and 4 capacitors (C1-C4), wherein: the grid electrode of the PMOS pipe P0 is connected with a signal P (low level signal), and the source electrode is connected with VDD; the gate of the PMOS transistor P1 is connected with a signal PR (high level signal), and the source is connected with an output signal V of the first output selection circuit; one end of the capacitor C1 is connected with the drain electrodes of the PMOS tube P0 and the PMOS tube P1, and the other end is connected with the drain electrode of the PMOS tube P2 and the source electrode of the PMOS tube P3; the grid electrode of the PMOS tube P2 is connected with a signal P, and the source electrode is connected with the drain electrode of the PMOS tube P4; the grid electrode of the PMOS tube P3 is connected with the signal PR, two ends of the capacitor C3 are respectively connected with the drain electrode and VSS of the PMOS tube P3, and the voltage of the drain electrode of the PMOS tube P3 is marked as V2; the grid electrode of the PMOS pipe P6 is connected with a signal P, and the source electrode is connected with VDD; the grid of the PMOS pipe P5 is connected with the signal PR, and the source is connected with the output signal V of the first output selection circuit; one end of the capacitor C2 is connected with the drain electrodes of the PMOS tube P5 and the PMOS tube P6 and the source electrode of the PMOS tube P4, and the other end is connected with the source electrode of the PMOS tube P7; the grid electrode of the PMOS tube P4 is connected with a signal P, and the drain electrode is connected with the source electrode of the PMOS tube P2; the gate of the PMOS transistor P7 is connected to the signal PR, the two ends of the capacitor C4 are respectively connected to the drain and VSS of the PMOS transistor P7, and the voltage at the drain of the PMOS transistor P7 is marked as V1. The structure of the output selection circuit composed of transmission gates is shown in fig. 3 (d); the circuit structure of two sense amplifier technologies to combat bit line leakage current is shown in fig. 3 (e).
In the embodiment of the invention, the voltages of two bit lines (BL and BLB) are compared through a first sense amplifier (SA1), and an output voltage difference signal controls a first output selection circuit to select one end with a higher bit line voltage to be connected with a voltage follower circuit so as to follow the corresponding bit line, wherein the bit line has a higher voltage, namely a smaller leakage current, and meanwhile, the first output selection circuit also inputs the selected bit line voltage to a differential input tube of a second sense amplifier; then, the voltage of the followed bit line generates two following voltages through a voltage following circuit, and after the two following voltages are selected through a second output selection circuit, one of the two following voltages is output to the other differential input tube of the second sense amplifier; the second sense amplifier (SA2) compares the bit line voltage with the follow voltage to generate an output signal, and data reading is completed. The selection of the follower voltage is determined by reading 0 and reading 1, when reading 0, the result of comparing the follower voltage V2 output by the selection voltage follower circuit with the bit line voltage is taken as an output, and the output is 0 because the bit line voltage is greater than V2. When reading 1, the following voltage V1 output by the voltage following circuit is selected as the output compared with the bit line voltage, and the output is 1 because the bit line voltage is less than V1. The value of V1 is the value of the follower circuit input plus the voltage value across the capacitor C2, the value of V2 is the value of the follower circuit input minus the voltage value across the capacitor C1, the values of the capacitors C1 and C2 are VDD-V4, VDD is the power supply voltage, and V4 is a set constant value and is set to 700mv through tests.
Specifically, the circuit operation is divided into the following three phases: a bit line pre-charging stage, a leakage current checking stage and a data reading stage; wherein:
1) bit line precharge stage: at this stage the bit line voltage is precharged to the supply Voltage (VDD) and then the precharge circuit is turned off; at this time, the leakage current existing on the bit line can reduce the voltage of the bit line, and the voltage reduced by the two bit lines is different due to different leakage currents, so that a voltage difference caused by the leakage current is formed; at this stage, the memory cell word line is low and the memory cell is not turned on.
2) And (3) a leakage current checking stage: after a voltage difference with a certain magnitude caused by leakage current is formed, the first sense amplifier (SA1) is turned on to amplify the bit line voltage difference, and according to different polarities of the voltage difference, an output signal can control the output selection circuit to select one end with higher bit line voltage (namely, smaller leakage current) to be connected with the voltage follower circuit; at this stage, the memory cell is still not opened.
3) A data reading stage: selecting one of the two bit lines with smaller leakage voltage to follow according to the output signal of the first sense amplifier (SA1) and using the voltage as the input voltage of the second sense amplifier (SA 2); when the voltage of the memory cell word line rises to a high voltage, the memory cell is turned on, the discharge of the bit line connected to the node storing data "0" in the memory cell starts to increase, and the leakage current of the bit line is Ileakage0The bit line discharge current is IcellAt this time, the total discharge current is Ileakage0+Icell(ii) a And the leakage current of the bit line connected to the node storing the data "1" in the memory cell is Ileakage1(ii) a The follower circuit outputs a voltage; and selecting V1 or V2 as the following voltage output according to the storage content of the memory cell, opening a second sense amplifier (SA2) after the bit line discharges to a certain voltage, comparing the bit line voltage with the following voltage, generating an output signal, and finishing data reading.
To explain the principle of the voltage follower circuit more clearly, we give a simulation example, as shown in fig. 4. The operation of the voltage follower circuit can be divided into two phases. In the first stage, as shown in FIG. 4(a), V4 is a fixed voltage 700mv, the P signal is low, and the PR signal is high. At this time, the transistors P2, P4, P5, P7 are turned on, and the transistors P1, P3, P6, P8 are turned off. VDD is transmitted to one end of a capacitor C1 through a PMOS pipe P1, and 700mv voltage is transmitted to the other end of the capacitor C1 through another PMOS pipe P4. At this time, a voltage difference of 100mv is formed across the capacitor C1. Similarly, a voltage difference of-100 mv is formed across the capacitor C2. In the second stage, as shown in fig. 4(b), the transistors P2, P4, P5, P7 are turned off, and the transistors P1, P3, P6, P8 are turned on. When passing through a same voltage V, the voltage V2 output on the left is V-100mv, and the voltage V1 output on the right is V +100 mv. In the read phase, the output voltage V3 is selected by a selector to be V1 or V2.
In order to more clearly show the technical solutions and the technical effects provided by the present invention, the structural performance of the 2SA circuit provided by the embodiment of the present invention is compared with the conventional SRAM and SA circuit with reference to fig. 6 to 8 and table 1; the concrete content is as follows:
(1) as shown in fig. 6, in a conventional SRAM circuit under a 16nm FinFET (Fin-Field-Effect Transistor) process, the read time under different leakage current conditions is obtained by using the conventional SA and the 2SA circuit provided in the embodiment of the present invention. As can be seen from fig. 6: under the simulation conditions of 0.8V power supply voltage, TT process angle and 27 ℃, the result shows that when the leakage current is small, the reading time is basically the same as that of the 2SA circuit structure provided by the embodiment of the invention by adopting the traditional SA structure. However, when the leakage current increases to about 20 μ a, the reading time is longer than that of the 2SA circuit structure provided by the embodiment of the present invention, and when the leakage current is larger, the reading time using the conventional SA structure is increased sharply, and compared with the 2SA circuit structure provided by the embodiment of the present invention, the reading time is larger under the same leakage current.
(2) As shown in fig. 7, the conventional SA circuit and the 2SA circuit structure provided by the embodiment of the present invention have the capability of withstanding bit line leakage current under different process legs in the conventional SRAM circuit under 16nm FinFET process. As can be seen from fig. 7: under the simulation conditions of 0.8V power supply voltage and 27 ℃, the result shows that compared with the traditional SA circuit, the 2SA circuit structure provided by the embodiment of the invention has the advantages that the bit line leakage current bearing capacity is improved, and the maximum increase is that under the SS process angle, the leakage current bearing capacity of the 2SA is increased by 785%.
(3) As shown in fig. 8, the time required for reading data under different process pins with the maximum leakage current is obtained by using the conventional SA circuit and the 2SA circuit structure provided by the embodiment of the present invention in the conventional SRAM circuit under the 16nm FinFET process. As can be seen from fig. 8: under the simulation conditions of 0.8V power supply voltage and 27 ℃, the result shows that the 2SA circuit structure provided by the embodiment of the invention is improved in data reading time compared with the traditional SA circuit under different processes, and the reading time is reduced by 160% at least.
(4) As shown in table 1, the 2SA circuit structure provided in the embodiment of the present invention outputs data of 2 SAs under the conditions of different bit line leakage and different stored data under the simulation conditions of 0.8V power supply voltage and 27 ℃.
TABLE 12 SA circuit configuration output data variation of 2 SAs at different bit line leakage and different memory contents
As can be seen from table 1: under the simulation condition of 0.8V power supply voltage and 27 ℃, the result shows that when the memory cell is '1', the BL leaks, the output Q1 of the first sense amplifier (SA1) is 1, and the output Q2 of the second sense amplifier (SA3) is 1. When the memory cell is '0', BL leaks, Q1 is 1, and Q2 is 0. When the memory cell is '1', BLB leaks, Q1 is 0, and Q2 is 1. When the memory cell is '0', BLB leaks, Q1 is 0, and Q2 is 0.
In summary, the embodiments of the present invention can effectively resist the influence caused by the bit line leakage current, and compared with the SA structure in the prior art, the embodiments of the present invention can greatly reduce the data reading time and increase the reading speed and stability of the SRAM. Meanwhile, the capacity of resisting bit line leakage current of the SRAM is improved to a certain extent.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (3)
1. A circuit structure for counteracting bitline leakage current using two sense amplifier technology, comprising: the circuit comprises a first sensitive amplifier, a second sensitive amplifier, a first output selection circuit, a second output selection circuit and a voltage follower circuit, wherein the first output selection circuit and the second output selection circuit are composed of transmission gates; the first sensitive amplifier, the first output selection circuit, the voltage follower circuit, the second output selection circuit and the second sensitive amplifier are sequentially connected, and the output selection circuit formed by the transmission gates is also connected with the second sensitive amplifier;
comparing the voltages of the two bit lines by the first sense amplifier, wherein the output voltage difference signal controls the first output selection circuit to select one end with higher voltage of the bit line to be connected with the voltage follower circuit, the bit line has higher voltage, namely smaller leakage current, and meanwhile, the first output selection circuit also inputs the selected voltage of the bit line into a differential input tube of the second sense amplifier; then, the voltage of the followed bit line generates two following voltages through a voltage following circuit and is selected through a second output selection circuit, one following voltage is output to the other differential input tube of a second sense amplifier, the second sense amplifier compares the bit line voltage with the following voltages to generate an output signal, and data reading is completed;
wherein the voltage follower circuit comprises: 8 PMOS tubes, which are marked as P0-P7, and 4 capacitors, which are marked as C1-C4, wherein:
the grid electrode of the PMOS pipe P0 is connected with a signal P, the source electrode is connected with VDD, and the signal P is a low-level signal; the grid electrode of the PMOS pipe P1 is connected with a signal PR, the source electrode is connected with an output signal V of the first output selection circuit, and the signal PR is a high-level signal; one end of the capacitor C1 is connected with the drain electrodes of the PMOS tube P0 and the PMOS tube P1, and the other end is connected with the drain electrode of the PMOS tube P2 and the source electrode of the PMOS tube P3; the grid electrode of the PMOS tube P2 is connected with a signal P, and the source electrode is connected with the drain electrode of the PMOS tube P4; the grid electrode of the PMOS tube P3 is connected with the signal PR, and two ends of the capacitor C3 are respectively connected with the drain electrode and VSS of the PMOS tube P3; the grid electrode of the PMOS pipe P6 is connected with a signal P, and the source electrode is connected with VDD; the grid of the PMOS pipe P5 is connected with the signal PR, and the source is connected with the output signal V of the first output selection circuit; one end of the capacitor C2 is connected with the drain electrodes of the PMOS tube P5 and the PMOS tube P6 and the source electrode of the PMOS tube P4, and the other end is connected with the source electrode of the PMOS tube P7; the grid electrode of the PMOS tube P4 is connected with a signal P, and the drain electrode is connected with the source electrode of the PMOS tube P2; the grid electrode of the PMOS tube P7 is connected with the signal PR, and two ends of the capacitor C4 are respectively connected with the drain electrode and VSS of the PMOS tube P7; the signal PR represents a high level signal, the signal P represents a low level signal, the voltage of the drain electrode of the PMOS transistor P3 is marked as V2, and the voltage of the drain electrode of the PMOS transistor P7 is marked as V1.
2. The circuit structure of claim 1, wherein the circuit operation is divided into three stages as follows: a bit line pre-charging stage, a leakage current checking stage and a data reading stage; wherein:
bit line precharge stage: at this stage, the bit line voltage is precharged to the power supply voltage, and then the precharge circuit is turned off; at this time, the leakage current existing on the bit line can reduce the voltage of the bit line, and the voltage reduced by the two bit lines is different due to different leakage currents, so that a voltage difference caused by the leakage current is formed; at this stage, the word line of the memory cell is at a low voltage, and the memory cell is not turned on;
and (3) a leakage current checking stage: after a voltage difference with a certain magnitude caused by leakage current is formed, the first sensitive amplifier is opened to amplify the bit line voltage difference, and the output signal can control the output selection circuit to select one end with smaller leakage current to be connected with the voltage follower circuit according to different polarities of the voltage difference; at this stage, the memory cell is still not opened;
a data reading stage: selecting one bit line with smaller leakage voltage from the two bit lines to follow according to the output signal of the first sense amplifier, and taking the voltage of the bit line as the input voltage of the second sense amplifier; when the voltage of the memory cell word line rises to a high voltage, the memory cell is turned on, the discharge of the bit line connected to the node of the memory cell storing data 0 starts to increase, and the discharge current is Ileakage0+IcellWherein, Ileakage0Is leakage current of bit line, IcellDischarging current for the bit line; and the leakage current of the bit line connected to the node storing data 1 in the memory cell is Ileakage1(ii) a The following circuit outputs following voltage; and selecting V1 or V2 as the following voltage to be output according to the storage content of the storage unit, opening a second sense amplifier after the bit line discharges to a certain voltage, comparing the bit line voltage with the following voltage by the second sense amplifier to generate an output signal, and finishing data reading.
3. A circuit arrangement for counteracting bitline leakage current using two sense amplifier techniques according to claim 1 or 2, characterized in that the following voltage selection is determined by reading 0 and reading 1: when reading 0, the result of the comparison of the follower voltage V2 with the bit line voltage is selected as an output, which is 0 because the bit line voltage is greater than the follower voltage V2; when reading a1, the result of the comparison of the follower voltage V1 with the bit line voltage is selected as the output, which is 1 since the bit line voltage is less than V1.
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| CN114863971B (en) * | 2022-04-19 | 2025-02-14 | 安徽大学 | A control circuit for bit line leakage current, sensitive amplifier and memory |
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| CN109559767A (en) | 2019-04-02 |
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