CN108305858B - Enhanced heat dissipation type package and preparation method thereof - Google Patents
Enhanced heat dissipation type package and preparation method thereof Download PDFInfo
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- 230000017525 heat dissipation Effects 0.000 title claims abstract description 195
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 238000005476 soldering Methods 0.000 claims abstract description 53
- 239000002184 metal Substances 0.000 claims description 81
- 238000000034 method Methods 0.000 claims description 46
- 238000005538 encapsulation Methods 0.000 claims description 17
- 238000007789 sealing Methods 0.000 claims description 7
- 238000003466 welding Methods 0.000 claims description 7
- 238000009713 electroplating Methods 0.000 claims description 6
- 239000003566 sealing material Substances 0.000 claims description 6
- 239000000463 material Substances 0.000 claims description 5
- 150000001875 compounds Chemical class 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 11
- 238000000227 grinding Methods 0.000 description 8
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- 239000004065 semiconductor Substances 0.000 description 4
- 239000000084 colloidal system Substances 0.000 description 3
- 229910000975 Carbon steel Inorganic materials 0.000 description 2
- 239000010962 carbon steel Substances 0.000 description 2
- 239000012050 conventional carrier Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
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- 238000010137 moulding (plastic) Methods 0.000 description 2
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- 230000001680 brushing effect Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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Abstract
本发明提供一种增强散热型封装体及其制备方法。所述封装体包括至少一芯片及一塑封体，所述塑封体塑封所述芯片，每一所述芯片具有一设置有焊垫的上表面及一与所述上表面相对设置的下表面，在所述塑封体底部设置有一底部散热板，在所述塑封体至少一侧壁设置有一侧壁散热板，所述芯片的下表面与所述底部散热板连接，设置于所述塑封体上表面的芯片输出管脚穿过所述塑封体与所述芯片上表面的焊垫连通。本发明的优点在于，在所述封装体的底面及侧面均设置散热板，使封装体具有优良的散热性能，且结构简单，对于常用IC封装或者大功率器件可以显著提高散热效果，减少芯片封装的热阻，提高芯片的可靠性、稳定性，提升芯片的功能和实用性。
The invention provides an enhanced heat dissipation type package and a preparation method thereof. The package includes at least one chip and a plastic package. The plastic package encapsulates the chip. Each chip has an upper surface provided with soldering pads and a lower surface opposite to the upper surface. A bottom heat dissipation plate is provided at the bottom of the plastic package body, and a side wall heat dissipation plate is provided on at least one side wall of the plastic package body. The lower surface of the chip is connected to the bottom heat dissipation plate. The output pins of the chip pass through the plastic package and are connected to the soldering pads on the upper surface of the chip. The advantage of the present invention is that heat dissipation plates are provided on the bottom and sides of the package, so that the package has excellent heat dissipation performance and has a simple structure. It can significantly improve the heat dissipation effect for commonly used IC packages or high-power devices and reduce chip packaging. The thermal resistance improves the reliability and stability of the chip, and improves the function and practicality of the chip.
Description
技术领域Technical field
本发明涉及半导体封装领域，尤其涉及一种增强散热型封装体及其制备方法。The present invention relates to the field of semiconductor packaging, and in particular to an enhanced heat dissipation type package and a preparation method thereof.
背景技术Background technique
为满足电子产品的轻薄短小的需求，作为电子产品的核心元件的半导体封装体也朝微型化(Miniaturization)的方向发展。近年来，业界发展出一种芯片尺寸封装体(ChipScalePackage，简称CSP)的微型化半导体封装体，其特点在于，前述芯片尺寸封装体的尺寸约等于其芯片的尺寸或略大于其芯片的尺寸。另一方面，半导体封装体除了需在尺寸上微型化外，也需提高集成度(integrity)以及与电路板等外部电子元件电性连接所用的输入/输出端子(Input/Output，简称I/O)的数量，才满足电子产品在高性能与高处理速度上的需求。In order to meet the demand for thin, light and compact electronic products, semiconductor packages, which are the core components of electronic products, are also developing in the direction of miniaturization. In recent years, the industry has developed a miniaturized semiconductor package called Chip Scale Package (CSP). Its characteristic is that the size of the aforementioned chip scale package is approximately equal to the size of the chip or slightly larger than the size of the chip. On the other hand, in addition to being miniaturized in size, semiconductor packages also need to increase their integrity and input/output terminals (Input/Output, referred to as I/O) for electrical connection with external electronic components such as circuit boards. ) can meet the needs of electronic products for high performance and high processing speed.
现有的芯片尺寸封装体的制作一般是采用封装胶体包覆芯片，包覆后在封装胶体以及芯片的主动表面上形成重配置线路层，并使芯片的主动表面上的输入/输出端子(I/O)与重配置线路层电性连接。一般来说，由于封装胶体的热传导系数较低、散热效果差，因此芯片所产生的热大多是通过重配置线路传递至外界，其散热面积或散热途径有限，故散热效率不佳。在热无法快速地传递至外界而积累于尺寸封装体的内部的情况下，容易造成封装体产生翘曲(warpage)。Existing chip-size packages are generally made by using packaging colloid to coat the chip. After coating, a reconfiguration circuit layer is formed on the packaging colloid and the active surface of the chip, and the input/output terminals (I) on the active surface of the chip are /O) is electrically connected to the reconfiguration line layer. Generally speaking, because the thermal conductivity of the packaging colloid is low and the heat dissipation effect is poor, most of the heat generated by the chip is transferred to the outside world through reconfiguration circuits. Its heat dissipation area or heat dissipation channels are limited, so the heat dissipation efficiency is poor. When heat cannot be quickly transferred to the outside and accumulates inside the large package, it is easy to cause warpage of the package.
发明内容Contents of the invention
本发明所要解决的技术问题是，提供一种增强散热型封装体及其制备方法。The technical problem to be solved by the present invention is to provide an enhanced heat dissipation type package and a preparation method thereof.
为了解决上述问题，本发明提供了一种增强散热型封装体，包括至少一芯片及一塑封体，所述塑封体塑封所述芯片，每一所述芯片具有一设置有焊垫的上表面及一与所述上表面相对设置的下表面，在所述塑封体底部设置有一底部散热板，在所述塑封体至少一侧壁设置有一侧壁散热板，所述芯片的下表面与所述底部散热板连接，设置于所述塑封体上表面的芯片输出管脚穿过所述塑封体与所述芯片上表面的焊垫连通。In order to solve the above problems, the present invention provides an enhanced heat dissipation type package, which includes at least one chip and a plastic package body. The plastic package body molds the chip, and each chip has an upper surface provided with a soldering pad and a A lower surface opposite to the upper surface. A bottom heat dissipation plate is provided at the bottom of the plastic package. A side wall heat dissipation plate is provided on at least one side wall of the plastic package. The lower surface of the chip is in contact with the bottom. The heat dissipation plate is connected, and the chip output pins provided on the upper surface of the plastic package pass through the plastic package and communicate with the soldering pads on the upper surface of the chip.
在一实施例中，在所述塑封体的一个侧壁、两个侧壁、三个侧壁或者四个侧壁上均设置有侧壁散热板。In one embodiment, side wall heat dissipation plates are provided on one side wall, two side walls, three side walls, or four side walls of the plastic package.
在一实施例中，所述侧壁散热板与所述底部散热板连接。In one embodiment, the side wall heat dissipation plate is connected to the bottom heat dissipation plate.
在一实施例中，所述塑封体包括一基层塑封体及一设置在所述基层塑封体表面的绝缘层，在所述基层塑封体上表面设置有一重布线层，所述重布线层具有多个分别与所述芯片的焊垫连接的金属垫，所述绝缘层覆盖所述重布线层，所述绝缘层暴露出所述金属垫，所述芯片输出管脚穿过所述绝缘层与所述重布线层的金属垫连通。In one embodiment, the plastic package includes a base plastic package and an insulating layer disposed on the surface of the base plastic package. A rewiring layer is provided on the upper surface of the base plastic package. The rewiring layer has multiple metal pads respectively connected to the soldering pads of the chip; the insulating layer covers the rewiring layer; the insulating layer exposes the metal pads; the chip output pins pass through the insulating layer and connect to the Describe the metal pad connectivity of the redistribution layer.
本发明还提供一种增强散热型封装体的制备方法，包括如下步骤：提供一载体；在所述载体上表面形成一底部散热板及至少一垂直所述载体的侧壁散热板；将至少一芯片的下表面黏贴在所述底部散热板的上表面，所述芯片设置有焊垫的上表面与所述芯片的下表面相对设置；采用塑封料塑封所述芯片、所述底部散热板及所述侧壁散热板，形成塑封体；去除与所述芯片的焊垫对应的塑封体，暴露出所述焊垫；在所述塑封体上表面形成芯片输出管脚，所述芯片输出管脚与所述暴露的焊垫连通；去除所述侧壁散热板外表面的塑封料，并去除所述载体，形成增强散热型封装体。The invention also provides a method for preparing an enhanced heat dissipation type package, which includes the following steps: providing a carrier; forming a bottom heat dissipation plate and at least one side wall heat dissipation plate perpendicular to the carrier on the upper surface of the carrier; placing at least one The lower surface of the chip is adhered to the upper surface of the bottom heat dissipation plate, and the upper surface of the chip is provided with soldering pads opposite to the lower surface of the chip; plastic sealing material is used to seal the chip, the bottom heat dissipation plate and The side wall heat dissipation plate forms a plastic package; the plastic package corresponding to the welding pad of the chip is removed to expose the welding pad; a chip output pin is formed on the upper surface of the plastic package, and the chip output pin Connected to the exposed soldering pad; remove the plastic sealant on the outer surface of the side wall heat dissipation plate, and remove the carrier to form an enhanced heat dissipation package.
在一实施例中，所述载体的上表面设置有一金属层，所述底部散热板及所述侧壁散热板通过电镀方式形成在所述金属层表面。In one embodiment, a metal layer is provided on the upper surface of the carrier, and the bottom heat dissipation plate and the side wall heat dissipation plate are formed on the surface of the metal layer by electroplating.
在一实施例中，所述侧壁散热板为一个、两个三个、或四个，所述侧壁散热板与所述底部散热板连接。In one embodiment, the number of the side wall heat dissipation plates is one, two, three, or four, and the side wall heat dissipation plates are connected to the bottom heat dissipation plate.
在一实施例中，在去除与所述芯片的焊垫对应的塑封体的步骤中，进一步包括去除所述焊垫所在平面上的所有塑封体，暴露出所述焊垫上表面及所述侧壁散热板上表面。In one embodiment, the step of removing the plastic package corresponding to the bonding pad of the chip further includes removing all the plastic package on the plane where the bonding pad is located, exposing the upper surface of the bonding pad and the side wall The upper surface of the heat sink.
在一实施例中，在所述塑封体上表面形成芯片输出管脚的步骤之前还包括一形成重布线层的步骤，其中，定义采用塑封料塑封所述芯片、所述底部散热板及所述侧壁散热板形成的塑封体为基层塑封体：在所述基层塑封体上表面形成重布线层，所述重布线层具有分别与所述芯片的焊垫连通的金属垫；在所述重布线层表面形成一绝缘层，所述绝缘层覆盖所述重布线层及基层塑封体；去除与所述重布线层的金属垫对应的绝缘层，暴露出所述金属垫；在所述绝缘层上表面形成芯片输出管脚，所述芯片输出管脚与所述暴露的金属垫连通。In one embodiment, the step of forming the chip output pins on the upper surface of the plastic package further includes a step of forming a rewiring layer, wherein it is defined that the chip, the bottom heat dissipation plate and the The plastic package formed by the side wall heat dissipation plate is a base plastic package: a rewiring layer is formed on the upper surface of the base plastic package, and the rewiring layer has metal pads that are respectively connected to the soldering pads of the chip; in the rewiring An insulating layer is formed on the surface of the layer, and the insulating layer covers the rewiring layer and the base layer plastic body; the insulating layer corresponding to the metal pad of the rewiring layer is removed to expose the metal pad; on the insulating layer Chip output pins are formed on the surface, and the chip output pins are connected to the exposed metal pads.
在一实施例中，在形成重布线层的步骤中，所述侧壁散热板也被增高。In one embodiment, during the step of forming the redistribution layer, the sidewall heat dissipation plate is also raised.
本发明的优点在于，在所述封装体的底面及侧面均设置散热板，使封装体具有优良的散热性能，且结构简单，对于常用IC封装或者大功率器件可以显著提高散热效果，减少芯片封装的热阻，提高芯片的可靠性、稳定性，提升芯片的功能和实用性。The advantage of the present invention is that heat dissipation plates are provided on the bottom and sides of the package, so that the package has excellent heat dissipation performance and has a simple structure. It can significantly improve the heat dissipation effect for commonly used IC packages or high-power devices and reduce chip packaging. The thermal resistance improves the reliability and stability of the chip, and improves the function and practicality of the chip.
附图说明Description of drawings
图1是增强散热型封装体的制备方法的第一实施例步骤示意图；Figure 1 is a schematic diagram of the steps of a first embodiment of a method for preparing a heat dissipation-enhanced package;
图2A～图2G是本发明增强散热型封装体的制备方法的第一实施例的工艺流程图；2A to 2G are process flow diagrams of the first embodiment of the method for preparing a heat dissipation-enhanced package of the present invention;
图3是增强散热型封装体的制备方法的第二实施例步骤示意图；Figure 3 is a schematic diagram of the steps of a method for preparing a heat dissipation-enhanced package according to a second embodiment;
图4A～图4J是本发明增强散热型封装体的制备方法的第二实施例的工艺流程图4A to 4J are process flow diagrams of a second embodiment of the method for preparing an enhanced heat dissipation package according to the present invention.
图5是本发明增强散热型封装体的第一实施例的结构示意图；Figure 5 is a schematic structural diagram of the first embodiment of the enhanced heat dissipation type package of the present invention;
图6是本发明增强散热型封装体的第二实施例的结构示意图。FIG. 6 is a schematic structural diagram of a second embodiment of the enhanced heat dissipation type package of the present invention.
具体实施方式Detailed ways
下面结合附图对本发明提供的增强散热型封装体及其制备方法的具体实施方式做详细说明。The specific embodiments of the enhanced heat dissipation package and its preparation method provided by the present invention will be described in detail below with reference to the accompanying drawings.
本发明提供一种增强散热型封装体的制备方法。其中附图中各个部件的结构尺寸与实际构件有差别，在本文中仅为说明本发明的技术方案，并不限定其具体结构。The invention provides a method for preparing a heat dissipation-enhanced package. The structural dimensions of each component in the drawings are different from the actual components. This article only illustrates the technical solution of the present invention and does not limit its specific structure.
图1是增强散热型封装体的制备方法的第一实施例步骤示意图。请参阅图1，在第一具体实施方式中，所述增强散热型封装体的制备方法包括如下步骤：步骤S10、提供一载体；步骤S11、在所述载体上表面形成一底部散热板及至少一垂直所述载体的侧壁散热板；步骤S12、将至少一芯片的下表面黏贴在所述底部散热板的上表面，所述芯片设置有焊垫的上表面与所述芯片的下表面相对设置；步骤S13、采用塑封料塑封所述芯片、所述底部散热板及所述侧壁散热板，形成塑封体；步骤S14、去除与所述芯片的焊垫对应的塑封体，暴露出所述焊垫；步骤S15、在所述塑封体上表面形成芯片输出管脚，所述芯片输出管脚与所述暴露的焊垫连通；步骤S16、去除所述侧壁散热板外表面的塑封料，并去除所述载体，形成增强散热型封装体。FIG. 1 is a schematic diagram of the steps of a method for preparing a heat dissipation-enhanced package according to a first embodiment. Please refer to Figure 1. In a first specific embodiment, the method for preparing the enhanced heat dissipation type package includes the following steps: step S10, providing a carrier; step S11, forming a bottom heat dissipation plate and at least one on the upper surface of the carrier. A side wall heat sink perpendicular to the carrier; step S12, stick the lower surface of at least one chip to the upper surface of the bottom heat sink, and the chip is provided with an upper surface of a soldering pad and a lower surface of the chip Relative arrangement; step S13, use plastic sealing material to seal the chip, the bottom heat sink plate and the side wall heat sink plate to form a plastic package; step S14, remove the plastic package corresponding to the welding pad of the chip to expose the The soldering pad; Step S15, form a chip output pin on the upper surface of the plastic package, and the chip output pin is connected to the exposed soldering pad; Step S16, remove the plastic package material on the outer surface of the side wall heat sink plate , and remove the carrier to form an enhanced heat dissipation package.
图2A～图2G是本发明增强散热型封装体的制备方法的第一实施例的工艺流程图。2A to 2G are process flow charts of the first embodiment of the method for manufacturing a heat dissipation-enhanced package of the present invention.
请参阅步骤S10及图2A，提供一载体200。所述载体200可以为本领域常规的载体，例如碳素钢等。其中，若所述载体200为绝缘载体，则在所述载体200的上表面可以覆盖一金属层(附图中未绘示)，以提供导电性能，若所述载体200为导电载体，则可以不在所述载体200表面形成金属层。所述载体200具有导电性能，可以为后续采用电镀方法形成底部散热板及侧壁散热板提供基础。Referring to step S10 and FIG. 2A, a carrier 200 is provided. The carrier 200 can be a conventional carrier in this field, such as carbon steel. Wherein, if the carrier 200 is an insulating carrier, the upper surface of the carrier 200 can be covered with a metal layer (not shown in the drawings) to provide conductive properties. If the carrier 200 is a conductive carrier, then No metal layer is formed on the surface of the carrier 200 . The carrier 200 has electrical conductivity and can provide a basis for subsequent electroplating methods to form the bottom heat dissipation plate and the side wall heat dissipation plate.
请参阅步骤S11及图2B，在所述载体200上表面形成一底部散热板201及至少一垂直所述载体200的侧壁散热板202。在本实施例中，可采用电镀的方法形成底部散热板201及侧壁散热板202。进一步，所述底部散热板201与所述侧壁散热板202连接。所述侧壁散热板202为一个、两个、三个或者四个，相邻的侧壁散热板202彼此连接且与所底部散热板201连接。在本实施中，在所述载体200上设置有两个相对设置的侧壁散热板202，两个所述侧壁散热板202与所述底部散热板201形成U型结构。Referring to step S11 and FIG. 2B , a bottom heat dissipation plate 201 and at least one side wall heat dissipation plate 202 perpendicular to the carrier 200 are formed on the upper surface of the carrier 200 . In this embodiment, the bottom heat dissipation plate 201 and the side wall heat dissipation plate 202 can be formed by electroplating. Further, the bottom heat dissipation plate 201 is connected to the side wall heat dissipation plate 202 . The number of side wall heat dissipation plates 202 is one, two, three or four, and adjacent side wall heat dissipation plates 202 are connected to each other and to the bottom heat dissipation plate 201 . In this implementation, two opposite side wall heat dissipation plates 202 are provided on the carrier 200 , and the two side wall heat dissipation plates 202 and the bottom heat dissipation plate 201 form a U-shaped structure.
请参阅步骤S12及图2C，将至少一芯片203的下表面黏贴在所述底部散热板201的上表面，所述芯片203设置有焊垫2031的上表面与所述芯片203的下表面相对设置。其中所述芯片203的数目不进行限制，可以设置多个，也可以设置一个，在本实施例中在所述底部散热板201的上表面设置一个芯片203。所述芯片203采用导电或不导电的粘结剂210黏贴在所述底部散热板201的上表面。所述粘结剂可以包括导电胶、不导电胶、锡膏或者金属材料等。所述芯片203的类型可以为功能性芯片。Referring to step S12 and FIG. 2C, the lower surface of at least one chip 203 is pasted on the upper surface of the bottom heat sink 201. The upper surface of the chip 203 is provided with a soldering pad 2031 opposite to the lower surface of the chip 203. set up. The number of the chips 203 is not limited. Multiple chips 203 can be provided, or one chip 203 can be provided. In this embodiment, one chip 203 is provided on the upper surface of the bottom heat dissipation plate 201 . The chip 203 is adhered to the upper surface of the bottom heat dissipation plate 201 using conductive or non-conductive adhesive 210 . The adhesive may include conductive glue, non-conductive glue, solder paste or metal materials. The type of chip 203 may be a functional chip.
请参阅步骤S13及图2D，采用塑封料塑封所述芯片203、所述底部散热板201及所述侧壁散热板202，形成塑封体204。所述塑封的方法为本领域常规的塑封方法。其中，所述底部散热板201的下表面与所述载体200的上表面接触，使得所述底部散热板201的下表面没有被塑封体204塑封，即其下表面暴露于所述底部散热板201的下表面。Referring to step S13 and FIG. 2D , the chip 203 , the bottom heat dissipation plate 201 and the side wall heat dissipation plate 202 are encapsulated with a plastic encapsulation material to form a plastic encapsulation body 204 . The plastic sealing method is a conventional plastic sealing method in this field. The lower surface of the bottom heat dissipation plate 201 is in contact with the upper surface of the carrier 200 , so that the lower surface of the bottom heat dissipation plate 201 is not molded by the plastic sealing body 204 , that is, its lower surface is exposed to the bottom heat dissipation plate 201 the lower surface.
请参阅步骤S14及图2E，去除与所述芯片203的焊垫2031对应的塑封体，暴露出所述焊垫2031。在本步骤中，暴露出所述焊垫2031的方法有很多，例如，通过钻孔等方法去除所述焊垫2031对应位置处的塑封体，暴露出所述焊垫2031，或者通过研磨等方法去除所述焊垫2031所在层上方的全部塑封体，暴露出所述焊垫2031。在本实施例中，采用的是通过研磨等方法去除所述焊垫2031所在层上方的全部塑封体，暴露出所述焊垫2031。其中，在本步骤中，在暴露出所述焊垫2031的同时，也暴露出所述侧壁散热板202的上表面。Referring to step S14 and FIG. 2E , the plastic package corresponding to the bonding pad 2031 of the chip 203 is removed to expose the bonding pad 2031 . In this step, there are many methods to expose the soldering pad 2031, for example, by drilling or other methods to remove the plastic package at the corresponding position of the soldering pad 2031 to expose the soldering pad 2031, or by grinding or other methods. The entire plastic package above the layer where the soldering pad 2031 is located is removed to expose the soldering pad 2031 . In this embodiment, the entire plastic package above the layer where the soldering pad 2031 is located is removed by grinding or other methods to expose the soldering pad 2031 . In this step, while the soldering pad 2031 is exposed, the upper surface of the sidewall heat dissipation plate 202 is also exposed.
请参阅步骤S15及图2F，在所述塑封体204上表面形成芯片输出管脚205，所述芯片输出管脚205与所述暴露的焊垫2031连通。若在步骤S14中，通过钻孔等方法去除所述焊垫2031对应位置处的塑封体，暴露出所述焊垫2031，则在本步骤中，形成一金属层，所述金属层穿过塑封体的孔与所述焊垫2031连通，图形化所述金属层，形成芯片输出管脚205；若在步骤S14中，通过研磨等方法去除所述焊垫2031所在层上方的全部塑封体，暴露出所述焊垫2031，则在本步骤中，形成一金属层，所述金属层覆盖所述暴露的焊垫2031及塑封体204，图形化所述金属层，形成芯片输出管脚205。其中，在本步骤中，在所述侧壁散热板202的上表面也形成金属块206，所述金属块206增加所述侧壁散热板202的高度。所述金属块206的厚度小于或等于所述芯片输出管脚205的厚度，从而避免所述侧壁散热板202影响所述封装体与外部构件的连接。Referring to step S15 and FIG. 2F , a chip output pin 205 is formed on the upper surface of the plastic package 204 , and the chip output pin 205 is connected to the exposed pad 2031 . If in step S14, the plastic package body at the corresponding position of the soldering pad 2031 is removed by drilling or other methods to expose the soldering pad 2031, then in this step, a metal layer is formed, and the metal layer passes through the plastic package The hole of the body is connected with the soldering pad 2031, and the metal layer is patterned to form the chip output pin 205; if in step S14, all the plastic packaging body above the layer where the soldering pad 2031 is located is removed by grinding or other methods, and the exposed After removing the soldering pad 2031, in this step, a metal layer is formed to cover the exposed soldering pad 2031 and the plastic package 204, and the metal layer is patterned to form the chip output pin 205. In this step, a metal block 206 is also formed on the upper surface of the side wall heat dissipation plate 202 , and the metal block 206 increases the height of the side wall heat dissipation plate 202 . The thickness of the metal block 206 is less than or equal to the thickness of the chip output pin 205, thereby preventing the sidewall heat dissipation plate 202 from affecting the connection between the package and external components.
请参阅步骤S16及图2G，去除所述侧壁散热板202外表面的塑封料，并去除所述载体200，形成增强散热型封装体。在本步骤中，去除所述侧壁散热板202外表面的塑封料，以使侧壁散热板202暴露出来，实现所述侧壁散热板202的散热功能；去除所述载体200，以暴露出所述底部散热板201的下表面，实现所述底部散热板201的散热功能。若所述载体200的表面具有金属层，则所述金属层可以保留，其不会影响所述底部散热板201的散热性能。Please refer to step S16 and FIG. 2G to remove the plastic compound on the outer surface of the sidewall heat dissipation plate 202 and remove the carrier 200 to form an enhanced heat dissipation package. In this step, the plastic sealing material on the outer surface of the side wall heat dissipation plate 202 is removed to expose the side wall heat dissipation plate 202 to realize the heat dissipation function of the side wall heat dissipation plate 202; the carrier 200 is removed to expose the side wall heat dissipation plate 202. The lower surface of the bottom heat dissipation plate 201 realizes the heat dissipation function of the bottom heat dissipation plate 201 . If the surface of the carrier 200 has a metal layer, the metal layer can be retained, which will not affect the heat dissipation performance of the bottom heat dissipation plate 201 .
本发明增强散热型封装体的制备方法在所述封装体的底面及侧面均设置散热板，使封装体具有优良的散热性能，且结构简单，对于常用IC封装或者大功率器件可以显著提高散热效果，减少芯片封装的热阻，提高芯片的可靠性、稳定性，提升芯片的功能和实用性。The preparation method of the enhanced heat dissipation type package of the present invention provides heat dissipation plates on both the bottom and side surfaces of the package, so that the package has excellent heat dissipation performance and a simple structure. It can significantly improve the heat dissipation effect for commonly used IC packages or high-power devices. , reduce the thermal resistance of the chip package, improve the reliability and stability of the chip, and enhance the function and practicality of the chip.
图3是增强散热型封装体的制备方法的第二实施例步骤示意图。请参阅图3，在第二具体实施方式中，所述增强散热型封装体的制备方法包括如下步骤：步骤S30、提供一载体；步骤S31、在所述载体上表面形成一底部散热板及至少一垂直所述载体的侧壁散热板；步骤S32、将至少一芯片的下表面黏贴在所述底部散热板的上表面，所述芯片设置有焊垫的上表面与所述芯片的下表面相对设置；步骤S33、采用塑封料塑封所述芯片、所述底部散热板及所述侧壁散热板，形成基层塑封体；步骤S34、去除与所述芯片的焊垫对应的基层塑封体，暴露出所述焊垫；步骤S35、在所述基层塑封体上表面形成重布线层，所述重布线层具有分别与所述芯片的焊垫连通的金属垫；步骤S36、在所述重布线层表面形成一绝缘层，所述绝缘层覆盖所述重布线层及基层塑封体；步骤S37、去除与所述重布线层的金属垫对应的绝缘层，暴露出所述金属垫；步骤S38、在所述绝缘层上表面形成芯片输出管脚，所述芯片输出管脚与所述暴露的金属垫连通；步骤S39、去除所述侧壁散热板外表面的塑封料，并去除所述载体，形成增强散热型封装体。FIG. 3 is a schematic diagram of the steps of a method for preparing a heat dissipation-enhanced package according to a second embodiment. Please refer to Figure 3. In a second specific embodiment, the preparation method of the enhanced heat dissipation type package includes the following steps: Step S30, providing a carrier; Step S31, forming a bottom heat dissipation plate and at least one on the upper surface of the carrier. A side wall heat dissipation plate perpendicular to the carrier; step S32, stick the lower surface of at least one chip to the upper surface of the bottom heat dissipation plate, and the upper surface of the chip is provided with a soldering pad and the lower surface of the chip Relative arrangement; step S33, use plastic molding material to mold the chip, the bottom heat dissipation plate and the side wall heat dissipation plate to form a base plastic encapsulation; step S34, remove the base plastic encapsulation corresponding to the welding pad of the chip, and expose Remove the soldering pads; Step S35, form a rewiring layer on the upper surface of the base plastic package, the rewiring layer has metal pads respectively connected to the soldering pads of the chip; Step S36, On the rewiring layer An insulating layer is formed on the surface, and the insulating layer covers the rewiring layer and the base plastic package; Step S37, remove the insulating layer corresponding to the metal pad of the rewiring layer, exposing the metal pad; Step S38, in A chip output pin is formed on the upper surface of the insulating layer, and the chip output pin is connected to the exposed metal pad; step S39, remove the plastic sealing material on the outer surface of the side wall heat dissipation plate, and remove the carrier to form Enhanced heat dissipation package.
图4A～图4J是本发明增强散热型封装体的制备方法的第二实施例的工艺流程图。4A to 4J are process flow diagrams of a second embodiment of the method for manufacturing a heat dissipation-enhanced package according to the present invention.
请参阅步骤S30及图4A，提供一载体400。所述载体400可以为本领域常规的载体，例如碳素钢等。其中，若所述载体400为绝缘载体，则在所述载体400的上表面可以覆盖一金属层(附图中未绘示)，以提供导电性能，若所述载体400为导电载体，则可以不在所述载体400表面形成金属层。所述载体400具有导电性能，可以为后续采用电镀方法形成底部散热板及侧壁散热板提供基础。Referring to step S30 and FIG. 4A, a carrier 400 is provided. The carrier 400 can be a conventional carrier in this field, such as carbon steel. Wherein, if the carrier 400 is an insulating carrier, the upper surface of the carrier 400 can be covered with a metal layer (not shown in the drawings) to provide conductive properties. If the carrier 400 is a conductive carrier, then No metal layer is formed on the surface of the carrier 400 . The carrier 400 has electrical conductivity and can provide a basis for subsequent electroplating methods to form the bottom heat dissipation plate and the side wall heat dissipation plate.
请参阅步骤S31及图4B，在所述载体400上表面形成一底部散热板401及至少一垂直所述载体400的侧壁散热板402。在本实施例中，可采用电镀的方法形成底部散热板401及侧壁散热板402。进一步，所述底部散热板401与所述侧壁散热板402连接。所述侧壁散热板402为一个、两个三个或四个，相邻的侧壁散热板402彼此连接且与所底部散热板401连接。在本实施中，在所述载体400上设置有两个相对设置的侧壁散热板402，两个所述侧壁散热板402与所述底部散热板401形成U型结构。Referring to step S31 and FIG. 4B , a bottom heat dissipation plate 401 and at least one side wall heat dissipation plate 402 perpendicular to the carrier 400 are formed on the upper surface of the carrier 400 . In this embodiment, electroplating can be used to form the bottom heat dissipation plate 401 and the side wall heat dissipation plate 402. Further, the bottom heat dissipation plate 401 is connected to the side wall heat dissipation plate 402 . The number of side wall heat dissipation plates 402 is one, two, three or four, and adjacent side wall heat dissipation plates 402 are connected to each other and to the bottom heat dissipation plate 401 . In this implementation, two opposite side wall heat dissipation plates 402 are provided on the carrier 400 , and the two side wall heat dissipation plates 402 and the bottom heat dissipation plate 401 form a U-shaped structure.
请参阅步骤S32及图4C，将至少一芯片403的下表面黏贴在所述底部散热板401的上表面，所述芯片403设置有焊垫4031的上表面与所述芯片403的下表面相对设置。其中所述芯片403的数目不进行限制，可以设置多个，也可以设置一个，在本实施例中在所述底部散热板401的上表面设置一个芯片403。所述芯片403采用导电或不导电的粘结剂黏贴在所述底部散热板401的上表面。所述粘结剂可以包括导电胶、不导电胶、锡膏或者金属材料等。所述芯片403的类型可以为功能性芯片。Referring to step S32 and FIG. 4C, the lower surface of at least one chip 403 is pasted on the upper surface of the bottom heat sink 401. The upper surface of the chip 403 is provided with a soldering pad 4031 opposite to the lower surface of the chip 403. set up. The number of the chips 403 is not limited. Multiple chips 403 may be provided, or one chip may be provided. In this embodiment, one chip 403 is provided on the upper surface of the bottom heat dissipation plate 401 . The chip 403 is adhered to the upper surface of the bottom heat dissipation plate 401 using conductive or non-conductive adhesive. The adhesive may include conductive glue, non-conductive glue, solder paste or metal materials. The type of chip 403 may be a functional chip.
请参阅步骤S33及图4D，采用塑封料塑封所述芯片403、所述底部散热板401及所述侧壁散热板402，形成基层塑封体404。所述塑封的方法为本领域常规的塑封方法。其中，所述底部散热板401的下表面与所述载体400的上表面接触，使得所述底部散热板401的下表面没有被基层塑封体404塑封，即其下表面暴露于所述底部散热板401的下表面。Referring to step S33 and FIG. 4D , the chip 403 , the bottom heat dissipation plate 401 and the side wall heat dissipation plate 402 are molded using plastic molding material to form a base plastic encapsulation body 404 . The plastic sealing method is a conventional plastic sealing method in this field. Wherein, the lower surface of the bottom heat dissipation plate 401 is in contact with the upper surface of the carrier 400, so that the lower surface of the bottom heat dissipation plate 401 is not molded by the base plastic encapsulation body 404, that is, its lower surface is exposed to the bottom heat dissipation plate. The lower surface of 401.
请参阅步骤S34及图4E，去除与所述芯片403的焊垫4031对应的塑封体，暴露出所述焊垫4031。在本步骤中，暴露出所述焊垫4031的方法有很多，例如，通过钻孔等方法去除所述焊垫4031对应位置处的塑封体，暴露出所述焊垫4031，或者通过研磨等方法去除所述焊垫4031所在层上方的全部塑封体，暴露出所述焊垫4031。在本实施例中，采用的是通过研磨等方法去除所述焊垫4031所在层上方的全部塑封体，暴露出所述焊垫4031。其中，在本步骤中，在暴露出所述焊垫4031的同时，也暴露出所述侧壁散热板402的上表面。Referring to step S34 and FIG. 4E , the plastic package corresponding to the bonding pad 4031 of the chip 403 is removed to expose the bonding pad 4031 . In this step, there are many methods to expose the soldering pad 4031, for example, by drilling or other methods to remove the plastic package at the corresponding position of the soldering pad 4031 to expose the soldering pad 4031, or by grinding or other methods. The entire plastic package above the layer where the soldering pad 4031 is located is removed to expose the soldering pad 4031 . In this embodiment, the entire plastic package above the layer where the soldering pad 4031 is located is removed by grinding or other methods to expose the soldering pad 4031 . In this step, while the soldering pad 4031 is exposed, the upper surface of the sidewall heat dissipation plate 402 is also exposed.
请参阅步骤S35及图4F，在所述基层塑封体404上表面形成重布线层，所述重布线层具有分别与所述芯片403的焊垫4031连通的金属垫407。若在步骤S34中，通过钻孔等方法去除所述焊垫4031对应位置处的塑封体，暴露出所述焊垫4031，则在本步骤中，形成一金属层，所述金属层穿过基层塑封体404的孔与所述焊垫4031连通，图形化所述金属层，形成重布线层；若在步骤S34中，通过研磨等方法去除所述焊垫4031所在层上方的全部塑封体，暴露出所述焊垫4031，则在本步骤中，形成一金属层，所述金属层覆盖所述暴露的焊垫4031及基层塑封体404，图形化所述金属层，重布线层。其中，在本步骤中，在所述侧壁散热板402的上表面也形成有重布线层的金属垫407，其增加所述侧壁散热板202的高度。所述重布线层能够扩大所述芯片403的焊垫4031的范围，形成扇出结构。Referring to step S35 and FIG. 4F , a redistribution layer is formed on the upper surface of the base plastic package 404 . The redistribution layer has metal pads 407 that are respectively connected to the bonding pads 4031 of the chip 403 . If in step S34, the plastic package at the corresponding position of the soldering pad 4031 is removed by drilling or other methods to expose the soldering pad 4031, then in this step, a metal layer is formed, and the metal layer passes through the base layer The holes of the plastic package 404 are connected to the soldering pads 4031, and the metal layer is patterned to form a rewiring layer; if in step S34, all the plastic package above the layer where the soldering pads 4031 are located is removed by grinding or other methods, the exposed After removing the soldering pad 4031, in this step, a metal layer is formed to cover the exposed soldering pad 4031 and the base plastic package 404, and the metal layer is patterned and redistributed. In this step, a redistribution layer metal pad 407 is also formed on the upper surface of the side wall heat dissipation plate 402 , which increases the height of the side wall heat dissipation plate 202 . The rewiring layer can expand the range of the bonding pad 4031 of the chip 403 to form a fan-out structure.
请参阅步骤S36及图4G，在所述重布线层表面形成一绝缘层408，所述绝缘层408覆盖所述重布线层及基层塑封体404。所述绝缘层408可以采用与形成基层塑封体404相同的塑封料包封形成，也可以刷胶或贴膜等方式形成。在本实施例中，所述绝缘层408采用与形成基层塑封体404相同的塑封料包封形成。Referring to step S36 and FIG. 4G, an insulating layer 408 is formed on the surface of the redistribution layer, and the insulating layer 408 covers the redistribution layer and the base plastic package 404. The insulating layer 408 can be encapsulated and formed using the same plastic encapsulation material used to form the base layer plastic encapsulation body 404, or can be formed by brushing glue or pasting a film. In this embodiment, the insulating layer 408 is formed by using the same plastic encapsulation material used to form the base layer plastic encapsulation body 404 .
请参阅步骤S37及图4H，去除与所述重布线层的金属垫407对应的绝缘层408，暴露出所述金属垫407。在本步骤中，暴露出所述金属垫407的方法有很多，例如，通过钻孔等方法去除所述金属垫407对应位置处的绝缘层408，暴露出所述金属垫407，或者通过研磨等方法去除所述重布线层上方的全部绝缘层408，暴露出所述金属垫407。在本实施例中，钻孔等方法去除所述金属垫407对应位置处的绝缘层408，暴露出所述金属垫407。其中，在本步骤中，在暴露出所述焊垫4031对应的所述金属垫407的同时，也暴露出所述侧壁散热板402的金属垫407上表面。Referring to step S37 and FIG. 4H, the insulating layer 408 corresponding to the metal pad 407 of the redistribution layer is removed to expose the metal pad 407. In this step, there are many methods to expose the metal pad 407 , for example, by drilling or other methods to remove the insulating layer 408 at the corresponding position of the metal pad 407 to expose the metal pad 407 , or by grinding, etc. The method removes all the insulating layer 408 above the redistribution layer to expose the metal pad 407 . In this embodiment, the insulating layer 408 at the corresponding position of the metal pad 407 is removed by drilling or other methods to expose the metal pad 407 . In this step, while the metal pad 407 corresponding to the soldering pad 4031 is exposed, the upper surface of the metal pad 407 of the side wall heat dissipation plate 402 is also exposed.
请参阅步骤S38及图4I，在所述绝缘层408上表面形成芯片输出管脚405，所述芯片输出管脚405与所述暴露的金属垫407连通。若在步骤S37中，通过钻孔等方法去除所述金属垫407对应位置处的绝缘层408，暴露出所述金属垫407，则在本步骤中，形成一金属层，所述金属层穿过绝缘层408的孔与所述金属垫407连通，图形化所述金属层，形成芯片输出管脚405；若在步骤S37中，通过研磨等方法去除所述重布线层上方的全部绝缘层408，暴露出所述金属垫407，则在本步骤中，形成一金属层，所述金属层覆盖所述暴露的金属垫407及绝缘层408，图形化所述金属层，形成芯片输出管脚405。其中，在本步骤中，在所述侧壁散热板402对应的金属垫407上表面也形成金属块406，所述金属块406增加所述侧壁散热板402的高度。所述金属块406的厚度小于或等于所述芯片输出管脚405的厚度，从而避免所述侧壁散热板402影响所述封装体与外部构件的连接。其中，与所述侧壁散热板402连接的金属垫407及金属块406均可起到散热作用，可以统称为所述封装体的侧壁散热板。Referring to step S38 and FIG. 4I , a chip output pin 405 is formed on the upper surface of the insulating layer 408 , and the chip output pin 405 is connected to the exposed metal pad 407 . If in step S37, the insulating layer 408 at the corresponding position of the metal pad 407 is removed by drilling or other methods to expose the metal pad 407, then in this step, a metal layer is formed, and the metal layer passes through The hole of the insulating layer 408 is connected to the metal pad 407, and the metal layer is patterned to form the chip output pin 405; if in step S37, all the insulating layer 408 above the rewiring layer is removed by grinding or other methods, If the metal pad 407 is exposed, in this step, a metal layer is formed to cover the exposed metal pad 407 and the insulating layer 408, and the metal layer is patterned to form the chip output pin 405. In this step, a metal block 406 is also formed on the upper surface of the metal pad 407 corresponding to the side wall heat dissipation plate 402. The metal block 406 increases the height of the side wall heat dissipation plate 402. The thickness of the metal block 406 is less than or equal to the thickness of the chip output pin 405, thereby preventing the sidewall heat dissipation plate 402 from affecting the connection between the package and external components. Among them, the metal pad 407 and the metal block 406 connected to the side wall heat dissipation plate 402 can both play a role in heat dissipation and can be collectively referred to as the side wall heat dissipation plate of the package.
请参阅步骤S39及图4J，去除所述侧壁散热板外表面的塑封料，并去除所述载体200，形成增强散热型封装体。在本步骤中，去除所述侧壁散热板外表面的塑封料，以使侧壁散热板暴露出来，实现所述侧壁散热板的散热功能；去除所述载体200，以暴露出所述底部散热板201的下表面，实现所述底部散热板201的散热功能。若所述载体400的表面具有金属层，则所述金属层可以保留，其不会影响所述底部散热板401的散热性能。Please refer to step S39 and FIG. 4J to remove the plastic compound on the outer surface of the side wall heat dissipation plate and remove the carrier 200 to form an enhanced heat dissipation package. In this step, the plastic sealing material on the outer surface of the side wall heat dissipation plate is removed to expose the side wall heat dissipation plate to realize the heat dissipation function of the side wall heat dissipation plate; the carrier 200 is removed to expose the bottom The lower surface of the heat sink 201 realizes the heat dissipation function of the bottom heat sink 201. If the surface of the carrier 400 has a metal layer, the metal layer can be retained, which will not affect the heat dissipation performance of the bottom heat dissipation plate 401 .
本发明还提供一种采用上述制备方法制备的增强散热型封装体。图5是本发明增强散热型封装体的第一实施例的结构示意图。请参阅图5，本发明增强散热型封装体包括至少一芯片503及一塑封体504，其中，所述塑封体504采用虚线绘示。在本具体实施方式中，示意性绘示出一个芯片503。所述塑封体504塑封所述芯片503。每一所述芯片503具有一设置有焊垫5031的上表面及一与所述上表面相对设置的下表面。在所述塑封体504底部设置有一底部散热板501。在所述塑封体504至少一侧壁设置有一侧壁散热板502。例如，在所述塑封体504的一个侧壁、两个侧壁、三个侧壁或者四个侧壁上均设置有侧壁散热板502，在本实施例中，在所述塑封体504的两个侧壁上设置有侧壁散热板502。所述侧壁散热板502与所述底部散热板501连接，在本实施例中，所述侧壁散热板502与所述底部散热板501形成U型结构。所述芯片503的下表面通过粘结剂510与所述底部散热板501连接。所述侧壁散热板502及所述底部散热板501用于为所述塑封体504散热。设置于所述塑封体504上表面的芯片输出管脚505穿过所述塑封体504与所述芯片上表面的焊垫5031连通。The invention also provides an enhanced heat dissipation type package prepared by the above preparation method. FIG. 5 is a schematic structural diagram of the first embodiment of the enhanced heat dissipation type package of the present invention. Please refer to FIG. 5 . The enhanced heat dissipation package of the present invention includes at least one chip 503 and a plastic package 504 , wherein the plastic package 504 is shown with a dotted line. In this specific embodiment, one chip 503 is schematically illustrated. The plastic encapsulation body 504 encapsulates the chip 503 . Each chip 503 has an upper surface provided with bonding pads 5031 and a lower surface opposite to the upper surface. A bottom heat dissipation plate 501 is provided at the bottom of the plastic package 504 . A side wall heat dissipation plate 502 is provided on at least one side wall of the plastic package 504 . For example, side wall heat dissipation plates 502 are provided on one side wall, two side walls, three side walls or four side walls of the plastic package body 504. In this embodiment, the side wall heat dissipation plates 502 are provided on one side wall, two side walls, three side walls or four side walls of the plastic package body 504. Side wall heat dissipation plates 502 are provided on the two side walls. The side wall heat dissipation plate 502 is connected to the bottom heat dissipation plate 501. In this embodiment, the side wall heat dissipation plate 502 and the bottom heat dissipation plate 501 form a U-shaped structure. The lower surface of the chip 503 is connected to the bottom heat dissipation plate 501 through an adhesive 510 . The side wall heat dissipation plate 502 and the bottom heat dissipation plate 501 are used to dissipate heat for the plastic package 504 . The chip output pins 505 provided on the upper surface of the plastic package 504 pass through the plastic package 504 and communicate with the bonding pads 5031 on the upper surface of the chip.
图6是本发明增强散热型封装体的第二实施例的结构示意图。请参阅图6，本发明第二实施例与第一实施例的区别在于，所述塑封体504包括一基层塑封体5041及一设置在所述基层塑封体5041表面的绝缘层508，在所述基层塑封体5041上表面设置有一重布线层，所述重布线层具有多个分别与所述芯片503的焊垫5031连接的金属垫507，所述绝缘层508覆盖所述重布线层，所述绝缘层508暴露出所述金属垫507，所述芯片输出管脚505穿过所述绝缘层508与所述重布线层的金属垫507连通。所述重布线层能够扩大所述芯片503的焊垫5031的范围，形成扇出结构。其中，所述基层塑封体504及绝缘层50采用虚线绘示。FIG. 6 is a schematic structural diagram of a second embodiment of the enhanced heat dissipation type package of the present invention. Please refer to Figure 6. The difference between the second embodiment of the present invention and the first embodiment is that the plastic package 504 includes a base plastic package 5041 and an insulating layer 508 disposed on the surface of the base plastic package 5041. In the A rewiring layer is provided on the upper surface of the base plastic package 5041. The rewiring layer has a plurality of metal pads 507 respectively connected to the soldering pads 5031 of the chip 503. The insulating layer 508 covers the rewiring layer. The insulating layer 508 exposes the metal pad 507 , and the chip output pin 505 passes through the insulating layer 508 to communicate with the metal pad 507 of the redistribution layer. The rewiring layer can expand the range of the bonding pad 5031 of the chip 503 to form a fan-out structure. Wherein, the base plastic encapsulation body 504 and the insulating layer 50 are shown with dotted lines.
以上所述仅是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员，在不脱离本发明原理的前提下，还可以做出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。The above are only preferred embodiments of the present invention. It should be noted that those of ordinary skill in the art can also make several improvements and modifications without departing from the principles of the present invention. These improvements and modifications should also be regarded as It is the protection scope of the present invention.
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