CN104659021A - Three-dimensional wafer level fan-out PoP encapsulating structure and preparation method for encapsulating structure - Google Patents

Abstract

The invention discloses a three-dimensional wafer-level fan-out PoP package structure and a manufacturing method thereof. The three-dimensional wafer-level fan-out PoP package is formed by stacking at least one fan-out PoP package unit, and the fan-out PoP package unit includes an IC chip, a metal Bump structure, plastic packaging material, metal layer, dielectric material layer, redistribution metal trace layer, solder ball. The method comprises the following steps: disposing metal substrate wafers, fabricating metal bump structures on the upper surface of the wafers, flip chip mounting, plastic packaging, making through holes on the plastic packaging material, fabricating metal bump structures in the through holes, fabricating and rewiring Metal wiring layer, configuration and removal of the wafer, etching the lower surface of the wafer to form a rewiring metal wiring layer, stacking reflow soldering, removing the wafer, planting balls and reflow soldering to form a three-dimensional wafer-level fan-out PoP package. The invention solves the problems of packaging density, cost and reliability existing in the existing PoP packaging technology.

Description

A three-dimensional wafer-level fan-out PoP packaging structure and manufacturing method thereof

technical field

The invention relates to the field of microelectronic packaging technology and three-dimensional integration technology, in particular to a three-dimensional wafer-level fan-out PoP packaging technology and a manufacturing method thereof.

Background technique

With the continuous development of electronic packaging products in the direction of high density, multi-function, low power consumption, and miniaturization, the system-level packaging (System in Package, SiP) using three-dimensional integration technology has achieved rapid development. The Through Silicon Via (TSV) technology solution is the optimal solution for realizing 3D integration technology due to its characteristics of the highest stacking density, the smallest size, greatly improved chip speed and reduced power consumption. However, the current TSV technology faces serious problems such as manufacturing difficulty, process cost, yield rate and reliability of finished products. The existing mature three-dimensional integration technology is mainly package on package (Package on Package, PoP), in which the upper and lower packages are usually package structures using printed circuit substrates. Since the printed circuit substrate has a certain thickness and high cost, it is difficult to effectively reduce the height and cost of the entire PoP package, and it is difficult to meet the requirements of high density and low cost. Due to the differences in the structure of the upper and lower packages in the existing PoP package, it is difficult to effectively control package warpage during the manufacturing process, which seriously affects the reliability of the solder ball interconnection structure. The existing PoP packaging manufacturing process adopts the traditional non-wafer level packaging manufacturing mode, resulting in low efficiency and high cost, which is not conducive to the promotion of PoP packaging.

Therefore, new packaging structures and manufacturing techniques are still needed to solve the problems existing in the prior art.

Contents of the invention

The present invention proposes a packaging structure and a manufacturing method for the three-dimensional PoP packaging technology, so as to solve the problems of packaging density, cost and reliability existing in the existing PoP packaging technology.

In order to achieve the above object, the present invention adopts the following technical solutions:

A three-dimensional wafer-level fan-out PoP packaging structure, which is formed by stacking at least one fan-out PoP packaging unit; a fan-out PoP packaging unit is composed of two packages with the same structure;

The one package includes a first metal bump structure, an IC chip, a bump, a first plastic encapsulation material, a second metal bump structure, a first redistribution metal wiring layer, a first metal layer, a first dielectric Material layer, second rewiring metal wiring layer, second dielectric material layer, and second metal layer; the IC chip has bumps, and the bumps are connected to the first metal bump structure, but not connected to the bumps The first metal bump structure is connected with the second metal bump structure, the first plastic encapsulation material surrounds the first metal bump structure, the IC chip, the bump and the second metal bump structure, and the IC chip and the second metal bump structure The structure is connected to the first redistribution metal wiring layer, the first metal wiring layer is fabricated on the first redistribution metal wiring layer, the first dielectric material layer surrounds the first redistribution metal wiring layer, and is coated on the IC chip 1. The second metal bump structure is on the same side as the first plastic encapsulation material; the second dielectric material layer is coated on the other side of the first metal bump structure and the first plastic encapsulation material, and the second dielectric material layer surrounds the second and further Wiring the metal wiring layer, the second rewiring metal wiring layer is connected to the first metal bump structure, and the first metal layer is formed on the second rewiring metal wiring layer;

The second metal layers of two opposite packages are connected by the first solder balls, and the second solder balls are connected on the first metal layer of one package to form a fan-out PoP package unit;

The second solder ball of the fan-out PoP package unit is connected with the first metal layer of a fan-out PoP package unit placed oppositely, and the first metal layer of the non-ball-planted part, the first solder ball and its connection A pair of second metal layers, a second solder ball and a pair of first metal layers connected thereto are surrounded by a second plastic encapsulation material to form a three-dimensional wafer-level fan-out PoP packaging structure.

Utilizing this structure, first of all, because the package has no substrate structure, the interconnection with the external environment can be realized directly through rewiring the metal wiring layer, so the thickness of the overall package can be greatly reduced, and the manufacturing cost can also be reduced; further, the low-cost mold Plastic through-hole TMV has the same function of interconnection and conduction between the upper and lower structures of TSV, so it can replace the TSV structure to realize fine-pitch interconnection ports, so that the number of I/O interconnection channels between the upper and lower packages and with the external structure And the density has been greatly improved, which improves the packaging density; in addition, the fan-out (Fan-Out) feature of the three-dimensional wafer-level fan-out PoP packaging structure can significantly increase the number of I/O interconnection channels of the PoP package. Finally, since all the fan-out PoP packaging units in the 3D wafer-level fan-out PoP packaging structure are the same, and all of them are stacked and reflowed in a face-to-face manner, the 3D wafer-level fan-out PoP package has a high degree of symmetry, which can be greatly improved. Improve package warpage.

The molded compound through-hole is used to realize the three-dimensional integrated interconnection between the upper and lower package bodies, as well as with the external structure.

The first metal bump structure may be but not limited to copper, copper alloy, iron, iron alloy, nickel, nickel alloy, tungsten and other metal materials.

The second metal bump structure may be, but not limited to, metal materials such as copper, copper alloy, iron, iron alloy, nickel, nickel alloy, tungsten, or brazing material.

The first redistribution metal wiring layer and the second redistribution metal wiring layer may be, but not limited to, copper, copper alloy, iron, iron alloy, nickel, nickel alloy, tungsten and other metal materials.

The first dielectric material layer and the second dielectric material layer may be, but not limited to, insulating materials such as thermosetting plastic packaging material, plugging resin, ink, and solder mask green oil.

The back surface of the IC chip, the upper surface of the first molding material and the upper surface of the second metal bump structure are on the same plane.

The three-dimensional wafer-level fan-out PoP packaging is formed by stacking at least one fan-out PoP packaging unit, and the adjacent fan-out PoP packaging units are interconnected through second solder balls.

The through holes in the first plastic sealing material are opened by laser or mechanically, or are directly formed by using a special plastic sealing mold during the plastic sealing process.

The bumps of the IC chip may be but not limited to copper pillar bumps.

A method for manufacturing a three-dimensional wafer-level fan-out PoP packaging structure, characterized in that, the steps are as follows:

Step 1: Prepare the first carrier wafer, and arrange the metal substrate wafer on the first carrier wafer through the first adhesive material;

Step 2: making a first metal bump structure on the upper surface of the metal substrate wafer by etching or electroplating;

Step 3: flip-chip mounting IC chips with bumps on the first metal bump structure;

Step 4: Using a high-temperature heating injection molding method, the first plastic sealing material is used to cover and seal the IC chip with bumps and the first metal bump structure, and expose the back of the IC chip, and then bake and cure after plastic sealing;

Step 5: Making through holes in the first plastic packaging material by laser or mechanical opening method, exposing the upper surface of the first metal bump structure;

Step 6: forming a second metal bump structure in the prepared through hole by electroplating or liquid metal filling method, the first metal bump structure and the second metal bump structure together form a molding compound through hole;

Step 7: Coating the first dielectric material layer on the back of the IC chip, the upper surface of the second metal bump structure and the upper surface of the first plastic packaging material, and making the first rewiring metal wiring layer by electroplating or electroless plating , making a first metal layer on the first redistribution metal wiring layer, and coating and wrapping the first redistribution metal wiring layer with a first dielectric material layer;

Step 8: disposing the structure formed in the above step 7 on the second carrier wafer through the third paste material;

Step 9: removing the first carrier wafer and the first paste material by mechanical, etching or exposure methods;

Step 10: Etching the lower surface of the metal substrate wafer with the same etching method as in step 2 to form a second rewiring metal wiring layer, and making a second metal layer on the second rewiring metal wiring layer, using Coating and wrapping the second redistribution metal wiring layer with the second dielectric material layer;

Step 11: performing a ball planting process on the second metal layer, and performing a reflow soldering process to obtain the first solder balls arranged in an array;

Step 12: Perform the face-to-face stacking reflow soldering process on the structure formed in the above step 11, and the first solder ball becomes the interconnection structure of the upper and lower structures;

Step 13: removing the second carrier wafer and the third paste material by mechanical, etching or exposure methods;

Step 14: Perform ball planting and reflow soldering processes on the first metal layer to obtain second solder balls arranged in an array to form a fan-out PoP packaging unit;

Step 15: Perform stacking and reflow soldering of at least one fan-out PoP packaging unit, and the second solder ball becomes the interconnection structure of the upper and lower adjacent fan-out PoP packaging units;

Step 16: Using a high-temperature heating injection molding method, the second plastic packaging material is covered and sealed, and after the plastic packaging is baked and cured, a three-dimensional wafer-level fan-out PoP package is formed;

Step 17: Using a blade cutting method to separate the product array of the 3D wafer-level fan-out PoP package to form a single 3D wafer-level fan-out PoP package.

In step 5, the through hole in the first plastic sealing material is directly formed by using a special plastic sealing mold.

Description of drawings

Fig. 1 is a schematic diagram of disposing a metal substrate wafer on a first carrier wafer;

Fig. 2 is a schematic diagram of making a first metal bump structure on a metal substrate wafer;

Fig. 3 is the schematic diagram of disposing IC chip on the metal substrate wafer;

Fig. 4 is a schematic diagram of covering and sealing the IC chip, bumps and metal bump structure in the first plastic packaging material, and exposing the back of the IC chip;

Fig. 5 is a schematic diagram of making a through hole on the first molding material;

6 is a schematic diagram of making a second metal bump structure in a through hole;

7 is a schematic diagram of making a first redistribution metal wiring layer, fabricating a first metal layer on the first redistribution metal wiring layer, and coating and wrapping the first redistribution metal wiring layer with a first dielectric material layer;

Fig. 8 is a schematic diagram of configuring a second carrier wafer;

Fig. 9 is a schematic diagram of removing the first carrier wafer;

Figure 10 is to use etching method to etch the lower surface of the metal substrate wafer to form a second rewiring metal wiring layer, and to make a second metal layer on the second rewiring metal wiring layer, using a second dielectric material A schematic diagram of layer coating wrapping the second redistribution metal trace layer;

11 is a schematic diagram of the first solder ball array obtained by performing ball planting and reflow soldering processes on the second metal layer;

12 is a schematic diagram of a face-to-face stacking reflow process;

Fig. 13 is a schematic diagram of removing the second carrier wafer;

FIG. 14 is a schematic diagram of performing ball planting and reflow soldering processes on the first metal layer to obtain a second solder ball array to form a fan-out PoP package unit;

15 is a schematic diagram of stacking and reflowing at least one fan-out PoP packaging unit;

FIG. 16 is a schematic diagram of an embodiment of a three-dimensional wafer-level fan-out PoP package.

In the figure, 100 is the first carrier wafer, 100a is the first paste material, 200 is the second carrier wafer, 200a is the third paste material, 1 is the metal substrate wafer, 2 is the first metal bump structure, 3 is the IC chip, 4 is the bump, 5 is the first plastic packaging material, 6 is the second metal bump structure, 7 is the first redistribution metal wiring layer, 8 is the first metal layer, and 9 is the first dielectric Material layer, 10 is the second redistribution metal wiring layer, 11 is the second dielectric material layer, 12 is the second metal layer, 13 is the first solder ball, 14 is the second solder ball, 15 is the second plastic packaging material .

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention clearer, the specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings.

As shown in Figure 16, a three-dimensional wafer-level fan-out PoP packaging structure is formed by stacking at least one fan-out PoP packaging unit; a fan-out PoP packaging unit is composed of two packages with the same structure;

The one package includes a first metal bump structure 2, an IC chip 3, a bump 4, a first molding material 5, a second metal bump structure 6, a first redistribution metal wiring layer 7, a first metal layer 8, a first dielectric material layer 9, a second rewiring metal wiring layer 10, a second dielectric material layer 11, and a second metal layer 12; the IC chip 3 has a bump 4, and the bump 4 is connected to On the first metal bump structure 2, a second metal bump structure 6 is connected to the first metal bump structure 2 that is not connected to the bump 4, and the first plastic encapsulation material 5 surrounds the first metal bump structure 2, the IC The chip 3, the bump 4 and the second metal bump structure 6, the IC chip 3 and the second metal bump structure 6 are connected to the first rewiring metal wiring layer 7, and the first rewiring metal wiring layer 7 is made with The first metal layer 8, the first dielectric material layer 9 surrounds the first redistribution metal wiring layer 7, and is coated on the same side of the IC chip 3, the second metal bump structure 6 and the first plastic packaging material 5; A metal bump structure 2 and the other side of the first molding material 5 are coated with a second dielectric material layer 11, the second dielectric material layer 11 surrounds the second redistribution metal trace layer 10, the second redistribution metal trace The line layer 10 is connected to the first metal bump structure 2, and the first metal layer 12 is fabricated on the second redistribution metal line layer 10;

The first solder ball 13 connects the second metal layer 12 of two opposite packages, and connects the second solder ball 14 on the first metal layer 8 of one package to form a fan-out PoP package unit;

The second solder ball 14 of the fan-out PoP package unit is connected to the first metal layer 8 of a fan-out PoP package unit placed oppositely, the first metal layer 8 and the first solder ball 13 of the non-ball-planted part A pair of second metal layers 12 connected thereto, a second solder ball 14 and a pair of first metal layers 8 connected thereto are surrounded by a second plastic encapsulation material 15 to form a three-dimensional wafer-level fan-out PoP packaging structure.

The first metal bump structure 2 and the second metal bump structure 6 may be made of, but not limited to, copper, copper alloy, iron, iron alloy, nickel, nickel alloy, tungsten metal material, or brazing material.

The first redistribution metal wiring layer 7 and the second redistribution metal wiring layer 10 may be, but not limited to, copper, copper alloy, iron, iron alloy, nickel, nickel alloy, tungsten metal material.

The first dielectric material layer 9 and the second dielectric material layer 11 may be, but not limited to, insulating materials such as thermosetting plastic packaging material, plugging resin, ink, and solder mask green oil.

The back surface of the IC chip 3 , the upper surface of the first molding material 5 and the upper surface of the second metal bump structure 6 are on the same plane.

The bumps 4 of the IC chip 3 may be but not limited to copper pillar bumps.

The following will take the three-dimensional wafer-level fan-out PoP packaging structure of the embodiment of the present invention as an example, and use FIGS. 1 to 16 to describe the manufacturing process of the three-dimensional wafer-level fan-out PoP packaging structure in detail.

Step 1: Prepare the first carrier wafer, and arrange the metal substrate wafer on the first carrier wafer through the first adhesive material, as shown in FIG. 1 .

Referring to FIG. 1 , a first carrier wafer 100 is prepared. The first carrier wafer 100 can be metal, wafer, glass, polymer organic material, etc. Referring to FIG. The metal substrate wafer 1 is disposed on the first carrier wafer 100 through the first adhesive material 100a. In the present invention, the metal substrate wafer 1 can be metal materials such as copper, copper alloy, iron, iron alloy, nickel, nickel alloy, etc., preferably copper or copper alloy material, and the first adhesive material 100a can be but not limited to adhesive tape , polymer resin and other materials. The size of the metal substrate wafer 1 is not larger than the size of the first carrier wafer 100 .

Step 2: Fabricate a first metal bump structure on the upper surface of the metal substrate wafer, as shown in FIG. 2 .

Referring to FIG. 2 , a first metal bump structure 2 is fabricated on the upper surface of the metal substrate wafer 1 . In the present invention, the first metal bump structure 2 is fabricated by etching or electroplating. In the etching method, a photosensitive wet film or a dry film is coated or pasted on the upper surface of the metal substrate wafer 1, and a pattern is made by an exposure and development method, and the photosensitive wet film or dry film with a pattern is used as a resist layer, The upper surface of the wafer 1 is etched with an etching solution that only etches the metal substrate wafer 1 to form the first metal bump structure 2 . In the electroplating method, a light-sensitive wet film or dry film with a certain thickness is coated or pasted on the upper surface of the metal substrate wafer 1, a pattern is made by exposure and development, and the first metal bump structure 2 is formed by electroplating. , the thickness of the photosensitive wet film or dry film should exceed the height dimension of the fabricated first metal bump structure 2 . In the present invention, the first metal bump structure 2 may be but not limited to copper, copper alloy, iron, iron alloy, nickel, nickel alloy, tungsten and other metal materials.

Step 3: flip-chip mounting the IC chip with bumps on the first metal bump structure, as shown in FIG. 3 .

Please refer to FIG. 3 , the IC chip 3 with bumps 4 is flip-chip mounted on the first metal bump structure 2 by using flip-chip equipment, and the electrical interconnection is realized through a reflow process. In the present invention, the bumps 4 on the IC chip 3 may be but not limited to copper stud bumps.

Step 4: Cover and seal the IC chip with bumps and the first metal bump structure in the first plastic packaging material by injection molding method, and expose the back side of the IC chip, bake and cure after plastic packaging, as shown in Figure 4 Show.

Please refer to FIG. 4 , using a high-temperature heating injection molding method, the low water absorption and low stress environment-friendly first plastic packaging material 5 is used to cover and seal the IC chip 3 with bumps 4 and the first metal bump structure 2, and the IC chip is exposed. The back of the chip 3 , the back of the IC chip 3 and the surface of the first molding material 5 are on the same plane. In the present invention, the first molding material 5 is a material such as a thermosetting polymer. After plastic sealing, a post-baking curing process is carried out.

Step 5: Make a through hole on the first molding material, exposing the upper surface of the first metal bump structure, as shown in FIG. 5 .

Please refer to FIG. 5 , laser or mechanical opening method is used to make through holes in the first plastic packaging material 5 , or in step 4, a special plastic mold is used to directly form through holes, exposing the upper surface of the first metal bump structure 2 .

Step 6: Fabricate a second metal bump structure in the through hole, as shown in FIG. 6 .

Please refer to Fig. 6, make the second metal bump structure 6 in the through hole, adopt electroplating or liquid metal filling method to form the second metal bump structure 6 in the through hole of making, the second metal bump structure 6 can be copper , copper alloy, iron, iron alloy, nickel, nickel alloy, tungsten and other metal materials, or brazing materials, but not limited to these materials. In the present invention, the second metal bump structure 6 can also be formed by solder paste printing method. The first metal bump structure 2 and the second metal bump structure 6 together form a through molding compound via TMV.

Step 7: Make the first rewiring metal wiring layer, make the first metal layer on the first rewiring metal wiring layer, and use the first dielectric material layer to coat and wrap the first rewiring metal wiring layer, as shown in the figure 7.

Please refer to Fig. 7, on the back side of IC chip 3, the upper surface of the second metal bump structure 6 and the upper surface of the first molding material 5, the first dielectric material layer 9 is coated, and the first dielectric material layer 9 is formed by exposure and development methods. A pattern is formed on the electrical material layer 9, and the first redistribution metal wiring layer 7 is fabricated by electroplating or electroless plating, and the first metal layer 8 is fabricated on the first redistribution metal wiring layer 7, and the first dielectric material layer is used 9 Coating and wrapping the first redistribution metal wiring layer 7 . In the present invention, the first redistribution metal wiring layer 7 can be, but not limited to, metal materials such as copper, copper alloy, iron, iron alloy, nickel, nickel alloy, tungsten, etc., and the first metal layer 8 can be, but not limited to, Copper, nickel, gold, titanium, tin and other metal multilayer structure combination, the first dielectric material layer 9 can be but not limited to insulating materials such as thermosetting plastic packaging material, plugging resin, ink and solder mask green oil.

Step 8: Configure the second carrier wafer, as shown in FIG. 8 .

Referring to FIG. 8 , the structure produced in the above step 7 is arranged on the second carrier wafer 200 through the third paste material 200 a. In the present invention, the second carrier wafer 200 can be metal, wafer, glass, polymer organic material, etc., and the third adhesive material 200a can be, but not limited to, adhesive tape, polymer resin and other materials.

Step 9: removing the first carrier wafer, as shown in FIG. 9 .

Referring to FIG. 9 , the first carrier wafer 100 and the first paste material 100 a are removed by mechanical, etching or exposure methods.

Step 10: Etching the lower surface of the metal substrate wafer by an etching method to form a second redistribution metal wiring layer, making a second metal layer on the second redistribution metal wiring layer, using a second dielectric material Layer coating wraps the second redistribution metal trace layer, as shown in Figure 10.

Please refer to FIG. 10, adopt the same etching method as step 2 to etch the lower surface of the metal substrate wafer 1 to form a second redistribution metal wiring layer 10, and make a second redistribution metal wiring layer 10 on the second redistribution metal wiring layer 10. The second metal layer 12 uses the second dielectric material layer 11 to coat and wrap the second redistribution metal wiring layer 10 . In the present invention, the second metal layer 12 is, but not limited to, a combination of metal multilayer structures such as copper, nickel, gold, titanium, and tin.

Step 11: Perform ball planting and reflow soldering processes on the second metal layer to obtain a first solder ball array, as shown in FIG. 11 .

Referring to FIG. 11 , a ball planting process is performed on the second metal layer 12 and a reflow soldering process is performed to obtain first solder balls 13 arranged in an array.

Step 12: The structure formed in the above step 11 is subjected to a face-to-face stacking reflow process, as shown in FIG. 12 .

Referring to FIG. 12 , the structure formed in the above step 11 is subjected to a face-to-face stacking reflow process, and the first solder ball 13 becomes an interconnection structure of the upper and lower structures.

Step 13: removing the second carrier wafer, as shown in FIG. 13 .

Referring to FIG. 13 , the second carrier wafer 200 and the third paste material 200 a are removed by mechanical, etching or exposure methods.

Step 14: Perform ball planting and reflow soldering processes on the first metal layer to obtain a second solder ball array to form a fan-out PoP packaging unit, as shown in FIG. 14 .

Referring to FIG. 14 , ball planting and reflow soldering processes are performed on the first metal layer 8 to obtain second solder balls 14 arranged in an array to form a fan-out PoP packaging unit.

Step 15: At least one fan-out PoP package unit is stacked and reflowed, as shown in FIG. 15 .

Referring to FIG. 15 , at least one fan-out PoP package unit is stacked and reflow-soldered, and the second solder ball 14 becomes an interconnection structure of upper and lower adjacent fan-out PoP package units.

Step 16: Carry out a plastic encapsulation process to form a three-dimensional wafer-level fan-out PoP package, as shown in FIG. 16 .

Please refer to FIG. 16 , using a high-temperature heating injection molding method, encapsulating and sealing the second environment-friendly plastic packaging material 15 with low water absorption and low stress, and performing a post-baking curing process after plastic packaging to form a three-dimensional wafer-level fan-out PoP package.

Step 17: Cut to form a single three-dimensional wafer-level fan-out PoP package. As shown in Figure 16, this figure is the single POP package after cutting.

The product array of the 3D wafer-level fan-out PoP package is separated by a blade cutting method to form a single 3D wafer-level fan-out PoP package.

The active surface of the IC chip refers to the surface with the integrated circuit, generally located on the surface of the chip, not shown in the figure.

The through hole of molding compound is TMV (Through Mold Via) in English.

The description of the embodiments of the present invention is for the purpose of effectively illustrating and describing the present invention, and is not intended to limit the present invention. Any person skilled in the art should understand that: within the spirit and principles of the present invention, any Modifications, equivalent replacements, improvements, etc., should all be included within the protection scope of the present invention.

Claims (8)

1. A three-dimensional wafer-level fan-out PoP packaging structure, characterized in that, it is formed by stacking at least one fan-out PoP packaging unit; a fan-out PoP packaging unit is composed of two packages of the same structure; The one package includes a first metal bump structure (2), an IC chip (3), a bump (4), a first molding material (5), a second metal bump structure (6), a first The wiring metal wiring layer (7), the first metal layer (8), the first dielectric material layer (9), the second redistribution metal wiring layer (10), the second dielectric material layer (11), the first Two metal layers (12); the IC chip (3) has bumps (4), the bumps (4) are connected to the first metal bump structure (2), and the first metal bump structure (2) is not connected to the bumps (4). A metal bump structure (2) is connected with a second metal bump structure (6), and the first plastic encapsulation material (5) surrounds the first metal bump structure (2), the IC chip (3), and the bump (4) and the second metal bump structure (6), the IC chip (3) and the second metal bump structure (6) are connected with the first rewiring metal wiring layer (7), and the first rewiring metal wiring layer (7) ) is made with a first metal layer (8), the first dielectric material layer (9) surrounds the first redistribution metal wiring layer (7), and is coated on the IC chip (3), the second metal bump structure (6) and the same side of the first molding material (5); the second dielectric material layer (11) is coated on the other side of the first metal bump structure (2) and the first molding material (5), and the second The dielectric material layer (11) surrounds the second redistribution metal wiring layer (10), the second redistribution metal wiring layer (10) is connected to the first metal bump structure (2), and the second redistribution metal wiring layer A first metal layer (12) is formed on the layer (10); The second metal layers (12) of two opposite packages are connected to the first solder balls (13), and the second solder balls (14) are connected on the first metal layer (8) of one package to form a fan Out of PoP encapsulation unit; The second solder ball (14) of the fan-out PoP package unit is connected with a first metal layer (8) of a fan-out PoP package unit placed oppositely, and the first metal layer (8) of the non-ball-planted part , the first solder ball (13) and a pair of second metal layers (12) connected thereto, the second solder ball (14) and a pair of first metal layers (8) connected thereto are surrounded by a second plastic encapsulation material (15 ), forming a three-dimensional wafer-level fan-out PoP packaging structure. 2. A three-dimensional wafer-level fan-out PoP packaging structure according to claim 1, wherein the first metal bump structure (2) and the second metal bump structure (6) are but not limited to copper, Copper alloy, iron, iron alloy, nickel, nickel alloy, tungsten metal material or brazing material. 3. A kind of three-dimensional wafer-level fan-out PoP packaging structure according to claim 1, characterized in that, the first rewiring metal wiring layer (7) and the second rewiring metal wiring layer (10) are but not Limited to copper, copper alloys, iron, iron alloys, nickel, nickel alloys, or tungsten metal materials. 4. A three-dimensional wafer-level fan-out PoP packaging structure according to claim 1, characterized in that, the first dielectric material layer (9) and the second dielectric material layer (11) are but not limited to thermosetting plastic packaging material, plugging resin, ink or solder mask insulating material. 5. a kind of three-dimensional wafer-level fan-out PoP packaging structure according to claim 1, is characterized in that, the back side of IC chip (3), the upper surface of the first molding material (5) and the second metal bump structure ( 6) The upper surfaces are on the same plane. 6. A three-dimensional wafer-level fan-out PoP packaging structure according to claim 1, characterized in that the bumps (4) of the IC chip (3) are but not limited to copper pillar bumps. 7. A method for manufacturing a three-dimensional wafer-level fan-out PoP packaging structure, characterized in that, proceed according to the following steps: Step 1: preparing a first carrier wafer (100), disposing the metal substrate wafer (1) on the first carrier wafer (100) through a first adhesive material (100a); Step 2: Fabricate a first metal bump structure (2) on the upper surface of the metal substrate wafer (1) by etching or electroplating; Step 3: flip-chip mounting the IC chip (3) with bumps (4) on the first metal bump structure (2); Step 4: Using a high-temperature heating injection molding method, the first plastic sealing material (5) is used to cover and seal the IC chip (3) with bumps (4) and the first metal bump structure (2), and the IC chip (3) is exposed ) on the back side, bake and solidify after plastic sealing; Step 5: Making through holes in the first plastic packaging material (5) by laser or mechanical opening method, exposing the upper surface of the first metal bump structure (2); Step 6: Forming a second metal bump structure (6) in the through-hole by electroplating or liquid metal filling, the first metal bump structure (2) and the second metal bump structure (6) together form a molding compound through hole; Step 7: Coating the first dielectric material layer (9) on the back surface of the IC chip (3), the upper surface of the second metal bump structure (6) and the upper surface of the first molding material (5), using electroplating or The first redistribution metal wiring layer (7) is produced by the electroless plating method, the first metal layer (8) is fabricated on the first redistribution metal wiring layer (7), and the first dielectric material layer (9) is used for coating Wrapping the first redistribution metal wiring layer (7); Step 8: disposing the structure produced in the above step 7 on the second carrier wafer (200) through the third paste material (200a); Step 9: removing the first carrier wafer (100) and the first paste material (100a) by mechanical, etching or exposure methods; Step 10: Etching the lower surface of the metal substrate wafer 1 using the same etching method as in step 2 to form a second rewiring metal wiring layer (10), on the second rewiring metal wiring layer (10) Making the second metal layer (12), coating and wrapping the second redistribution metal wiring layer (10) with the second dielectric material layer (11); Step 11: performing a ball planting process on the second metal layer (12), and performing a reflow soldering process to obtain first solder balls (13) arranged in an array; Step 12: Perform the face-to-face stacking reflow soldering process on the structure formed in the above step 11, and the first solder ball (13) becomes the interconnection structure of the upper and lower structures; Step 13: removing the second carrier wafer (200) and the third paste material (200a) by mechanical, etching or exposure methods; Step 14: performing ball planting and reflow soldering processes on the first metal layer (8) to obtain second solder balls (14) arranged in an array to form a fan-out PoP packaging unit; Step 15: Perform stacking and reflow soldering of at least one fan-out PoP packaging unit, and the second solder ball (14) becomes the interconnection structure of the upper and lower adjacent fan-out PoP packaging units; Step 16: Using a high-temperature heating injection molding method, the second plastic packaging material (15) is covered and sealed, and after plastic sealing, a baking and post-curing process is performed to form a three-dimensional wafer-level fan-out PoP package; Step 17: Using a blade cutting method to separate the product array of the 3D wafer-level fan-out PoP package to form a single 3D wafer-level fan-out PoP package. 8 . The manufacturing method of a three-dimensional wafer-level fan-out PoP packaging structure according to claim 7 , wherein the through holes in the first plastic sealing material in the step 5 are directly formed by using a special plastic sealing mold.