CN108241117A - System and method for testing semiconductor devices - Google Patents

Abstract

The present disclosure provides a system for testing semiconductor components, which includes a data generating device, a data testing device, and a data processing device. The data processing device is configured to send a first command to the data testing device and to send a first response to the data generating device after sending the first command. After receiving the first response, the data generating device transmits a first data to the data processing device.

Description

System and method for testing semiconductor components

technical field

The present disclosure relates to a system for testing a semiconductor device and a method for testing a semiconductor device.

Background technique

Generally speaking, after the chip (such as an integrated circuit chip) is manufactured, an electrical test is performed to determine whether the chip is a good product with normal electrical properties, so as to ensure the quality of the chip when it is shipped. In the field of semiconductor testing, test time is an important factor in automatic testing that affects throughput. Generally speaking, production capacity is measured by the number of units that can be completed per hour (unit per hour). Test time is affected by three factors: the design of the test method, the degree of optimization of the test program, and the performance of the test system. The performance of the test system mainly depends on: the execution speed of the hardware, the execution efficiency of the software, and the communication time between the hardware and software.

In the traditional chip testing process, every time the hardware test terminal executes a test, it must wait for the application programming interface (Application Programming Interface, API) in the computer of the tester to generate the next test command, and write the test command After entering the memory of the machine control unit, the hardware test terminal can obtain the next test command through the machine control unit. Therefore, when a large number of tests are performed, the time for the hardware tester to wait for the next test command will reduce the test efficiency.

In order to reduce the time spent on communication between hardware and software, an embedded system test method has been developed. In the embedded system test process, all test program codes are pre-burned into the hard disk of the hardware test terminal. Therefore, every time the hardware test After the terminal executes a test command, it can immediately retrieve the next test command from the memory of the hardware test terminal.

However, although embedded systems can reduce instruction transmission time, they also bring other problems. As more and more functions are embedded in the hardware for execution, the modification flexibility of the test process becomes smaller. Because all the program codes are pre-burned into the hard disk of the hardware tester, when the program codes are abnormal or the test results are abnormal, the test cannot be interrupted directly and the test program codes are debugged, causing the R&D personnel to correct and adjust the test program The code is inconvenient, so the embedded system testing method has not been widely used. Therefore, there is an urgent need for a semiconductor testing system and method, which can improve the efficiency of the traditional chip testing process, and can also efficiently eliminate the abnormality of the testing procedure.

Contents of the invention

An embodiment of the present disclosure provides a system for testing a semiconductor device, which includes a data generating device, a data testing device, and a data processing device. The data processing device is configured to send a first command to the data testing device and send a first response to the data generating device after sending the first command. After receiving the first response, the data generating device transmits a first data to the data processing device.

Another embodiment of the present disclosure provides a method for testing a semiconductor device, which includes providing a data generating device, providing a data processing device, and providing a data testing device. The method further includes: sending a first command to the data testing device at a first time by the data processing device, so that the data testing device performs a test according to the first command; and sending the first command to the data testing device After the device is installed, the data processing device sends a first response to the data generating device. Wherein the data generating device transmits a first data to the data processing device according to the received first response.

The semiconductor testing system and semiconductor testing method described in this disclosure can improve the efficiency of semiconductor testing, reduce the usage of memory in the semiconductor testing system, and increase the efficiency of troubleshooting abnormalities in testing procedures.

Description of drawings

FIG. 1 is a schematic diagram of a semiconductor testing system.

FIG. 2 is a schematic diagram of a semiconductor testing system according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of a semiconductor testing method according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of a semiconductor test system according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a semiconductor testing method according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of a semiconductor testing method according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of a semiconductor testing system according to an embodiment of the present invention.

FIG. 8 is a schematic diagram of a semiconductor testing method according to an embodiment of the present invention.

FIG. 9 is a schematic diagram of a semiconductor testing system according to an embodiment of the present invention.

FIG. 10 is a schematic diagram of a semiconductor testing method according to an embodiment of the present invention.

Detailed ways

The present disclosure provides several different implementation methods or embodiments, which can be used to realize different features of the present invention. For simplicity of illustration, the present disclosure also describes examples of certain components and arrangements. Please note that these specific examples are provided for illustration purposes only and are not intended to be limiting.

As used herein, the terms "first", "second", "third" and "fourth" describe various components, components, steps, signals or commands that Orders shall not be limited by these terms. These terms are only used to distinguish one component, component, step, signal or command from another component, component, step, signal or command. Terms such as "first," "second," "third," and "fourth," when used herein, do not imply a sequence or order unless clearly indicated by the context.

FIG. 1 shows a schematic diagram of a semiconductor testing system. As shown in FIG. 1 , the semiconductor testing system includes a testing computer 100 , a machine control unit 120 , a hardware testing machine 140 and a load board 180 . The testing computer 100 , the machine control unit 120 , the hardware testing machine 140 and the load board 180 are electrically connected to each other for transmitting signals and commands, and the device under test 160 is mounted on the load board 180 . Generally speaking, the device under test can be an integrated circuit chip.

The test computer 100 includes a processor 102 and a memory 104 . The test computer 100 generates test data through the API installed thereon and stores them in the memory 104 . The machine control unit 120 includes a processor 122 , a memory 124 and an input/output port 126 . The machine control unit 120 can receive test data from the test computer 100 and process the test data to generate test commands. The test commands can be stored in the memory 124 and sent to the hardware testing machine 140 through the input/output port 126 .

The hardware tester 140 may include a plurality of modules for testing semiconductor devices. For example, the hardware testing machine 140 may include a direct current module 142 , a precision measurement unit (Precision Measurement Unit, PMU) 144 , a digital module 146 and a relay board 148 . According to the content of the generated test command, the machine control unit 120 sends the test command to the corresponding modules of the hardware tester 140 via the input/output port 126 .

The DC module 142 provides measurement of DC parameters of semiconductor devices. For example, the direct current module 142 can provide test current to the semiconductor device to be tested, and measure the corresponding voltage of the semiconductor device. Alternatively, the DC module 142 can provide a test voltage to the semiconductor device to be tested and measure the corresponding current of the semiconductor device.

The precise measurement unit 144 also provides the measurement of the DC parameters of the semiconductor device. However, compared with the direct current module 142 , the precision measurement unit 144 can provide higher accuracy measurement. Generally speaking, the precise measurement unit 144 is aimed at the test of small current and small voltage. Because it provides smaller voltage and current, it must have better accuracy.

In the test of the integrated circuit chip, in addition to the above-mentioned electrical measurement for the direct current, it is also necessary to test the different functions of the integrated circuit chip. The digital module 146 can perform signal sending and receiving tests for various digital functions of the integrated circuit. For example, the digital module 146 can perform signal sending and receiving tests on digitally controlled I2C bus (Inter-Integrated Circuit Bus), TTL (Transistor-transistor logic), SPI (Serial Peripheral Interface) and baseband Tx/Rx of integrated circuits. In order to perform the above tests, the digital module 146 can set not only voltage level and current value, but also signal switching frequency, voltage rising/falling edge, synchronization of receiving/sending time, etc. Generally speaking, the voltage range that the digital module 146 can provide is relatively small, which is approximately close to that of the precision measurement unit 144 . In one embodiment, the digital module 146 can also provide all the functions of the precision measurement unit 144 .

The relay version 148 can provide the path switching function of the hardware testing machine 140 . In the testing of semiconductor components, the number of testing channels available for the hardware testing machine 140 is often insufficient due to cost constraints or too many pins of the device under test. In this case, there must be pins sharing the same test channel, and the control switching can be performed through the relay board 148 .

FIG. 2 is a schematic diagram of a semiconductor testing system 200 according to an embodiment of the present invention. As shown in FIG. 2 , the semiconductor testing system 200 includes a data generating device 220 , a data processing device 240 and a data testing device 260 . The data generating device 220 , the data processing device 240 and the data testing device 260 are electrically connected to each other to transmit signals and instructions. The device under test 280 is installed on the data testing device 260 . The data processing device 240 includes a processor 242 and a memory 244 .

The data generating device 220 can generate test data. After receiving the test data from the data generating device 220 , the data processing device 240 processes the test data and generates a test command. Processing of test data and generation of test commands are performed by processor 242 . The data testing device 260 can test the device under test 280 according to the test command from the data processing device 240 . In one embodiment of the present invention, after the data processing device 240 transmits the test command to the data testing device 260 , the data processing device 240 then generates a response to the data generating device 220 . After receiving the response, the data generating device 220 generates the next test data and sends it to the data processing device 240 .

The data processing device 240 will receive the next test data for processing and generate the next test order. After the data testing device 260 completes the test according to the current test command, it will generate a response to the data processing device 240 , and the data processing device 240 can then send the next test command to the data testing device 260 .

It should be noted that, in this embodiment, the data generating device 220 does not need to wait for the data testing device 260 to complete the current test command before generating the test data for the next test. The data processing device 240 has completed the processing of the next test data and generated the next test command before the data testing device 260 completes the current test command. In this manner, the multiple tests performed by the data testing device 260 can continue without interruption, greatly reducing the waiting time spent in communication between software and hardware in the semiconductor testing system.

In addition, the data processing device 240 can determine whether the test command is executed correctly according to the response returned by the data testing device 260 . If the data processing device 240 judges that the response returned by the data testing device 260 is abnormal, it can generate a corresponding warning message, so that the research and development personnel can correct and adjust the test program code in real time, which can increase the efficiency of abnormal elimination.

FIG. 3 is a schematic diagram of a semiconductor testing method according to an embodiment of the present invention. As shown in Figure 3, the semiconductor testing method of the present embodiment includes the following steps:

Step 302: the data processing device 240 processes the first data from the data generating device 220, generates a first command and sends the first command to the data testing device 260;

Step 304: the data testing device 260 tests the device under test 280 according to the first command;

Step 306: the data processing device 240 transmits the first response to the data generating device 220;

Step 308: After receiving the first response from the data processing device 240, the data generating device 220 generates second data for the next test, and sends the second data to the data processing device 240;

Step 310: the data processing device 240 processes the second data and generates a second command for the next test;

Step 312: After the data testing device 260 finishes testing the first command, the data processing device 240 transmits the second command to the data testing device 260; and

Step 314: The data testing device 260 tests the device under test 280 according to the second command.

It should be noted that there is not necessarily a time difference between step 304 and step 306, that is to say, step 304 and step 306 can be started at the same time.

FIG. 4 is a schematic diagram of a semiconductor test system 400 according to an embodiment of the present invention. As shown in FIG. 4 , the semiconductor testing system 400 includes a data generating device 420 , a data processing device 440 and a data testing device 460 . The data generating device 420 , the data processing device 440 and the data testing device 460 are electrically connected to each other to transmit signals and instructions. The device under test 480 is installed on the data testing device 460 . The data generating device 420 includes a memory 422 . The data processing device 440 includes a processor 442 and a memory 444 .

In this embodiment, the data generating device 420 generates a piece of test data according to the first response sent by the data processing device 440 . Whenever the data generating device 420 generates a piece of test data, it does not directly transmit the test data to the data processing device 440 , but stores the test data in the memory 422 first. After receiving a second response from the data processing device 440 , the data generating device 420 transmits the test data to the data processing device 440 .

After the data processing device 440 sends a test command to the data testing device 460, it sends a first response to the data generating device. The data processing device 440 may transmit the second response according to different situations. Generally speaking, when the data processing device 440 finishes processing the current test data and can process the next test data, it will send the second response to the data generating device 420 .

In this embodiment, the data generating device 420 generates test data according to the first response sent by the data processing device 440 , which can prevent the data generating device 420 from continuously generating test data, thereby reducing the memory usage of the data generating device 420 . In addition, the data processing device 440 can determine whether the test command is executed correctly according to the response returned by the data testing device 460 . The transmission of the first response and the second response and the judgment of abnormality are performed by the processor 442 . If the data processing device 440 judges that the response returned by the data testing device 460 is abnormal, it can generate a corresponding warning message, so that the research and development personnel can correct and adjust the test program code in real time, which can increase the efficiency of abnormal elimination.

FIG. 5 is a schematic diagram of a semiconductor testing method according to an embodiment of the present invention. The semiconductor testing method shown in FIG. 5 corresponds to some operation steps of the semiconductor testing system 400 shown in FIG. 4 . As shown in Figure 5, the semiconductor testing method of the present embodiment includes the following steps:

Step 502: the data processing device 440 transmits the first response to the data generating device 420;

Step 504: in response to the first response, the data generating device 420 generates first data and stores the first data in the memory 422;

Step 506: the data processing device 440 transmits the second response to the data generating device 420; and

Step 508 : In response to the second response, the data generating device 420 transmits the first data stored in the memory 422 to the data processing device 440 .

Step 510 : The data processing device 440 stores the first data in the memory 444 .

FIG. 6 is a schematic diagram of a semiconductor testing method according to an embodiment of the present invention. The semiconductor testing method shown in FIG. 6 may correspond to some operation steps of the semiconductor testing system shown in FIGS. 2 , 4 , 7 and 9 . For the convenience of description, the semiconductor test system 200 shown in FIG. 2 is taken as an example for description.

As shown in Figure 6, the semiconductor testing method of the present embodiment includes the following steps:

Step 602: the data processing device 240 processes the second data from the data generating device 220 and generates a second command;

Step 604: the data testing device 260 completes the test according to the first command;

Step 606: the data testing device 260 sends a third response to the data processing device 240;

Step 608: the data processing device 240 sends the second command to the data testing device 260; and

Step 610: The data test device 260 performs a test according to the second command.

It should be noted that in this embodiment, step 602 must be earlier than step 606 in time, so that the data processing device 240 has completed the second data before the data testing device 260 completes the test according to the first command. processing and has generated a second command. In this manner, the multiple tests performed by the data testing device 260 can continue without interruption, greatly reducing the waiting time spent in communication between software and hardware in the semiconductor testing system.

FIG. 7 is a schematic diagram of a semiconductor testing system 700 according to an embodiment of the present invention. As shown in FIG. 7 , the semiconductor testing system 700 includes a data generating device 720 , a data processing device 740 and a data testing device 760 . The data generating device 720 , the data processing device 740 and the data testing device 760 are electrically connected to each other to transmit signals and instructions. The device under test 780 is installed on the data testing device 760 . The data processing device 740 includes a processor 742 , a first memory 744 and a second memory 746 .

In this embodiment, the data generating device 720 transmits the encoded test data to the data processing device 740 . After the data processing device 740 receives the coded test data, it first stores it in the first memory 744 . After the encoded test data is stored in the first memory 744 , the data processing device 740 returns a response to the data generating device 720 , so that the data generating device 720 generates the next test data. The processor 742 of the data processing device 740 decodes the test data stored in the first memory 744 and processes and generates test commands. The generated test command will be stored in the second memory 746 . At this time, the data processing device 740 will send a response to the data generating device 720 , so that the data generating device 720 will send the next piece of encoded test data to the data processing device 740 and store it in the first memory 744 .

Whenever a test is completed, the data testing device 760 sends a response to the data processing device 740 , and then the data processing device 740 sends the test command stored in the second memory 746 to the data testing device 760 . After the test command in the second memory 746 is sent to the data testing device 760, the data processing device 740 decodes the test data stored in the first memory 744, and processes to generate the next test command. The next test command generated will be stored in the second memory 746 .

FIG. 8 is a schematic diagram of a semiconductor testing method according to an embodiment of the present invention. The semiconductor testing method shown in FIG. 8 corresponds to a part of operation steps of the semiconductor testing system 700 shown in FIG. 7 . As shown in Figure 8, the semiconductor testing method of this embodiment includes the following steps:

Step 802: the data generating device 720 transmits the encoded first data to the data processing device 740, and the data processing device 740 stores the encoded first data in the first memory 744;

Step 804: the data processing device 740 transmits the first response to the data generating device 720, so that the data generating device 720 generates encoded second data;

Step 806: The data processing device 740 decodes the encoded first data, processes and generates the first command and stores the first command in the second memory 746;

Step 808: the data processing device 740 sends the second response to the data generating device 720, so that the data generating device 720 transmits the encoded second data to the data processing device 740 and stores it in the first memory 744; and

Step 810 : the data testing device 760 sends a third response to the data processing device 740 , so that the data processing device 740 sends the first command to the data testing device 760 .

It should be noted that, in this embodiment, the data generating device 720 has sent the next test data to the data processing device 740 and stored it in the first memory before the data testing device 760 completes the current test command. And the data processing device 740 has already decoded and generated the next test command and stored it in the second memory before the data test device 760 completes the current test command. In this manner, whenever the data testing device 760 completes a test, it can immediately obtain the command for the next test after returning a response to the data processing device 740 . Therefore, the multiple tests performed can continue without interruption, greatly reducing the waiting time spent in communication between hardware and software in the semiconductor test system.

FIG. 9 is a schematic diagram of a semiconductor testing system according to an embodiment of the present invention. As shown in FIG. 9 , the semiconductor testing system 900 includes a data generating device 920 , a data processing device 940 and a data testing device 960 . The data generating device 920 , the data processing device 940 and the data testing device 960 are electrically connected to each other to transmit signals and instructions. The device under test 980 is installed on the data testing device 960 . The data processing device 940 includes a processor 942 , a memory 944 and a register 946 .

In this embodiment, the data generating device 920 transmits the encoded test data to the data processing device 940 . After the data processing device 940 receives the coded test data, it first stores it in the memory 944 . When the data processing device 940 receives a response from the data testing device 960, notifying that the current test has been completed, the processor 942 of the data processing device 940 decodes the test data stored in the memory 944 and simultaneously synchronizes the test data through the register 946 Send to the data testing device 960. That is, the data processing device 940 does not need to store the next test command generated in the memory. The memory usage of the data processing device 940 can be saved.

FIG. 10 is a schematic diagram of a semiconductor testing method according to an embodiment of the present invention. The semiconductor testing method shown in FIG. 10 corresponds to a part of operation steps of the semiconductor testing system 900 shown in FIG. 9 . As shown in Figure 10, the semiconductor testing method of this embodiment includes the following steps:

Step 1002: the data generating device 920 transmits the encoded test data to the data processing device 940;

Step 1004: the data processing device 940 stores the coded test data in the memory 944;

Step 1006: the data testing device 960 sends a response to the data processing device 940;

Step 1008: The data processing device 940 decodes the encoded test data in the memory 944 to generate a test command, and synchronously transmits it to the data test device 960 through the register 946 .

While the invention has been described and illustrated with reference to particular embodiments of the invention, such description and illustration do not limit the invention. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the invention as defined by the appended claims. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, method or component to the objective, spirit and scope of the invention. All such modifications are intended to be within the scope of the patent claims appended hereto. Although methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that such operations may be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. . Thus, unless specifically indicated herein, the order and grouping of operations is not limiting of the invention.

Claims (14)

1. A system for testing semiconductor components comprising: a data generating device; a data testing device; and a data processing device configured to transmit a first command to the data testing device and to transmit a first response to the data generating device after transmitting the first command, Wherein after receiving the first response, the data generating device transmits a first data to the data processing device. 2. The system according to claim 1, wherein said data processing means comprises: a processor; and a first memory; The processor is configured to process the first data and generate a second command, and store the second command in the first memory. 3. The system of claim 2, wherein the data generating means is responsive to the first response to generate the first data. 4. The system of claim 2, wherein the data generating means transmits the first data to the data processing means in response to a second response from the data processing means. 5. The system of claim 4, wherein the data processing device is configured to transmit the second command stored in the first memory to the data testing device in response to a third response . 6. The system of claim 5, wherein the transmission of the first data is completed before the data processing device receives the third response. 7. The system of claim 2, wherein The data processing device further includes a buffer; and The data processing device is configured to synchronously transmit the second command to the data testing device via the buffer while processing the first data in response to a third response. 8. The system of claim 2, wherein the data processing device further comprises: a second memory, where The data processing device is configured to dump the second command from the first memory into the second memory before transmitting the first response to the data generating device. 9. The system of claim 8, wherein the data processing device is configured to transmit the second command stored in the second memory to the data testing device in response to a third response. 10. A method for testing a semiconductor assembly comprising: providing a data generating device; providing a data processing device; and providing a data testing device; Sending a first command to the data testing device at a first time by the data processing device, so that the data testing device performs a test according to the first command; After the first command is sent to the data testing device, the data processing device sends a first response to the data generating device; The data generating device transmits a first data to the data processing device according to the received first response. 11. The method of claim 10, further comprising processing, by the data processing device, the first data and generating a second command. 12. The method of claim 10, wherein The data generating means generates the first data in response to the first response, and transmits the first data to the data processing means in response to a second response from the data processing means. 13. The method of claim 11, wherein the data processing device synchronously transmits the second command to the data testing device while processing the first data in response to a third response. 14. The method of claim 13, wherein the transmission of the first data is completed before the data processing device receives the third response.