CN111856246B - High-speed synchronous trigger bus circuit and synchronous trigger method - Google Patents
High-speed synchronous trigger bus circuit and synchronous trigger method Download PDFInfo
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- CN111856246B CN111856246B CN202010668804.4A CN202010668804A CN111856246B CN 111856246 B CN111856246 B CN 111856246B CN 202010668804 A CN202010668804 A CN 202010668804A CN 111856246 B CN111856246 B CN 111856246B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0002—Serial port, e.g. RS232C
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Automation & Control Theory (AREA)
- Tests Of Electronic Circuits (AREA)
- X-Ray Techniques (AREA)
- Traffic Control Systems (AREA)
- Logic Circuits (AREA)
Abstract
The invention relates to a high-speed synchronous trigger bus circuit, and belongs to the technical field of chip testing devices. The method is characterized in that: the device comprises a central control board part and a test board card part, wherein each part comprises an FPGA chip, a circuit interface and a high-speed communication interface; the FPGA chip is provided with a synchronous signal output end with two ports and a synchronous signal receiving end with two ports; the FPGA chip of the central control panel part is connected with the communication bus of the upper computer through a circuit interface, and the FPGA chip of the test board part is connected with the functional unit of the chip test device through the circuit interface; the synchronous signal output end of the central control board part, the synchronous signal receiving end of the test board card part, the synchronous signal output end of the test board card part and the synchronous signal receiving end of the central control board part are all connected with each other through a high-speed communication cable. The invention provides high-speed synchronous trigger signal input and output by utilizing the LVDS port signal characteristic of the FPGA chip, and avoids interference.
Description
Technical Field
The invention relates to a high-speed synchronous triggering bus circuit and a synchronous triggering method, and belongs to the technical field of chip testing devices.
Background
Automatic Test Equipment (ATE) is commonly used to test logic on manufactured chips in the field of chip manufacturing, ensuring that the performance on the chip meets design requirements. Different test projects are usually arranged in the automatic tester, different test boards are designed, and the central control board and each test board are synchronously triggered through buses. The internal communication of synchronous triggering communication is divided into parallel communication and serial communication, wherein the parallel communication generally transmits each bit of a data byte by using a plurality of data lines at the same time, but a plurality of data lines and control lines are needed, so that more resources are occupied for the whole system, and the running speed is limited due to the difficulty of data bit alignment; serial communication is usually a mode of splitting data into one bit and one bit, and transmits the data on a single data line, which has the advantages of saving system resources and extremely high single line transmission speed (which can reach 5 Gbps). However, the common ground between the boards makes the low-frequency disturbance between the two communication end boards mutually affect, which is not in line with the requirement of high-speed synchronous triggering in the chip test.
Disclosure of Invention
The invention provides a high-speed synchronous trigger bus circuit, which solves the problem of safe and high-speed communication between a central control board and each test board card.
The technical scheme is as follows:
a high speed synchronous trigger bus circuit, characterized by: the device comprises a central control board part and a test board card part, wherein each part comprises an FPGA chip, a circuit interface and a high-speed communication interface; the FPGA chip is provided with a synchronous signal output end with two ports and a synchronous signal receiving end with two ports; the FPGA chip of the central control panel part is connected with the communication bus of the upper computer through a circuit interface, and the FPGA chip of the test board card part is connected with the functional unit of the chip test device through the circuit interface; the synchronous signal output end of the central control board part, the synchronous signal receiving end of the test board card part, the synchronous signal output end of the test board card part and the synchronous signal receiving end of the central control board part are all connected with each other through a high-speed communication cable.
Furthermore, the central control board part and the test board part do not share the ground, so that low-frequency disturbance among the boards is effectively isolated.
Further, the synchronous signal output end and the synchronous signal receiving end of the FPGA chip are LVDS signal ports
Further, the high-speed communication cable is a differential coaxial cable.
Furthermore, a capacitor is respectively connected in front of the synchronous signal receiving ends of the two ends of the FPGA chip for direct current isolation.
Further, the capacity of the capacitor is 10nF.
The FPGA chip at the transmitting end decomposes the synchronous trigger signal into first class data and second class data, encodes the first class data into third class data, encodes the second class data into fourth class data, and then transmits the third class data and the fourth class data, and the FPGA chip at the receiving end decodes the received third class data and the received fourth class data into the first class data and the second class data and synthesizes the synchronous trigger signal.
The first type data and the second type data are opposite to each other, the third type data and the fourth type data are formed by combining the first type data and the second type data at intervals, and the first type data and the second type data are opposite to each other, for example, the first type data are 0, the second type data are 1, the third type data are 01, the fourth type data are 10 or the first type data are 0, the second type data are 1, the third type data are 010, and the fourth type data are 101; the synchronous trigger signals of the transmitting end and the receiving end are different by a fixed clock period, the different clock period is equal to the length difference value of the third type data and the first type data or the fourth type data and the second type data, 01 and 0 or 10 and 1 are different by one period, and 010 and 0 or 101 and 1 are different by two periods.
The beneficial effects are that:
1) The invention provides high-speed synchronous trigger signal input and output by utilizing the signal characteristic of a high-speed port LVDS (low voltage differential signal) of an FPGA (field programmable gate array) chip, does not need an additional driving circuit, and reduces the cost.
2) The common high-speed differential coaxial cable is matched with the capacitance detection and the direct isolation of the receiving end to realize uploading and distributing of internal synchronous trigger signals, direct current isolation among boards is realized, boards with different voltages are supported to be connected with each other, and common-ground interference is avoided.
3) And the special synchronous triggering method is matched, the triggering of the system is completed in extremely low delay (with fixed delay of only one clock), and the testing efficiency of the whole ATE testing system is improved. Meanwhile, when a plurality of instrument boards work cooperatively, the instrument boards work under the same delay condition, so that the strict synchronous triggering of a large system can be ensured, and the problem that the triggering asynchronism among the multiple boards is caused by the traditional triggering bus is avoided.
Drawings
FIG. 1 is a schematic diagram of a high-speed synchronous trigger bus circuit according to the present invention;
FIG. 2 is a schematic representation of an embodiment of the present invention;
FIG. 3 is a schematic diagram of a coding scheme of the synchronous triggering method;
FIG. 4 is a schematic diagram of another encoding scheme of the synchronous triggering method;
Wherein: 1 is a central control board part, 2 is a test board card part, 3 is an FPGA chip, 4 is a high-speed communication cable, 5 is a capacitor, 6 is an upper computer, and 7 is a functional unit.
Detailed Description
The invention is described in detail below with reference to the attached drawings and the specific embodiments:
As shown in fig. 1, a high-speed synchronous trigger bus circuit is divided into a central control board part 1 and a test board card part 2, wherein each part comprises an FPGA chip 3, a circuit interface and a high-speed communication interface; the FPGA chip 3 is provided with a synchronous signal output end with two ports and a synchronous signal receiving end with two ports; the FPGA chip 3 of the central control panel part 1 is connected with the communication bus of the upper computer 6 through a circuit interface, and the FPGA chip 3 of the test board card part 2 is connected with the functional unit 7 of the chip test device through the circuit interface; the synchronous signal output end of the central control board part 1 and the synchronous signal receiving end of the test board part 2, the synchronous signal output end of the test board part 2 and the synchronous signal receiving end of the central control board part 1 are all connected with each other through the high-speed communication cable 4.
The central control board part 1 and the test board part 2 do not share the ground, so that low-frequency disturbance among the boards is effectively isolated.
The synchronous signal output end and the synchronous signal receiving end of the FPGA chip 3 are LVDS signal ports.
The high-speed communication cable 4 is a differential coaxial cable.
And a capacitor 5 is respectively connected in front of the synchronous signal receiving ends of the two ends of the FPGA chip 3 for direct current isolation.
The capacity of the capacitor 5 is 10nF.
The FPGA chip at the transmitting end decomposes the synchronous trigger signal into first class data and second class data, encodes the first class data into third class data, encodes the second class data into fourth class data, and then transmits the third class data and the fourth class data, and the FPGA chip at the receiving end decodes the received third class data and the received fourth class data into the first class data and the second class data and synthesizes the synchronous trigger signal.
The first type data and the second type data are opposite to each other, the third type data and the fourth type data are formed by combining the first type data and the second type data at intervals, the first type data and the fourth type data are opposite to each other, the synchronous trigger signals of the sending end and the receiving end are different by a fixed clock period, and the different clock period is equal to the length difference value between the third type data and the first type data or between the fourth type data and the second type data.
Example 1 as shown in fig. 3: the FPGA chip connected with the circuit of the central control board part of the PC upper computer decomposes an internal synchronous trigger signal transmitted by the ATE test device through a bus into first class data 0 and second class data 1, encodes the data 0 into data 01, encodes the data 1 into data 10, transmits the data to the test board part through a high-speed communication cable, decodes the signal correspondingly, restores the data 01 into data 0, restores the data 10 into data 1, simultaneously encodes the signal fed back by the test board to the central control board through the FPGA chip, transmits the signal to the central control board through the high-speed communication cable, decodes the signal correspondingly after receiving the signal by the FPGA chip of the central control board part, and the signals of the transmitting end and the receiving end differ by one clock interval. And the FPGA chip performs direct current isolation on the received signals through a 10nF capacitor at the synchronous signal receiving end, so that voltage floating between the central control board and the test board card is ensured, and the transmitted signal data is not interfered.
Example 2 as shown in fig. 4: the FPGA chip connected with the circuit of the central control board part of the PC upper computer decomposes an internal synchronous trigger signal transmitted by the ATE test device through a bus into first class data 0 and second class data1, encodes the data 0 into data 10, encodes the data1 into data 01, transmits the data 01 to the test board part through a high-speed communication cable, decodes the signal correspondingly, restores the data 10 into data 0, restores the data 01 into data1, encodes the signal fed back by the test board to the central control board through the FPGA chip, transmits the signal to the central control board through the high-speed communication cable, decodes the signal correspondingly after receiving the signal by the FPGA chip of the central control board part, and the signals of the transmitting end and the receiving end are identical in phase difference by one clock interval, and the rest parts are identical to those in the embodiment 1.
The foregoing description of the preferred embodiment of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.
Claims (6)
1. A high speed synchronous trigger bus circuit, characterized by: the device comprises a central control board part (1) and a test board card part (2), wherein each part comprises an FPGA chip (3), a circuit interface and a high-speed communication interface; the FPGA chip (3) is provided with a synchronous signal output end with two ports and a synchronous signal receiving end with two ports; the FPGA chip (3) of the central control board part (1) is connected with the communication bus of the upper computer (6) through a circuit interface, and the FPGA chip (3) of the test board part (2) is connected with the functional unit (7) of the chip test device through the circuit interface; the synchronous signal output end of the central control board part (1) and the synchronous signal receiving end of the test board part (2), the synchronous signal output end of the test board part (2) and the synchronous signal receiving end of the central control board part (1) are connected with each other through a high-speed communication cable (4); the FPGA chip at the transmitting end decomposes the synchronous trigger signal into first class data and second class data, encodes the first class data into third class data, encodes the second class data into fourth class data, and then transmits the fourth class data; the first type data and the second type data are opposite to each other, the third type data and the fourth type data are formed by combining the first type data and the second type data at intervals, the first type data and the second type data are opposite to each other, the synchronous trigger signals of the sending end and the receiving end are different by a fixed clock period, and the different clock period is equal to the length difference value between the third type data and the first type data or between the fourth type data and the second type data.
2. The high-speed synchronous trigger bus circuit as set forth in claim 1, wherein: the central control board part (1) and the test board part (2) do not share the ground, so that low-frequency disturbance among the boards is effectively isolated.
3. The high-speed synchronous trigger bus circuit as set forth in claim 1, wherein: the synchronous signal output end and the synchronous signal receiving end of the FPGA chip (3) are LVDS signal ports.
4. The high-speed synchronous trigger bus circuit as set forth in claim 1, wherein: the high-speed communication cable (4) is a differential coaxial cable.
5. The high-speed synchronous trigger bus circuit as set forth in claim 1, wherein: and a capacitor (5) is connected in front of the synchronous signal receiving ends of the two ports of the FPGA chip (3) respectively for direct current isolation.
6. The high-speed synchronous trigger bus circuit as set forth in claim 5 wherein: the capacity of the capacitor (5) is 10nF.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010668804.4A CN111856246B (en) | 2020-07-13 | 2020-07-13 | High-speed synchronous trigger bus circuit and synchronous trigger method |
| TW110117199A TWI777557B (en) | 2020-07-13 | 2021-05-13 | Synchronous triggering method based on high speed synchronous triggering bus circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010668804.4A CN111856246B (en) | 2020-07-13 | 2020-07-13 | High-speed synchronous trigger bus circuit and synchronous trigger method |
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| CN111856246A CN111856246A (en) | 2020-10-30 |
| CN111856246B true CN111856246B (en) | 2024-07-09 |
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| CN115941398B (en) * | 2022-12-01 | 2024-03-05 | 电子科技大学 | A cross-chip interconnection system and LVDS parallel data software and hardware collaborative calibration method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN212379519U (en) * | 2020-07-13 | 2021-01-19 | 胜达克半导体科技(上海)有限公司 | High-speed synchronous trigger bus circuit |
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| JP3011680B2 (en) * | 1996-09-06 | 2000-02-21 | 株式会社東芝 | Variable length coding apparatus and method |
| KR20000040531A (en) * | 1998-12-18 | 2000-07-05 | 윤종용 | High-speed physical chip system for ieee 1394 serial bus interface and method transmitting and receiving data of the same |
| US8094766B2 (en) * | 2008-07-02 | 2012-01-10 | Teradyne, Inc. | Tracker circuit and method for automated test equipment systems |
| US7679391B2 (en) * | 2008-07-11 | 2010-03-16 | Advantest Corporation | Test equipment and semiconductor device |
| TWI637177B (en) * | 2016-12-23 | 2018-10-01 | 台灣福雷電子股份有限公司 | System and method for testing semiconductor elements |
| CN107480390B (en) * | 2017-08-23 | 2020-08-21 | 京东方科技集团股份有限公司 | Signal delay compensation method and device and computer equipment |
| TWI676129B (en) * | 2018-06-29 | 2019-11-01 | 致茂電子股份有限公司 | Syncronized multi-core processing device and syncronization control method thereof |
| CN111385047B (en) * | 2018-12-28 | 2023-05-05 | 中兴通讯股份有限公司 | Time synchronization method and electronic equipment |
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| CN212379519U (en) * | 2020-07-13 | 2021-01-19 | 胜达克半导体科技(上海)有限公司 | High-speed synchronous trigger bus circuit |
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| Publication number | Publication date |
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| CN111856246A (en) | 2020-10-30 |
| TWI777557B (en) | 2022-09-11 |
| TW202203024A (en) | 2022-01-16 |
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Address after: 201799 1st floor, building 1, 1130 qinghewan Road, Qingpu District, Shanghai Applicant after: Sundak Semiconductor Technology (Shanghai) Co.,Ltd. Address before: 201799 1st floor, building 1, 1130 qinghewan Road, Qingpu District, Shanghai Applicant before: Sundec semiconductor technology (Shanghai) Co.,Ltd. |
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