CN108153362A - DC voltage control circuit based on pll clock module - Google Patents

Abstract

The invention discloses a direct current voltage control circuit based on a PLL clock module, which is composed of a clock generation circuit, a PLL clock module circuit, a pulse width generation circuit and a gate circuit. The clock generation circuit multiplies the frequency of the input clock signal and outputs the basic clock signal to the PLL clock module circuit; the pulse width generation circuit outputs the coarse pulse width signal to the PLL clock module circuit under the control of the zero-delay clock; the PLL clock module circuit outputs The zero-delay clock signal of the basic clock signal is sent to the pulse width generating circuit, and the delay clock signal is generated for the delay of the basic clock signal at the same time, and the coarse adjustment pulse width signal generates a delay pulse width signal under the control of the delay clock signal; The pulse width modulated signal and the delayed pulse width signal are passed through an OR gate circuit to generate a final DC voltage control signal. The invention solves the defect that the resolution of the PWM signal duty cycle of the traditional PWM type DC voltage controller is difficult to improve, and has strong accuracy, universality and applicability.

Description

DC voltage control circuit based on PLL clock module

technical field

The invention relates to the field of electronic technology, in particular to a direct current voltage control circuit based on a PLL clock module.

Background technique

Pulse Width Modulation (PWM) DC voltage converters are widely used in portable electronic products such as cameras, video cameras, PDAs, and laptop computers. There are two architectures of PWM-type branch voltage converters, analog and digital. The product area of the analog architecture is small, low power consumption, occupying the mainstream of the market, but it is very sensitive to noise; while the digital design architecture has good scalability, high stability, and is relatively insensitive to external noise, which can just make up for the lack of analog architecture. shortcoming. From the perspective of the development requirements of the DC voltage converter, digital control technology is necessary. At present, in the design of the DC voltage of the digital architecture, it is generally difficult to improve the resolution of the duty cycle of the PWM signal.

The PPLL clock module is a firmware resource integrated in higher-level FPGA products that is specially used for clock synthesis, clock skew elimination, and clock phase adjustment. It is very convenient to use PLL to complete clock frequency multiplication, frequency division, and phase shift. Design brings convenience.

Contents of the invention

The purpose of the present invention is to provide a DC voltage control circuit based on a PLL clock module, which can increase the duty cycle resolution of the DC voltage control signal by 32 times under the condition that the basic clock signal remains unchanged.

The technical solution to realize the purpose of the present invention is: a DC voltage control circuit based on a PLL clock module, which is composed of four parts: a clock generation circuit, a PLL clock module circuit, a pulse width generation circuit and a gating circuit. The clock generation circuit generates the basic clock signal after multiplying the frequency of the input clock signal; the pulse width generation circuit realizes the coarse adjustment of the pulse width, and outputs the coarse adjustment pulse width signal; the PLL clock module circuit generates a delayed clock signal for the delay of the basic clock signal, and the coarse The pulse width modulation signal generates a delayed pulse width signal under the control of a delayed clock signal; the coarse pulse width modulation signal and the delayed pulse width signal output a final DC voltage control signal through an OR gate circuit.

The invention implements precise time delay on the basic clock signal based on the PLL clock module, which is equivalent to dividing the frequency of the basic clock signal, and improves the duty cycle resolution of the DC voltage control signal under the condition that the basic clock signal remains unchanged.

The clock generation circuit multiplies the frequency of the input clock signal by a frequency multiplier to generate a basic clock signal.

In the pulse width generation circuit, the pulse width generator generates coarse pulse width signals through several D flip-flops under the control of the zero-delay clock to realize the coarse adjustment of the pulse width.

The PLL clock module circuit is composed of 1 PLL and 1 D flip-flop. The PLL outputs the zero-delay clock signal of the basic clock signal to the pulse width generation circuit, and at the same time realizes the phase resolution of the basic clock signal is 360°/32= The precise time delay of 11.25° is equivalent to dividing the frequency of the basic clock signal by 32. Under the condition that the basic clock remains unchanged, the duty cycle resolution of the DC voltage control signal is increased by 32 times to generate a delayed clock signal and coarsely adjust the pulse width. The signal generates a delayed pulse width signal under the control of a delayed clock signal.

The OR gate circuit realizes the logical OR function by a look-up table (Look-Up-Table, LUT), and the coarse adjustment pulse width signal and the delayed pulse width signal output the final DC voltage control signal through the LUT.

Compared with the prior art, the present invention has the remarkable advantages that: the present invention solves the shortcoming that the resolution of the duty ratio of the PWM signal of the traditional PWM type DC voltage controller is difficult to improve, and the present invention realizes the basic clock signal through the PLL clock module circuit The precise time delay is equivalent to the frequency division of the basic clock signal, and the duty cycle resolution of the DC voltage control signal is improved under the condition that the basic clock signal remains unchanged. It has strong accuracy, versatility and applicability.

Description of drawings

Figure 1 is the overall structure of the DC/DC control circuit.

Figure 2 is the pulse width generation circuit.

Figure 3 is the PLL clock module circuit.

Figure 4 is an OR gate circuit.

Figure 5 is the output waveform of the pulse width generating circuit.

Figure 6 is the output waveform of the PLL clock module circuit.

Figure 7 is the output waveform of the OR gate circuit.

Detailed ways

The present invention will be described in further detail below with reference to the accompanying drawings.

The present invention provides a high-resolution DC voltage control circuit, the overall structure of which is shown in Figure 1. The control circuit is composed of four parts: a clock generation circuit, a PLL clock module circuit, a pulse width generation circuit and a gating circuit. The specific circuit diagrams of each part are shown in Figure 2 to Figure 5.

First, the input 13-bit array dc(12:0) is divided into high 8-bit dc(12:5) and low 5-bit dc(4:0).

In the pulse width generation circuit shown in Figure 2, the frequency of the input clock signal CK is 250MHz, and the pulse width generator outputs the corresponding pulse width coarse The pulse width modulation signal is sent to the DCM0 of the DCM modulation circuit and or the LUT of the gating circuit.

In the DCM modulation circuit shown in Figure 3, DCM0 outputs the zero-delay clock signal CLK0 of CK to the pulse width generator of the pulse width generation circuit, and at the same time, according to the input low 5-bit array dc (4:0) to CK Perform phase delay, the specific delay phase is delay=dc(4:0)×360°/32, to generate a delayed clock signal. The coarse adjustment pulse width signal generates a delayed pulse width signal under the control of a delayed clock signal. The relationship between the array dc(4:0) and the delay phase is shown in the table below.

LUT input and output relationship table

In the OR gate circuit shown in Figure 4, the logical OR function is implemented by the LUT. The LUT input and output relationship table is shown in Figure 7. The A2 and A3 input terminals of the control LUT are 0, the coarse adjustment pulse width signal and the delayed pulse width signal are respectively input from A0 and A1, and the LUT output is the final DC voltage control signal. It is equivalent to controlling the leading edge and the trailing edge of the DC voltage control signal respectively by the coarse adjustment pulse width signal and the delayed pulse width signal. The output waveform of the OR gate circuit is shown in FIG. 7 .

Claims (5)

1. A direct current voltage control circuit based on PLL clock module characterized in that: the control circuit consists of a clock generating circuit, a PLL clock module circuit, a pulse width generating circuit and/or a gating circuit; wherein,

the clock generation circuit multiplies the frequency of an input clock signal and outputs a basic clock signal to the direct-current voltage modulation circuit; the pulse width generating circuit outputs a coarse pulse width signal to the PLL clock module circuit under the control of a zero time delay clock; the PLL clock module circuit outputs a zero time delay clock signal of a basic clock signal to the pulse width generating circuit, generates a time delay clock signal for the time delay of the basic clock signal, and generates a time delay pulse width signal by the coarse tuning pulse width signal under the control of the time delay clock signal; the coarse pulse width signal and the delay pulse width signal output the final DC voltage control signal via an OR gate circuit.

2. The PLL clock module-based dc voltage control circuit of claim 1, wherein: the PLL clock module circuit is composed of 1 PLL and 1D trigger, the PLL outputs a zero time delay clock signal of a basic clock signal to the pulse width generating circuit, meanwhile, accurate time delay of 360 DEG/32 DEG to 11.25 DEG of phase resolution is carried out on the basic clock signal, a time delay clock signal is generated, and a coarse pulse width signal generates a time delay pulse width signal under the control of the time delay clock signal.

3. The PLL clock module-based dc voltage control circuit of claim 1, wherein: the clock generation circuit generates a basic clock signal by multiplying an input clock signal by a frequency multiplier.

4. The PLL clock module-based dc voltage control circuit of claim 1, wherein: the pulse width generating circuit generates a coarse pulse width signal by a pulse width generator under the control of a zero time delay clock signal and through a plurality of D triggers to realize the coarse adjustment of the pulse width.

5. The PLL clock module-based dc voltage control circuit of claim 1, wherein: the OR gate circuit realizes a logic OR function by a look-up table (LUT), and the coarse adjustment pulse width signal and the delay pulse width signal output a final direct current voltage control signal through the LUT.