CN106209037A - Digital pulse width modulator based on DCM modulation - Google Patents

Abstract

The invention discloses a digital pulse width modulator based on DCM modulation. The clock generation module outputs the basic clock signal to the DCM modulation module after multiplying the frequency of the input clock signal; the synchronous counting module is realized by accurately counting the zero-delay clock signal Coarse adjustment of the pulse width, outputting the initial control signal and the coarse adjustment control signal to the asynchronous signal generation module and the DCM modulation module at the beginning and end of the counting respectively; the DCM modulation module outputs the zero-delay clock signal of the basic clock signal to the synchronous counting module, At the same time, the precise time delay of the basic clock signal is realized, and the precise time delay of the coarse control signal is controlled by the delayed clock signal, and the termination control signal is output to the asynchronous signal generation module; the initial control signal and termination control signal are input into the asynchronous signal generation module And output the final DPWM signal. The invention realizes the precise phase delay of the basic clock signal based on DCM modulation, improves the modulation accuracy under the condition that the basic clock signal remains unchanged, and has strong accuracy, versatility and applicability.

Description

Digital Pulse Width Modulator Based on DCM Modulation

technical field

The invention belongs to the field of electronic technology, and in particular relates to a digital pulse width modulation circuit.

Background technique

In the system structure using digital pulse width modulation (Digital Pulse Width Modulation, DPWM), the main methods currently used are hybrid DPWM (Hybrid DPWM), and the second is DPWM realized by Dither method. The DPWM implemented by the Dither method is mainly realized by the idea of the design. This design can use a low-precision and high-frequency DPWM to achieve a high effective output accuracy, which also reduces the power consumption and area of the DPWM. However, the DPWM realized by the Dither method will generate a cycle delay when the mode is switched, which is not good for the high-speed response of the DPWM, and the design of the hybrid DPWM has no unnecessary delay.

The hybrid DPWM combines the traditional counter structure and the delay chain structure, and is usually composed of a coarse adjustment module and a fine adjustment module. Suppose the input is a string of binary array dc(N:0), the high bit is dc(N:m), and the low bit is dc(m:0). The coarse adjustment module uses the traditional counter structure, and the high bit determines the pulse duty cycle of the coarse adjustment. The fine-tuning module composed of the delay chain structure uses the low-bit fine-tuning duty cycle of the binary array to achieve higher resolution.

There are two ways to implement hybrid DPWM: digital-analog hybrid mode and all-digital mode. The difference between the two lies in the design of the delay chain. The digital-analog hybrid method adopts the analog delay chain, and the charge pump in the delay locked loop (Delay Locked Loop, DLL) controls the delay time of each delay unit through charging and discharging, so that the power consumption of the circuit is relatively large, while DLL may lose lock during the power-on process. The analog circuit control method is susceptible to external environment interference, and its robustness is not as strong as the digital control method. Therefore, the all-digital method has more advantages in overall performance.

Digital Clock Manager (Digital Clock Manager, DCM) is a firmware resource integrated in higher-level FPGA products dedicated to clock synthesis, clock skew elimination, and clock phase adjustment. DCM is used to complete clock frequency multiplication, frequency division, and phase shift. Very convenient.

The patent "a digital pulse width modulation circuit" (patent number: CN 102832914 A) proposes a digital pulse width modulation circuit, which uses a coarse adjustment module and a fine adjustment module to complete digital pulse width modulation, and the coarse adjustment module mainly Including counters and comparators, fine-tuning modules include delay chains, multiplexers, and full digital logic control modules. However, this method has the following disadvantages: the frequency of the basic clock signal of this method is only 1 MHz, and its structure is complex, the design process requirements are relatively high, and the cost is relatively high.

Contents of the invention

The purpose of the present invention is to provide a high-resolution digital pulse width modulator based on DCM modulation, which can increase the modulation accuracy by 32 times under the condition that the basic clock signal remains unchanged.

The technical solution for realizing the object of the present invention is as follows: a digital pulse width modulator based on DCM modulation is composed of a clock generation module, a synchronous counting module, a DCM modulation module and an asynchronous signal generation module. After the clock generation module doubles the frequency of the input clock signal Output the basic clock signal to the DCM modulation module; the synchronous counting module realizes the coarse adjustment of the pulse width by accurately counting the zero-delay clock signal, and outputs the initial control signal and the coarse adjustment control signal to the asynchronous signal generation module at the beginning and end of the counting respectively and the DCM modulation module; the DCM modulation module outputs the zero-delay clock signal of the basic clock signal to the synchronous counting module, and at the same time realizes the precise time delay of the basic clock signal, and realizes the coarse adjustment control signal under the control of the delayed clock signal Accurate time delay, output termination control signal asynchronous signal generation module; the initial control signal and termination control signal output the final DPWM signal through the asynchronous signal generation module. The invention realizes the accurate time delay of the basic clock signal based on DCM modulation, which is equivalent to the basic The frequency division of the clock signal improves the modulation accuracy under the condition that the basic clock signal remains unchanged.

The clock generation module includes a frequency multiplier, which generates the basic clock signal after multiplying the frequency of the input clock signal.

The synchronous counting module includes a preload counter, which completes precise synchronous counting for the zero-delay clock signal, and outputs the initial control signal and the coarse adjustment control signal to the asynchronous signal generation module and the DCM modulation module at the beginning and end of the counting respectively, realizing Coarse adjustment of pulse width.

The DCM modulation module is composed of a digital clock manager DCM and a D flip-flop. The function of the DCM is to output the zero-delay clock signal of the basic clock signal to the synchronous counting module, and at the same time realize the precise time delay of the basic clock signal. ;DCM can achieve an accurate phase delay of 360°/32=11.25° for the basic clock signal, which is equivalent to dividing the frequency of the basic clock signal by 32, and improving the modulation accuracy by 32 times under the condition that the basic clock signal remains unchanged. The D flip-flop performs phase delay on the coarse control signal under the control of the delayed clock signal output by the DCM, and outputs the termination control signal to the asynchronous signal generation module. The DCM can realize the precise phase delay of the basic clock signal, which is equivalent to the basic The frequency of the clock signal is divided by 32, and the modulation accuracy is increased by 32 times under the condition that the basic clock signal remains unchanged.

The initial control signal and termination control signal in the asynchronous signal generation module are input to the RS flip-flop and output the final digital pulse width modulation (DPWM) signal.

Compared with the traditional digital pulse width modulation (DPWM) circuit, the present invention can achieve higher modulation accuracy under the condition that the basic clock signal remains unchanged. The frequency of the basic clock signal of the present invention can reach 200MHz, and the design of the delay circuit It is simpler and easier to implement, and the cost is relatively low.

Description of drawings

Figure 1 is the overall structure of the DPWM circuit.

Figure 2 is the clock generation module.

Figure 3 is a synchronous counting module.

Figure 4 is the DCM modulation module.

Figure 5 is an asynchronous signal generation module.

Figure 6 is the output waveform of the synchronous counting module.

Figure 7 is the output waveform of the DCM modulation module.

Figure 8 is the output waveform of the asynchronous signal generation module.

detailed description

The present invention will be described in further detail below with reference to accompanying drawing.

The present invention provides a high-precision digital pulse width modulator. As shown in Figure 1, the digital pulse width modulator is composed of a clock generation module, a synchronous counting module, a DCM modulation module and an asynchronous signal generation module. The four modules are specific The circuit diagrams are shown in Figure 2 to Figure 5.

First, divide the input 13-bit array dc(12:0) into high 8-bit array N=dc(12:5) and low 5-bit array m=dc(4:0).

In the clock generation module shown in Figure 2, DCM×4 is a 4-fold frequency multiplier. The CLK signal is an input clock signal with a frequency of 50MHz. After the CLK clock signal is multiplied by DCM×4, the output frequency is 200MHz. The basic clock signal CK is sent to DCM0 of the DCM modulation module, and the zero-delay clock signal CLK0 is output from DCM0 to the synchronous counting module, that is, the period of the zero-delay clock signal is T=5ns.

In the synchronous counting module shown in Figure 3, the preload counter counts the input zero-delay clock signal CLK0, and when the counting starts (that is, count=0), the output signal of the load terminal of the counter passes through two D flip-flops to output The initial control signal is latched in the RS flip-flop of the asynchronous signal generation module. When the count is completed (ie count=N), the output signal at the carry_out terminal outputs the coarse control signal to the D flip-flop of the DCM modulation module through two D flip-flops At this point, the coarse adjustment of the pulse width is completed, and the coarse adjustment control signal shown in Figure 6 is obtained. The time interval between the coarse adjustment control signal and the initial control signal is N×T, which is an integer number of zero-delay clock signal periods for the input array of the preload counter.

In the DCM modulation module shown in Figure 4, after the basic clock signal is input to DCM0, a delayed clock signal corresponding to the lower 5 bits m of the input array will be generated. The corresponding delay phase is delay=m×360°/32, and the time delay is m×T/32, which is equivalent to dividing the frequency of the basic clock signal by 32, and the modulation accuracy is improved under the condition that the basic clock signal remains unchanged. 32 times. The coarse adjustment control signal is delayed by the D flip-flop under the control of the delayed clock signal, and then the termination control signal is output to the asynchronous signal generation module. The time delay between the termination control signal and the coarse adjustment control signal is m×T/32, which is the corresponding Fractional number of zero-latency clock signal periods in the DCM0 input array. The corresponding relationship between the low 5-bit array and the delay phase of the coarse control signal is shown in Fig. 7 . In order to ensure the synchronization, use the zero-delay clock signal CLK0 output by DCM0 as the control clock of the synchronous counting module.

In the asynchronous signal generation module shown in Figure 5, after the initial control signal is input into the RS flip-flop, the RS flip-flop will output a high level until the control signal is terminated After being input to the RS flip-flop, the RS flip-flop will output a low level, thus completing the pulse width modulation. It is equivalent to the initial control signal and the termination control signal to determine the rising edge and falling edge of the DPWM signal respectively. The output waveform of the asynchronous signal generation module is shown in Figure 8.

The digital pulse width modulator based on DCM modulation of the present invention mainly realizes the coarse adjustment of the signal by the synchronous counting module, and the coarse adjustment completes the pulse width modulation of an integer number of zero-delay clock signal cycles, which is N×T; The phase module completes the fine adjustment of the signal, and the fine adjustment realizes the pulse width modulation of a fractional number of zero-delay clock signal cycles, which is m×T/32. The final pulse width of the DPWM signal is the sum of the coarse and fine adjustment pulse widths, that is, (N+m/32)×T. Under the condition that the basic clock signal remains unchanged, the modulation accuracy of the DPWM signal is increased by 32 times.

Claims (5)

1. a digital pulse width modulator based on DCM modulation, it is characterised in that: include clock generating module, synchrometer Digital-to-analogue block, DCM modulation module and asynchronous signal generation module；Clock generating module is to output basis after input clock signal frequency multiplication Clock signal is to DCM modulation module；Synchronous counting module is by realizing the thick of pulsewidth to the accurate metering of zero time delay clock signal Adjust, counting start and at the end of export initial control signal respectively and coarse adjustment controls signal to asynchronous signal generation module and DCM Modulation module；The zero time delay clock signal of DCM modulation module output fundamental clock signal is to synchronous counting module, simultaneously to basis Clock signal realizes precise delay, and to coarse adjustment control signal precise delay, output termination under this delay clock signal controls Control signal to asynchronous signal generation module；Initial control signal and termination control signal export through asynchronous signal generation module Whole DPWM signal.

Digital pulse width modulator based on DCM modulation the most according to claim 1, it is characterised in that: DCM modulates mould Block is made up of 1 digital dock manager DCM and 1 d type flip flop, DCM according to its input array realize to input basic time The precise delay of clock signal, exports zero time delay clock signal to synchronous counting module simultaneously；D type flip flop is prolonging that DCM exports Time clock signal control under to coarse adjustment control signal precise phase time delay, output termination control signal to asynchronous signal produce mould Block；Time delay between termination control signal and coarse adjustment control signal is the little several zero time delay clocks corresponding to DCM input array Signal period.

Digital pulse width modulator based on DCM modulation the most according to claim 1, it is characterised in that: clock generates Module includes 1 doubler, exports fundamental clock signal to DCM modulation module after input clock signal carries out frequency multiplication.

Digital pulse width modulator based on DCM modulation the most according to claim 1, it is characterised in that: synchronous counting Module includes 1 preloading enumerator, according to its input array, zero time delay clock signal is completed accurate synchronous counting, and counting is opened Begin and at the end of export initial control signal respectively and coarse adjustment controls signal to asynchronous signal generation module and DCM modulation module, Realize the coarse adjustment of pulsewidth；Time interval between coarse adjustment pulse width signal and initial control signal is for input corresponding to preloading enumerator Integer the zero time delay clock signal period of array.

Digital pulse width modulator based on DCM modulation the most according to claim 1, it is characterised in that: initially control Signal and termination control signal are as the input signal of rest-set flip-flop in asynchronous signal generation module and export final DPWM letter Number, the two rising edge determining DPWM signal respectively and trailing edge, the pulsewidth of DPWM signal is integer fundamental clock signal week Phase and little several fundamental clock signal cycle sums.