CN106208676A - DC/DC controller based on time delay phase modulation circuit - Google Patents

Abstract

The invention discloses a DC/DC controller based on a delay phase modulation circuit. It is composed of clock generation circuit, pulse width generation circuit, delay phase modulation circuit and or gating circuit. The clock generation circuit multiplies the frequency of the input clock signal to generate a basic clock signal, which is input to the pulse generation circuit, and at the same time delays the basic clock signal to generate a delayed clock signal, which is input to the delay phase modulation circuit. The pulse width generation circuit generates a coarse pulse width adjustment signal and inputs it to the delay phase modulation circuit and or the gating circuit. The delay phase modulation circuit realizes the delay of the rough pulse width adjustment signal to generate 8 delay pulse width signals, which are input to the OR gate circuit. Select one corresponding delay pulse width signal by the OR gate circuit, and then output the final DC/DC control signal through the OR gate with the coarse adjustment pulse width signal. The present invention realizes the precise time delay of the coarse pulse width adjustment signal through the delay phase modulation circuit, improves the duty cycle resolution of the DC/DC control signal under the condition that the basic clock signal remains unchanged, and has strong accuracy, Versatility and applicability.

Description

DC/DC Controller Based on Delay Phase Modulation Circuit

technical field

The invention belongs to the field of electronic technology, and in particular relates to a DC/DC control circuit.

Background technique

Pulse width modulation (PWM) type DC/DC converters are widely used in portable electronic products such as cameras, video cameras, PDAs, and laptop computers. There are two architectures of PWM DC/DC converters, analog and digital. The product area of the analog architecture is small, low power consumption, occupying the mainstream of the market, but it is very sensitive to noise; while the digital design architecture has good scalability, high stability, and is relatively insensitive to external noise, which can just make up for the lack of analog architecture. shortcoming. From the perspective of the development requirements of DC/DC converters, digital control technology is necessary. In the current design of the digital architecture DC/DC, there is a common disadvantage that the resolution of the duty cycle of the PWM signal is difficult to improve.

In the article "Design of high-precision digital PWM DC/DC controller based on FPGA", a scheme of realizing digital high-precision PWM DC/DC by using field programmable gate array (FPGA) is proposed, which is mainly composed of A/ D conversion module, PID control module and DPWM (digital pulse width modulation) module, and the final simulation results show that digital PWM reaches 8-bit resolution, 1MHz output frequency. However, this scheme has the following disadvantages: as the frequency of the basic clock increases, the scheme cannot meet the expected requirements, and when the resolution of the basic clock remains unchanged, the modulation accuracy cannot be improved, but the modulation accuracy is low. In addition, the design scheme is relatively complicated, the design process requirements are relatively high, and the cost is relatively expensive.

The DC/DC controller circuit based on the delay phase modulation circuit adopts the traditional DC/DC control structure, and the pulse duty ratio of the rough adjustment is determined by the high bit. The delay phase modulation circuit composed of a delay chain structure uses the low-bit fine-tuning duty cycle of the binary array, which can achieve higher precision resolution.

Contents of the invention

The purpose of the present invention is to provide a high-resolution digital pulse width modulator realized by a DC/DC controller, which improves the modulation precision by 8 times when the resolution of the basic clock remains unchanged.

The technical scheme of the present invention is as follows: a DC/DC controller based on a delay phase modulation circuit, the coarse adjustment of the signal is realized by the pulse generation circuit, and the coarse adjustment pulse width signal is output; the coarse adjustment pulse is controlled by the delay phase modulation circuit The wide signal is delayed in different phases to improve the modulation resolution; in the asynchronous signal generation circuit, the selector selects a corresponding delayed pulse width signal, and the coarse pulse width signal is output through the OR gate to output the final DC/DC control signal; The basic clock signal of the pulse width generation circuit and the delay phase modulation circuit is generated by the clock generation circuit.

The clock generation circuit consists of a frequency multiplier and two digital clock managers. The frequency multiplier multiplies the input clock signal to obtain the required basic clock signal, and the two digital clock managers perform phase delay on the basic clock signal. Get 4 delayed clock signals;

The pulse width generating circuit is composed of a pulse width generator. The pulse width generator realizes the function of counting the basic clock signal, and generates a rough pulse width signal after counting the basic clock signal;

The delay phase modulation circuit is composed of 8 D flip-flops. The function of the D flip-flop is to delay and phase-modulate the coarse pulse width signal under the control of the delayed clock signal, and generate 8 delayed pulse width signals with a phase difference of 45° between adjacent channels, which is equivalent to the basic clock signal. 8 frequency division, improve the precision of DC/DC controller;

The OR gate circuit consists of a selector and an OR gate. The lower 3 bits dc (2:0) of the input array control the selector to select the corresponding 1-way delayed pulse width signal from the 8-way delayed pulse width signal. The delay time is (dc(2:0)*T)/8. Then the rising edge of the coarse adjustment pulse width signal and the falling edge of the delayed pulse width signal are used as the rising edge and falling edge of the DC/DC control signal by the OR gate (the OR gate can be realized by a look-up table LUT (Look-Up-Table)) , so as to obtain the final DC/DC control signal, and the duration of the high level of the final DC/DC control signal is (dc(2:0)*T)/8+dc(10:3)*T, so that the The duty cycle resolution of the DC/DC control signal has been improved by a factor of 8.

Compared with the prior art, the present invention has the remarkable advantages that: the present invention realizes the precise time delay of the coarse pulse width adjustment signal through the delay phase modulation circuit, and improves the DC/DC control signal under the condition that the basic clock signal remains unchanged. Duty cycle resolution, with strong accuracy, versatility and applicability.

Description of drawings

Figure 1 is the overall structure of the DC/DC control circuit based on the delay phase modulation circuit.

Figure 2 is a clock generation circuit.

Figure 3 is the pulse width generation circuit.

Figure 4 is a delay phase modulation circuit.

Figure 5 is an OR gate circuit.

Figure 6 is a LUT unit lookup table.

Figure 7 is the output waveform of the pulse width generating circuit.

Figure 8 is the output waveform of the delay phase modulation circuit.

Figure 9 is a DC/DC control signal waveform.

detailed description

The present invention will be described in further detail below with reference to the accompanying drawings.

The present invention provides a DC/DC controller based on a delay phase modulation circuit. As shown in FIG. 1 , the modulator is composed of a clock generation circuit, a delay phase modulation circuit, a pulse width generation circuit and a gating circuit. The specific circuit diagrams of the four circuits are shown in Fig. 2 to Fig. 5 .

First divide the input 11-bit array DC (10:0) into high 8-bit DC (10:3) and low 3-bit DC (2:0).

In the clock generation circuit shown in Figure 2, DCM×4 is a frequency multiplier of 4 times, and DCM0 and DCM1 are two digital clock managers respectively, and the phase difference between DCM0 and DCM1 is 45°. The CLK signal is an input clock signal with a frequency of 50MHz. After the CLK clock signal is spread by a DCM×4 frequency multiplier, a basic clock signal CK with a frequency of 200MHz is obtained. The CK signal passes through the two basic units of DCM0 and DCM1 to obtain four delayed clock signals of CK0, CK1, CK2 and CK3, whose phases are 0°, 45°, 90° and 135° in turn. And the four delay clock signals of CK0, CK1, CK2 and CK3 are respectively sent to the D flip-flops of the delay phase modulation circuit.

In the pulse width generation circuit shown in Figure 3, the pulse width generator is controlled by the upper 8 bits dc (10:3) of the input array to generate a high-level coarse-tuning pulse width signal, that is, the coarse-tuning pulse width signal is high The duration of the level is dc(10:3)*T (assuming that the period of the basic clock signal is T), thus realizing the coarse adjustment of the pulse width. Get the rough pulse width signal shown in Figure 7.

In the delay phase modulation circuit shown in Figure 4, the coarse pulse width adjustment signal passes through four D flip-flops under the control of the delay clock signals CK0, CK1, CK2, and CK3, and then signals with a phase difference of 45° are obtained. CLR0, CLR1, CLR2, CLR3, CLR0, CLR1, CLR2, and CLR3 respectively pass through four D flip-flops to obtain signals CLR4, CLR5, CLR6, and CLR7 with a phase difference of 180°. Finally, the phase difference between CLR0, CLR1, CLR2, CLR3, CLR4, CLR5, CLR6 and CLR7 is 45°, that is, the delay phases are 0°, 45°, 90°, 135°, 180°, 225°, 270° , 315° (as shown in Figure 8), 8 channels of delayed pulse width signals are obtained, and the eighth frequency division of the basic clock signal is realized, thereby increasing the precision of the modulator by 8 times. The CLR0, CLR1, CLR2, CLR3, CLR4, CLR5, CLR6, and CLR7 signals are then routed to the OR gate circuit.

In the OR gate circuit shown in Figure 5, the LUT unit is an OR gate, and its function can be implemented in the lookup table in the FPGA. The lookup table it follows is shown in Figure 6, so it is selected to input SET, RESET signal, A2, A3 select input 0. In the selector, the low three-bit dc (2:0) selects a corresponding delay pulse width signal (ie, the RESET signal shown in Figure 8), and a coarse pulse width signal (ie, the SET signal shown in Figure 8 ) through the OR gate to finally obtain the DC/DC control signal. The duration of the final high level of the DC/DC control signal is (dc(2:0)*T)/8+dc(10:3)*T (assuming that the period of the basic clock signal is T), so that the DC/DC The duty cycle resolution of the DC control signal has been improved by a factor of 8.

Claims (6)

1. A DC/DC controller based on a delay phase modulation circuit, characterized in that: comprising a clock generation circuit, a pulse width generation circuit, a delay phase modulation circuit and or a gating circuit; wherein the clock generation circuit is sensitive to the input clock After the signal is multiplied, the basic clock signal is generated and input to the pulse width generating circuit. The basic clock signal is delayed by two digital clock managers to generate a delayed clock signal, which is input to the delay phase modulation circuit; in the pulse width generating circuit, The function of counting the basic clock signal is realized by the pulse width generator, so as to realize the coarse adjustment of the pulse width, and at the same time, the coarse adjustment pulse width signal is generated and input to the delay phase modulation circuit and or gating circuit; The pulse width signal is delayed to generate 8 delayed pulse width signals, and the 8 delayed pulse width signals are input to the OR gate circuit, and the corresponding delay pulse width signal is selected by the OR gate circuit, and then combined with the coarse The pulse width modulation signal passes through the OR gate to output the final DC/DC control signal. 2. The DC/DC controller based on the delay phase modulation circuit according to claim 1, characterized in that: the delay phase modulation circuit is composed of 8 D flip-flops, and the coarse pulse is controlled by 4 delay clock signals The wide signals are respectively phase-delayed by 0° and 180°, thereby generating 8 channels of delayed pulse width signals to achieve precise delay of the phase of coarsely adjusted pulse width signals. 3. The DC/DC controller based on the delay phase modulation circuit according to claim 1, characterized in that: the coarse adjustment pulse width signal and the delay clock signal obtain 8 delay pulses after passing through the delay phase modulation circuit Wide signal, wherein the phase difference between adjacent delayed pulse width signals is 45°, that is, the phases of delayed pulse width signals are 0°, 45°, 90°, 135°, 180°, 225°, 270°, 315°. 4. The DC/DC controller based on the delay phase modulation circuit according to claim 1, characterized in that: the pulse width generating circuit is composed of a pulse width generator, and the upper 8 bits dc (10:3) of the input array Control the pulse width generator to generate a high-level coarse adjustment pulse width signal, that is, the duration of the high level of the coarse adjustment pulse width signal is dc(10:3)*T, assuming that the period of the basic clock signal is T, so as to achieve coarse Adjust the pulse width. 5. The DC/DC controller based on the delay phase modulation circuit according to claim 1, characterized in that: the OR gate circuit is composed of a selector and an OR gate, and the lower 3 bits dc (2:0) of the input array The control selector selects a corresponding delay pulse width signal, and the delay time of the delay pulse width signal relative to the coarse adjustment pulse width signal is (dc(2:0)*T)/8; The rising edge of the modulated pulse width signal and the falling edge of the delayed pulse width signal are respectively used as the rising edge and falling edge of the DC/DC control signal, and the OR gate is implemented by a look-up table LUT (Look-Up-Table) to obtain the final DC /DC control signal. 6. The DC/DC controller based on the delay phase modulation circuit according to claim 1, characterized in that: the clock generation circuit is composed of a frequency multiplier and two digital clock managers, and the frequency multiplier realizes the input clock signal frequency multiplication to generate the required basic clock signal; two digital clock managers complete the delay of the basic clock signal to generate 4 delayed clock signals, and the phase difference of the adjacent two delayed clock signals is 45°, Realize the precise delay of the basic clock signal.