CN108109917B - Isolation structure of field effect transistor and manufacturing method thereof - Google Patents

Abstract

The invention provides an isolation structure of a field effect transistor and a manufacturing method thereof, including: a semiconductor substrate, a dielectric layer, a metal layer, an insulating layer, a contact window and a contact electrode. The semiconductor substrate has a field effect transistor region and an annular trench surrounding the field effect transistor region. The dielectric layer is formed on the sidewalls and bottom of the annular trench. The metal layer is filled in the annular groove, and the upper part of the metal layer is removed to form the annular groove. The insulating layer fills the annular groove to bury the metal layer. The contact window exposes the metal layer in the annular trench. The contact electrode fills the contact window and contacts the metal layer. The present invention adopts a new isolation structure, which can prevent leakage between each transistor without the traditional shallow trench isolation structure, and can effectively improve the anti-leakage performance. Compared with the traditional shallow trench isolation structure, the present invention occupies a greatly reduced area and can effectively increase the integration density of field effect transistors.

Description

Isolation structure of field effect transistor and manufacturing method thereof

Technical field

The invention belongs to the field of semiconductor design and manufacturing, and in particular relates to an isolation structure of a field effect transistor and a manufacturing method thereof.

Background technique

Currently, semiconductor integrated circuits typically include active regions and isolation regions between the active regions, and these isolation regions are formed before active devices are manufactured. As the semiconductor process enters the deep sub-micron era, the active area isolation layer of semiconductor devices has mostly been produced using the shallow trench isolation process (Shallow Trench Isolation, STI).

The process steps for manufacturing a shallow trench isolation structure (STI) in the prior art generally include:

1) Form a hard mask and photoresist on the semiconductor substrate in sequence;

2) Use high selectivity etching to transfer the mask pattern to the hard mask pattern, and then transfer it to the semiconductor substrate to form trenches on the semiconductor substrate;

3) Form a SiO ₂ oxide layer on the sidewalls and bottom of the trench;

4) Form a SiN lining layer on the oxide layer;

5) Fill the trench with dielectric material to form a shallow trench isolation structure to prevent leakage between field effect transistors.

However, the manufacturing process of the existing shallow trench isolation structure (STI) is relatively complex, and the isolation effect is not ideal. There will still be a certain amount of leakage between field effect transistors with shallow trench isolation structures, and in order to ensure isolation As a result, usually the area occupied by the shallow trench isolation structure (STI) is too large, which will seriously reduce the integration density of field effect transistors.

Based on the above, it is necessary for the present invention to provide a new isolation structure and a manufacturing method thereof that can effectively improve the anti-leakage performance and increase the integration density of field effect transistors.

Contents of the invention

In view of the above shortcomings of the prior art, the purpose of the present invention is to provide an isolation structure of a field effect transistor and a manufacturing method thereof, which are used to solve the complex manufacturing process of the shallow trench isolation structure (STI) used in the prior art. Problems with poor anti-leakage performance and excessive area occupied.

In order to achieve the above objects and other related objects, the present invention provides a method for manufacturing an isolation structure of a field effect transistor. The manufacturing method includes: 1) providing a semiconductor substrate and defining a field effect transistor region in the semiconductor substrate. , and form an annular trench surrounding the field effect transistor area in the semiconductor substrate; 2) form a dielectric layer on the sidewalls and bottom of the annular trench; 3) fill the annular trench with a metal layer; 4) remove the upper part of the metal layer to form an annular groove; 5) fill the annular groove with an insulating layer to bury the metal layer; and 6) remove part of the insulating layer to form a contact Window, the contact window exposes the metal layer in the annular trench, and a contact electrode is filled in the contact window to form a control end of the isolation structure of the field effect transistor.

Preferably, step 1) includes: 1-1) providing the semiconductor substrate, defining a field effect transistor region in the semiconductor substrate, and forming a patterned light covering the field effect transistor region on the surface of the semiconductor substrate. Resistor; 1-2) Form an annular sacrificial mask layer on the sidewall of the patterned photoresist, and define the width of the annular trench based on the width of the sacrificial mask layer; 1-3) Remove the patterned light resist to expose the semiconductor substrate and retain the sacrificial mask layer; 1-4) form a hard mask layer on the surface of the semiconductor substrate; 1-5) remove the sacrificial mask layer, and retaining the hard mask layer to form a hard mask layer having an annular window, the annular window exposing the semiconductor substrate; and 1-6) etching the hard mask layer based on the annular window semiconductor substrate to form the annular trench.

Further, steps 1-4) include: first forming a hard mask layer on the semiconductor substrate and the sacrificial mask layer by deposition, and the hard mask layer completely covers the sacrificial mask layer, A grinding process is then used to remove part of the hard mask layer, so that the top surface of the sacrificial mask layer is exposed flush with the top surface of the hard mask layer.

Further, in steps 1-5), the removal rate of the hard mask layer is less than half of the removal rate of the sacrificial mask layer to ensure that the hard mask layer is on the semiconductor substrate retained thickness.

Preferably, step 2) oxidizes the sidewalls and bottom of the annular trench through a low-pressure annealing process (ISSG) to form the dielectric layer, and the dielectric layer includes a silicon dioxide layer (SiO ₂ ).

Preferably, step 3) filling the annular trench with a metal layer includes: 3-1) forming a titanium nitride layer (TiN) on the bottom and side walls of the annular trench; and 3-2) forming a titanium nitride layer (TiN) on the bottom and side walls of the annular trench; The annular trench is filled with a tungsten layer (W).

Preferably, the field effect transistor formed after step 6) is located in the peripheral area of the semiconductor substrate, and the array area of the semiconductor substrate is provided with multiple word line structures. Steps 1) to 3) are included in the word line structure. The formation process of line structure.

Preferably, in step 6), the method of filling the contact electrode in the contact window includes one of the group consisting of atomic layer deposition (ALD) and plasma enhanced chemical vapor deposition (PECVD).

Preferably, the resistivity of the contact electrode is between 2×10 ^-8 ohm meters (Ωm) and 1×10 ² ohm meters (Ωm), and its material includes tungsten (W), titanium (Ti), nickel A composite film composed of one or more of the group consisting of (Ni), aluminum (Al), platinum (Pt), N-type polysilicon, P-type polysilicon, metal nitride and metal silicide.

Preferably, the method further includes step 7) of fabricating a field effect transistor in the field effect transistor region. The field effect transistor includes a gate structure formed on the semiconductor substrate and an active layer formed in the semiconductor substrate. district.

Further, the annular trench has an outline corresponding to the area surrounded by the gate structure and the active area of the field effect transistor.

Preferably, the annular groove includes an annular groove having a closed shape.

Preferably, the depth of the annular groove is between 50nm (nanometer) and 200nm (nanometer).

Preferably, the width of the annular groove is between 10nm (nanometer) and 50nm (nanometer).

The invention also provides an isolation structure of a field effect transistor, including: a semiconductor substrate having a field effect transistor region and an annular trench surrounding the field effect transistor region; a dielectric layer formed in the annular The side walls and bottom of the trench; a metal layer, filled in the annular trench, and the upper part of the metal layer is removed to form an annular groove; an insulating layer, filled in the annular groove to bury the a metal layer; a part of the insulating layer is removed to form a contact window, the contact window exposes the metal layer in the annular trench; and a contact electrode is filled in the contact window and in contact with the metal layer, to form the control terminal of the isolation structure of the field effect transistor.

Preferably, the dielectric layer includes a silicon dioxide layer (SiO ₂ ).

Preferably, the metal layer includes a titanium nitride layer (TiN) formed on the bottom and sidewalls of the annular trench and a tungsten layer (W) filled in the annular trench.

Preferably, the resistivity of the contact electrode is between 2×10 ^-8 ohm meters (Ωm) and 1×10 ² ohm meters (Ωm), and its material includes tungsten (W), titanium (Ti), nickel A composite film composed of one or more of the group consisting of (Ni), aluminum (Al), platinum (Pt), N-type polysilicon, P-type polysilicon, metal nitride and metal silicide.

Preferably, the field effect transistor region has a field effect transistor including a gate structure formed on the semiconductor substrate and an active region formed in the semiconductor substrate.

Further, the annular trench has an outline corresponding to the area surrounded by the gate structure and the active area of the field effect transistor.

Preferably, the annular groove includes an annular groove having a closed shape.

Preferably, the depth of the annular groove is between 50nm (nanometer) and 200nm (nanometer).

Preferably, the width of the annular groove is between 10nm (nanometer) and 50nm (nanometer).

As mentioned above, the isolation structure of the field effect transistor and its manufacturing method of the present invention have the following beneficial effects:

The present invention uses a new isolation structure to isolate field effect transistors. It can prevent leakage between each field effect transistor without the traditional shallow trench isolation structure (STI), and can effectively improve the anti-leakage performance.

Compared with the traditional shallow trench isolation structure (STI), the isolation structure of the field effect transistor of the present invention occupies a greatly reduced area, and can effectively increase the integration density of the field effect transistor.

The invention has simple process and structure, good anti-leakage performance, and broad application prospects in the field of semiconductor design and manufacturing.

Description of the drawings

Figures 1a to 12b show schematic structural diagrams of each step of the method for manufacturing an isolation structure of a field effect transistor of the present invention, wherein Figure 1b is a schematic cross-sectional structure diagram at AA' in Figure 1a, and Figure 11b is a schematic diagram of the cross-sectional structure of Figure 11a Figure 11d is a schematic cross-sectional structural diagram at B-B' in Figure 11c, and Figure 12b is a schematic cross-sectional structural diagram at A-A' in Figure 12a.

Component label description

101 Semiconductor substrate

102 Field Effect Transistor Area

103 Graphic photoresist

104 sacrificial mask layer

105 hard mask layer

106 ring window

107 Annular Groove

108 dielectric layer

109 Titanium nitride layer (TiN)

110 Tungsten layer(W)

111 annular groove

112 insulation layer

113 Contact electrode

114 gate structure

115 source area

116 drain area

117 source electrode

118 drain electrode

119 gate electrode

120 contact window

Detailed ways

The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

Please refer to Figure 1a ~ Figure 12b. It should be noted that the illustrations provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner, so the illustrations only show the components related to the present invention and are not based on the number, shape and number of components during actual implementation. Dimension drawing, in actual implementation, the type, quantity and proportion of each component can be arbitrarily changed, and the component layout type may also be more complex.

As shown in Figures 1a to 12b, this embodiment provides a method for manufacturing an isolation structure of a field effect transistor. The manufacturing method includes:

As shown in Figures 1a to 6, step 1) is first performed to provide a semiconductor substrate 101, define a field effect transistor region 102 in the semiconductor substrate 101, and form a surrounding field in the semiconductor substrate 101 Annular trench 107 of effect transistor region 102 .

The semiconductor substrate 101 may include, for example, a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, a III-V group substrate, etc. In this embodiment, a silicon substrate may be used as an example.

The field effect transistor region 102 at least includes a substantial region of the field effect transistor and a necessary interval between the substantial region and the isolation structure. The necessary interval can be set according to actual needs. The substantial region of the field effect transistor includes an active Region and gate structure 114, the active region includes a source region 115, a drain region 116 and a channel region.

Specifically, step 1) includes:

As shown in Figures 1a to 1b, Figure 1b is a schematic cross-sectional structural diagram at AA' in Figure 1a. First, step 1-1) is performed to provide a semiconductor substrate 101. In the semiconductor substrate 101 A field effect transistor region 102 is defined, and a patterned photoresist 103 covering the field effect transistor region 102 is formed on the surface of the semiconductor substrate 101 .

The pattern photoresist 103 includes pattern photoresist that has passed an exposure process and a development process.

As shown in Figures 1a-1b, step 1-2) is then performed to form an annular sacrificial mask layer 104 on the sidewall of the patterned photoresist 103. The annular shape is defined based on the width of the sacrificial mask layer 104. The width of trench 107.

As an example, a method such as a chemical vapor deposition process can be used to cover the surface and sidewalls of the patterned photoresist 103 with a sacrificial mask material, and then dry etching is used to remove the sacrificial mask material from the surface of the patterned photoresist 103, leaving the An annular sacrificial mask layer 104 is located on the sidewall of the patterned photoresist 103 .

The present invention can define the width of the annular trench 107 based on the width of the sacrificial mask layer 104, without the need for further photolithography-etching process, that is, one photolithography-etching process can be omitted, which can greatly save processes. cost. Moreover, the width of the annular trench 107 defined by the annular sacrificial mask layer 104 will not be limited by the size of the photolithography-etching process, and its size can be made very small and has good controllability.

As an example, the width of the sacrificial mask layer 104 is between 10 nm (nanometer) and 50 nm (nanometer).

As shown in FIG. 2 , steps 1-3) are then performed to remove the patterned photoresist 103 to expose the semiconductor substrate 101 and retain the sacrificial mask layer 104 .

As shown in FIGS. 3 and 4 , steps 1-4) are then performed to form a hard mask layer 105 on the surface of the semiconductor substrate 101 .

Specifically, steps 1-4) include: first forming a hard mask layer 105 on the semiconductor substrate 101 and the sacrificial mask layer 104 by deposition, and the hard mask layer 105 completely covers the sacrificial mask layer 105 . Mask layer 104, and then use a grinding process to remove part of the hard mask layer 105, so that the top surface of the sacrificial mask layer 104 is exposed flush with the top surface of the hard mask layer 105 to ensure subsequent After the sacrificial mask layer 104 is selectively removed, the hard mask layer 105 can retain sufficient thickness.

As shown in Figure 5, steps 1-5) are then performed to remove the sacrificial mask layer 104 and retain the hard mask layer 105 to form a hard mask layer 105 with an annular window 106. 106 reveals the semiconductor substrate 101 .

As an example, in step 1-5), the removal rate of the hard mask layer 105 is less than half of the removal rate of the sacrificial mask layer 104 to ensure that the hard mask layer 105 is on the semiconductor The remaining thickness on the substrate 101. More preferably, the removal rate of the hard mask layer 105 is less than one-fifth of the removal rate of the sacrificial mask layer 104, which can ensure that the hard mask layer 105 retains more thickness to facilitate subsequent annular formation. Etching of trench 107.

As an example, the hard mask layer 105 may include a silicon dioxide layer.

As shown in FIG. 6 , steps 1-6) are finally performed to etch the semiconductor substrate 101 based on the hard mask layer 105 with the annular window 106 to form the annular trench 107 .

As an example, a plasma dry etching method is used to etch the semiconductor substrate 101 to form the annular trench 107 . The depth Z1 of the annular groove 107 is between 50nm (nanometer) and 200nm (nanometer).

As an example, the width Z2 of the annular trench 107 is between 10 nm (nanometer) and 50 nm (nanometer). Through the method of making a reverse mask, the present invention can make the size of the annular trench 107 smaller, greatly reducing the area it occupies, thereby greatly improving the integration of field effect transistors on the semiconductor substrate 101 density.

As an example, the annular trench 107 includes an annular trench 107 with a closed shape to further ensure the anti-leakage performance of the isolation structure.

As shown in FIG. 7 , step 2) is then performed to form a dielectric layer 108 on the sidewalls and bottom of the annular trench 107 .

As an example, step 2) oxidizes the sidewalls and bottom of the annular trench 107 through a low-pressure annealing process (ISSG) to form the dielectric layer 108. The dielectric layer 108 includes a silicon dioxide layer (SiO ₂ ). Using a low pressure annealing process (ISSG), the density of the dielectric layer 108 can be increased to improve its dielectric properties.

As shown in FIG. 8 , step 3) is then performed to fill the annular trench 107 with a metal layer.

Specifically, step 3) filling the annular trench 107 with a metal layer includes:

3-1) Form a titanium nitride layer (TiN) 109 on the bottom and side walls of the annular trench 107.

3-2) Fill the annular trench 107 with the tungsten layer (W) 110. The titanium nitride layer (TiN) 109 can greatly improve the bonding between the tungsten layer (W) 110 and the annular trench 107. strength and improve its mechanical properties.

3-3) Planarize the tungsten layer (W) 110 until the tungsten layer (W) 110 is flush with the surface of the semiconductor substrate 101 .

As shown in FIG. 9 , step 4) is then performed to remove the upper part of the metal layer to form an annular groove 111 .

Plasma dry etching is used to remove the upper portion of the metal layer to form an annular groove 111 , and the annular groove 111 has the same profile as the annular trench 107 .

As shown in FIG. 10 , step 5) is then performed to fill the annular groove 111 with an insulating layer 112 to bury the metal layer.

As an example, an atomic layer deposition process or a plasma enhanced chemical vapor deposition process is used to fill the annular groove 111 with an insulating layer 112 , where the insulating layer 112 includes a silicon nitride layer (SiN).

As shown in Figures 11a to 11d, Figure 11b is a schematic cross-sectional structural view at B-B' in Figure 11a, and Figure 11d is a schematic cross-sectional structural view at B-B' in Figure 11c. Then proceed to step 6) to remove Part of the insulating layer 112 is used to form a contact window 120, which exposes the metal layer in the annular trench 107, as shown in FIGS. 11a-11b, and is filled with contact electrodes in the contact window. 113, to form the control end of the isolation structure of the field effect transistor, as shown in Figures 11c to 11d.

As an example, the method of filling the contact electrode 113 in the contact window includes one of the group consisting of atomic layer deposition (ALD) and plasma enhanced chemical vapor deposition (PECVD). The resistivity of the contact electrode 113 is between 2×10 ^-8 ohm meters (Ωm) and 1×10 ² ohm meters (Ωm), and its material includes tungsten (W), titanium (Ti), nickel (Ni) ), aluminum (Al), platinum (Pt), N-type polysilicon, P-type polysilicon, metal nitride and metal silicide are composed of one or more composite films in the group. The metal nitride includes titanium nitride (TiN), and the metal silicide includes one of the group consisting of titanium silicide (TiSi), nickel silicide (NiSi), and titanium silicon nitride (TiSiN). For example, the contact electrode 113 may include a titanium nitride layer (TiN) located at the bottom and sidewalls of the contact window and a tungsten layer (W) filled in the contact window.

The contact window and contact electrode 113 are preferably disposed at any corner of the annular trench 107 to increase the contact area between the contact electrode 113 and the metal layer.

As shown in Figures 12a and 12b, Figure 12b is a schematic cross-sectional structural diagram at AA' in Figure 12a. Finally, step 7) is performed to fabricate a field effect transistor in the field effect transistor region 102. The field effect transistor is The transistor includes a gate structure 114 formed on the semiconductor substrate 101 and an active region formed in the semiconductor substrate 101. The active region includes a source region 115, a drain region 116 and a channel region. In addition, the step of forming a source electrode 117, a drain electrode 118 and a gate electrode 119 on the source region 115, the drain region 116 and the gate structure 114 is also included.

As an example, the annular trench 107 has an outline corresponding to the area enclosed by the gate structure 114 and the active area of the field effect transistor to further save the area occupied by the isolation structure, thereby further improving the field effect. Transistor integration density.

The present invention only needs to apply an appropriate voltage to the contact electrode 113 to create an energy barrier between the adjacent active area regions, thereby preventing leakage between field effect transistors.

It should be noted that the semiconductor substrate 101 includes a peripheral area and an array area. The field effect transistor formed after step 6) is located in the peripheral area of the semiconductor substrate 101. The array area of the semiconductor substrate 101 is provided with a plurality of A word line structure, the above steps 1) to 3) are included in the formation process of the word line structure.

As shown in Figures 11b, 12a and 12b, Figure 11b shows a schematic cross-sectional structure diagram at B-B' in Figure 12a, and Figure 12b shows a schematic cross-sectional structure diagram at A-A' in Figure 12a. This embodiment also provides an isolation structure of a field effect transistor, including: a semiconductor substrate 101, an annular trench 107, a dielectric layer 108, a metal layer, an insulating layer 112, a contact window and a contact electrode 113.

The semiconductor substrate 101 may include, for example, a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, a III-V group substrate, etc. In this embodiment, a silicon substrate may be used as an example.

The semiconductor substrate 101 has a field effect transistor region 102 therein. The field effect transistor region 102 at least includes a substantial region of the field effect transistor and a necessary interval between the substantial region and the isolation structure. The necessary interval can be set according to actual requirements. The field effect transistor region 102 has a field effect transistor including a gate structure 114 formed on the semiconductor substrate 101 and an active region formed in the semiconductor substrate 101. The region includes a source region 115, a drain region 116 and a channel region. In addition, the field effect transistor further includes a source electrode 117, a drain electrode 118 and a gate electrode 119 respectively located on the source region 115, the drain region 116 and the gate structure 114.

It should be noted that the semiconductor substrate includes a peripheral area and an array area, the field effect transistor is located in the peripheral area of the semiconductor substrate, and the array area of the semiconductor substrate is provided with a plurality of word line structures.

The annular trench 107 surrounds the field effect transistor area 102, and the annular trench 107 has an outline corresponding to the area enclosed by the gate structure 114 and the active area of the field effect transistor, as shown in Figure 12a. The surface profile of the annular trench 107 is the formation area of the insulating layer 112, corresponding to the area surrounded by the gate structure 114 and the active area including the source region 115 and the drain region 116, to further save the The area occupied by the isolation structure further increases the integration density of field effect transistors.

The depth Z1 of the annular groove 107 is between 50nm (nanometer) and 200nm (nanometer). The width Z2 of the annular trench 107 is between 10 nm (nanometer) and 50 nm (nanometer). Compared with the traditional shallow trench isolation structure (STI), the size of the annular trench 107 of the present invention is smaller, which can greatly reduce the area it occupies, thereby greatly improving the efficiency on the semiconductor substrate 101 The integration density of field effect transistors.

As an example, the annular trench 107 includes an annular trench 107 with a closed shape, which can further ensure the anti-leakage performance of the isolation structure.

The dielectric layer 108 is formed on the sidewall and bottom of the annular trench 107, and the dielectric layer 108 includes a silicon dioxide layer (SiO ₂ ).

The metal layer is filled in the annular groove 107, and an upper portion of the metal layer is removed to form an annular groove 111. The annular groove 111 has the same profile as the annular groove 107.

The metal layer includes a titanium nitride layer (TiN) 109 formed on the bottom and side walls of the annular trench 107 and a tungsten layer (W) 110 filled in the annular trench 107. The titanium nitride layer The layer (TiN) 109 can greatly improve the bonding strength between the tungsten layer (W) 110 and the annular groove 107 and improve its mechanical properties.

The insulating layer 112 is filled in the annular groove 111 to bury the metal layer. The insulating layer 112 includes a silicon nitride layer (SiN).

A portion of the insulating layer 112 is removed to form a contact window 120 , which exposes the metal layer in the annular trench 107 . The contact window and contact electrode 113 are preferably disposed at any corner of the annular trench 107 to increase the contact area between the contact electrode 113 and the metal layer.

The contact electrode 113 is filled in the contact window and contacts the metal layer to form a control end of the isolation structure of the field effect transistor. The contact window and contact electrode 113 are preferably disposed at any corner of the annular trench 107 to increase the contact area between the contact electrode 113 and the metal layer.

The resistivity of the contact electrode 113 is between 2×10 ^-8 ohm meters (Ωm) and 1×10 ² ohm meters (Ωm), and its material includes tungsten (W), titanium (Ti), nickel (Ni) ), aluminum (Al), platinum (Pt), N-type polysilicon, P-type polysilicon, metal nitride and metal silicide are composed of one or more composite films in the group. The metal nitride includes titanium nitride (TiN), and the metal silicide includes one of the group consisting of titanium silicide (TiSi), nickel silicide (NiSi), and titanium silicon nitride (TiSiN). For example, the contact electrode 113 may include a titanium nitride layer (TiN) located at the bottom and sidewalls of the contact window and a tungsten layer (W) filled in the contact window.

The present invention only needs to apply an appropriate voltage to the contact electrode 113 to create an energy barrier between the adjacent active area regions, thereby preventing leakage between field effect transistors.

As mentioned above, the isolation structure of the field effect transistor and its manufacturing method of the present invention have the following beneficial effects:

The present invention uses a new isolation structure to isolate field effect transistors. It can prevent leakage between each field effect transistor without the traditional shallow trench isolation structure (STI), and can effectively improve the anti-leakage performance.

Compared with the traditional shallow trench isolation structure (STI), the isolation structure of the field effect transistor of the present invention occupies a greatly reduced area, and can effectively increase the integration density of the field effect transistor.

The invention has simple process and structure, good anti-leakage performance, and broad application prospects in the field of semiconductor design and manufacturing.

Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

The above embodiments only illustrate the principles and effects of the present invention, but are not intended to limit the present invention. Anyone familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of the present invention.

Claims (20)

1. A method for fabricating an isolation structure of a field effect transistor, the method comprising:

1) Providing a semiconductor substrate, defining a field effect transistor region in the semiconductor substrate, and forming an annular groove surrounding the field effect transistor region in the semiconductor substrate;

2) Forming a dielectric layer on the side wall and the bottom of the annular groove;

3) Filling a metal layer in the annular groove;

4) Removing the upper layer part of the metal layer to form an annular groove;

5) Filling an insulating layer in the annular groove to bury the metal layer; and

6) And removing part of the insulating layer to form a contact window, exposing the metal layer in the annular groove, and filling a contact electrode in the contact window to form a control end of an isolation structure of the field effect transistor.

2. The method for manufacturing the isolation structure of the field effect transistor according to claim 1, wherein: step 1) comprises:

1-1) providing the semiconductor substrate, and forming a pattern photoresist covering the field effect transistor region on the surface of the semiconductor substrate;

1-2) forming a ring-shaped sacrificial mask layer on the side wall of the pattern photoresist, and defining the width of the ring-shaped groove based on the width of the sacrificial mask layer;

1-3) removing the patterned photoresist to expose the semiconductor substrate and leave the sacrificial mask layer;

1-4) forming a hard mask layer on the surface of the semiconductor substrate;

1-5) removing the sacrificial mask layer and reserving the hard mask layer to form a hard mask layer with a ring-shaped window, wherein the ring-shaped window exposes the semiconductor substrate; and

1-6) etching the semiconductor substrate based on the hard mask layer with the annular window to form the annular groove.

3. The method for manufacturing the isolation structure of the field effect transistor according to claim 2, wherein: the steps 1-4) comprise: and removing part of the hard mask layer by adopting a grinding process, so that the top surface of the sacrificial mask layer is exposed and flush with the top surface of the hard mask layer.

4. The method for manufacturing the isolation structure of the field effect transistor according to claim 2, wherein: in step 1-5), the removal rate of the hard mask layer is less than one half of the removal rate of the sacrificial mask layer to ensure a remaining thickness of the hard mask layer on the semiconductor substrate.

5. The method for manufacturing the isolation structure of the field effect transistor according to claim 1, wherein: step 2) oxidizing the sidewall and bottom of the annular trench by a low-pressure annealing process (ISSG) to form the dielectric layer comprising a silicon dioxide layer (SiO ₂ ）。

6. The method for manufacturing the isolation structure of the field effect transistor according to claim 1, wherein: step 3) filling a metal layer in the annular groove comprises the following steps:

3-1) forming a titanium nitride layer (TiN) on the bottom and the side wall of the annular groove; and

3-2) filling a tungsten layer (W) in the annular groove.

7. The method for manufacturing the isolation structure of the field effect transistor according to claim 1, wherein: the field effect transistor formed after the step 6) is located in the peripheral area of the semiconductor substrate, the array area of the semiconductor substrate is provided with a plurality of word line structures, and the step 1) to the step 3) comprise the forming process of the word line structures.

8. The method for manufacturing the isolation structure of the field effect transistor according to claim 1, wherein: in step 6), the method for filling the contact electrode in the contact window comprises one of Atomic Layer Deposition (ALD) and Plasma Enhanced Chemical Vapor Deposition (PECVD).

9. The method for manufacturing the isolation structure of the field effect transistor according to claim 1, wherein: the resistivity of the contact electrode is 2×10 ^-8 Ohm-meters (OMEGA.m) to 1X 10 ² The ohmic meter (OMEGA m) is made of a composite film consisting of one or more of tungsten (W), titanium (Ti), nickel (Ni), aluminum (Al), platinum (Pt), N-type polysilicon, P-type polysilicon, metal nitride and metal silicide.

10. The method for manufacturing the isolation structure of the field effect transistor according to claim 1, wherein: and 7) manufacturing a field effect transistor in the field effect transistor region, wherein the field effect transistor comprises a gate structure formed on the semiconductor substrate and an active region formed in the semiconductor substrate.

11. The method for manufacturing the isolation structure of the field effect transistor according to claim 10, wherein: the annular groove is provided with a contour corresponding to a region surrounded by the gate structure and the active region of the field effect transistor.

12. The method for manufacturing the isolation structure of the field effect transistor according to claim 1, wherein: the annular groove includes an annular groove having a closed configuration.

13. The method for manufacturing the isolation structure of the field effect transistor according to any one of claims 1 to 12, wherein: the depth of the annular groove is between 50 and nm nanometers and 200 nanometers, and the width of the annular groove is between 10 and nm nanometers and 50 and nm nanometers.

14. An isolation structure of a field effect transistor, comprising:

the semiconductor substrate comprises a peripheral area and an array area, the field effect transistor is positioned in the peripheral area of the semiconductor substrate, the array area of the semiconductor substrate is provided with a plurality of word line structures, and the semiconductor substrate is provided with a field effect transistor area and an annular groove surrounding the field effect transistor area;

the dielectric layer is formed on the side wall and the bottom of the annular groove;

a metal layer filled in the annular groove, and the upper layer part of the metal layer is removed to form an annular groove;

an insulating layer filled in the annular groove to bury the metal layer; removing part of the insulating layer to form a contact window, wherein the contact window exposes the metal layer in the annular groove; and

and the contact electrode is filled in the contact window and is contacted with the metal layer to form a control end of the isolation structure of the field effect transistor.

15. The isolation structure of a field effect transistor of claim 14, wherein: the metal layer comprises a titanium nitride layer (TiN) formed at the bottom and the side wall of the annular groove and a tungsten layer (W) filled in the annular groove.

16. The isolation structure of a field effect transistor of claim 14, wherein: the resistivity of the contact electrode is 2×10 ^-8 Ohm-meters (OMEGA.m) to 1X 10 ² The ohmic meter (OMEGA m) is made of a composite film consisting of one or more of tungsten (W), titanium (Ti), nickel (Ni), aluminum (Al), platinum (Pt), N-type polysilicon, P-type polysilicon, metal nitride and metal silicide.

17. The isolation structure of a field effect transistor of claim 14, wherein: the field effect transistor region has a field effect transistor including a gate structure formed on the semiconductor substrate and an active region formed in the semiconductor substrate.

18. The isolation structure of a field effect transistor of claim 17, wherein: the annular groove is provided with a contour corresponding to a region surrounded by the gate structure and the active region of the field effect transistor.

19. The isolation structure of a field effect transistor of claim 14, wherein: the annular groove includes an annular groove having a closed configuration.

20. The isolation structure of a field effect transistor according to any one of claims 14 to 19, wherein: the depth of the annular groove is between 50 and nm nanometers and 200 nanometers, and the width of the annular groove is between 10 and nm nanometers and 50 and nm nanometers.