CN103972174B - SiGe body longitudinal 1T-DRAM device and manufacturing method thereof - Google Patents

Abstract

The invention provides a longitudinal nanorod 1T-DRAM device and an array based on SiGe energy band engineering, wherein a longitudinal nanorod transistor is adopted, and a lamination layer formed by epitaxy is respectively used as a channel region and a drain region, so that a large space is provided for the design of the channel region and the drain region, and a plurality of implementation schemes are provided for improving the performance of the 1T-DRAM; meanwhile, the structure of the longitudinal transistor is beneficial to the integration of a SiGe channel region, epitaxial SiGe is adopted as the channel region, a potential well of a hole is manufactured in the channel region by utilizing the difference of the valence bands of SiGe and Si, and the current difference between the read 1 state and the read 0 state of the 1T-DRAM can be effectively improved.

Description

Vertical 1T-DRAM device with SiGe bulk region and its manufacturing method

technical field

The invention relates to the field of semiconductor devices and manufacturing methods thereof, in particular to a vertical high-integration transistor structure based on SiGe energy band engineering and a manufacturing method thereof.

Background technique

With the continuous shrinking of the feature size of semiconductor integrated circuit devices, the size of the traditional 1T/1C embedded DRAM unit is shrinking, and the area of its capacitor is becoming more and more difficult as scaling down, and the manufacturing process is also becoming more and more difficult. Complicated, and the compatibility with the logic device process is getting worse. Therefore, capacitorless DRAM (Capacitorless DRAM) with good compatibility with logic devices will have a good development prospect in the field of high-performance embedded DRAM of VLSI. Among them, 1T-DRAM (One Transistor Dynamic Random Access Memory) utilizing floating body effect is the main implementation method of 1T-DRAM.

1T-DRAM is generally a SOI floating body (floating body) transistor. When charging its body region, that is, the accumulation of holes in the body region to complete writing "1", at this time, the substrate effect is caused by the accumulation of holes in the body region, resulting in the transistor the threshold voltage decreases. When the body region is discharged, that is, through the positive bias of the body drain PN junction, the holes accumulated in the body region are discharged to complete writing "0". At this time, the substrate effect disappears, the threshold voltage returns to normal, and the turn-on current increases. The read operation is to read the source-leakage current when the transistor is on. Since the threshold voltages of the "1" and "0" states are different, the source-leakage currents of the two are also different. When it is larger, it means that the read is " 1", and when it is small, it means that the read is "0".

At present, the mechanism of charging the body region is mainly divided into: using the impact ionization in the saturation region to excite the parasitic BJT effect to accumulate holes in the body region and using the GIDL effect to accumulate holes in the body region. In comparison, 1T-DRAM utilizing the impact ionization effect has become a research hotspot due to its higher speed and good reliability.

At present, the structure of IT-DRAM is generally based on SOI planar structure, and the main problem of 1T-DRAM with SOI planar structure is that the potential of the body region is limited by the hole barrier between the body region and the source and drain. Due to the limited band gap of the conventional silicon semiconductor, the change of the body potential is limited, and the change of the threshold voltage is small, which makes the readout signal current smaller. In addition, the SOI substrate is not compatible with the bulk silicon process widely used at present, and there is a problem that it is not easy to dissipate heat.

Contents of the invention

The present invention aims at the non-capacitive 1T-DRAM cell structure with good development prospects in the field of embedded DRAM in the existing VLSI technology, and proposes a highly integrated vertical nanocolumn 1T-DRAM device and array based on SiGe energy band engineering and its Manufacturing method. The invention optimizes the 1T-DRAM, utilizes the vertical nano-column transistor to realize the floating body effect, and adopts the epitaxial SiGe body region which is easy to integrate, so the signal margin can be increased while reducing the unit area and improving the integration degree.

According to one aspect of the present invention, the present invention provides a semiconductor device manufacturing method, which includes the following steps:

Step 1, forming an N+ doped layer on the substrate as the source region of the transistor;

Step 2, epitaxially forming a SiGe layer on the substrate;

Step 3, using the first mask plate to etch the SiGe layer to form a SiGe nano-column as a channel region of the transistor;

Step 4, depositing a Si cap layer;

Step 5, depositing the first interlayer dielectric layer;

Step 6, using a second layer mask to etch the first interlayer dielectric layer;

Step 7, sequentially depositing a high-K gate dielectric material layer and a metal gate material layer;

Step 8, using a CMP process to remove part of the first interlayer dielectric layer, the high-K gate dielectric material layer and the metal gate material layer until the upper surface of the Si cap layer is exposed, and the remaining The metal gate material layer is formed into a metal gate, that is, a word line;

Step 9, performing selective epitaxy on the exposed upper surface of the Si cap layer to form an Si epitaxial layer;

Step 10, performing thermal oxidation treatment on part of the Si epitaxial layer;

Step 11, depositing a second interlayer dielectric layer;

Step 12, using a CMP process to remove part of the second interlayer dielectric layer until the upper surface of the Si epitaxial layer is exposed;

Step 13, depositing the first metal wiring layer, and patterning using the third layer mask to form bit lines.

According to another aspect of the present invention, the present invention provides a semiconductor device, which includes:

The semiconductor substrate; the N+ doped layer on the semiconductor substrate is the source region of the transistor; the SiGe nanocolumn on the N+ doped layer is the channel region of the transistor; the SiGe The Si epitaxial layer on the nanocolumn is the drain region of the transistor; the high-K gate dielectric material layer and the word line surround the SiGe nanocolumn and are the annular gate of the transistor; the Si epitaxial layer on the bit line.

In the present invention, the atomic percentage content of Ge in the SiGe nanocolumn is between 20% and 30%; the impurity of the N+ doped layer is arsenic, and the doping concentration is 1*10 ²⁰ cm ^-3 ; the The word lines are connected to a row of 1T-DRAM cells, and the word lines between adjacent cells are isolated by the first interlayer dielectric layer; the bit lines are connected to a column of 1T-DRAM cells; in the formed cells, the Si The diameter of the epitaxial layer is smaller than that of the SiGe nanopillars.

Description of drawings

Fig. 1-20 The flow chart of the manufacturing method of the semiconductor device of the present invention and its structure diagram

Detailed ways

Hereinafter, the present invention is described by means of specific embodiments shown in the drawings. It should be understood, however, that these descriptions are exemplary only and are not intended to limit the scope of the present invention. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present invention.

First, the present invention provides a method for manufacturing a semiconductor device, the manufacturing process of which is shown in Figures 1-20.

Firstly, referring to FIG. 1 , it is a layout of a 1T-DRAM device structure and array in an embodiment of the present invention, including three layers. Figure 1 shows a 1T-DRAM unit inside the dotted line box. The horizontal dotted line Aa indicates the direction along which the bit line extends, and the vertical dotted line Bb indicates the direction along which the word line extends. FIGS. 5 to 19 are cross-sectional views in the direction of Aa, and FIG. In addition, Fig. 2 is the pattern of the first layer mask of the 1T-DRAM device structure and array of the embodiment of the present invention, which is the mask of the nano-column pattern; Fig. 3 is the 1T-DRAM device structure and array of the embodiment of the present invention The pattern of the second reticle is the reticle of the word line; FIG. 4 is the pattern of the third reticle of the 1T-DRAM device structure and array according to the embodiment of the present invention, which is the reticle of the bit line.

First, referring to FIG. 5 , a substrate 1 is provided. The substrate 1 in this embodiment is a semiconductor substrate, such as a single crystal silicon substrate, with P- doping type. Optionally, the substrate 1 is made of semiconductor materials such as silicon germanium and gallium nitride.

Next, referring to FIG. 6 , impurity implantation is performed on the substrate 1 to form an N+ doped layer 2 . Wherein, the doping type is arsenic, the doping concentration is 1*10 ²⁰ cm ^-3 , and the peak doping distribution is between 5nm and 30nm. Optionally, an annealing process is performed after implantation. The N+ doped layer 2 serves as the source region of the transistor, therefore, the source terminals of all 1T-DRAMs in the array shown in FIG. 1 are at an equipotential.

Next, referring to FIG. 7 , the SiGe layer 3 is epitaxially formed. Wherein, the atomic percent content of Ge in the SiGe layer 3 is between 20% and 30%. In addition, during epitaxy, in-situ doping (in-situ doping), such as boron doping, can be performed at the same time, with a concentration of 1*10 ¹⁵ cm ^-3 . The thickness of SiGe layer 3 is preferably 10 to 50 nm.

Next, referring to FIG. 8 , the SiGe layer 3 is etched to form SiGe nano-columns 31 by photolithography of the nano-column pattern using the first layer mask. The SiGe nanocolumns 31 serve as the body region of the transistor, that is, the channel region of the transistor. This step specifically includes: coating of photoresist, exposing with the first mask, and then performing anisotropic etching on the exposed SiGe layer 3 until the N+ doped layer 2 . The height of the SiGe nanocolumn 31 is equal to the thickness of the SiGe layer 3 , and its diameter is preferably 10-40 nm. At the same time, the height of the SiGe nanocolumn 31 also determines the channel length of the vertical transistor.

Next, referring to FIG. 9 , the Si cap layer 4 is deposited on the entire surface. The deposition process includes CVD with a thickness of 5 nm, and the Si cap layer 4 completely covers and surrounds the SiGe nanocolumn 31 . The Si cap layer 4 has an arsenic doping of 1*10 ¹⁵ cm ⁻³ , which can be used to improve interface properties.

Next, referring to FIG. 10 , a first interlayer dielectric layer 5 is deposited. The material of the first interlayer dielectric layer 5 may optionally be silicon dioxide, which completely covers the SiGe nanocolumns 31 and the Si cap layer 4 . After depositing the first interlayer dielectric layer 5 , a CMP process is generally required to obtain a flat surface of the first interlayer dielectric layer 5 .

Next, referring to FIG. 11 , a photoresist is coated, and a second layer mask is used for exposure to form a patterned photoresist layer 6 . Afterwards, referring to FIG. 12 , using the patterned photoresist layer 6 as a mask, the first interlayer dielectric layer 5 is anisotropically etched until the Si cap layer 4 under the first interlayer dielectric layer 5 is exposed. . After the etching is completed, the patterned photoresist layer 6 is removed.

Next, referring to FIG. 13 , a high-K gate dielectric material layer 7 and a metal gate material layer 8 are deposited in sequence. Wherein, the deposition process includes CVD, ALD and the like. The material of the high-K gate dielectric material layer 7 is a hafnium-based high-K dielectric material including at least one of _HfSiOx , HfSiON, _HfAlOx , _HfTaOx , _HfLaOx , _HfAlSiOx , and _HfLaSiOx , and the metal gate material layer 8 The material is metal, alloy or metal compound, such as TiN, TaN, W, etc. Wherein, the EOT of the high-K gate dielectric material layer 7 is 1-2 nm.

Next, referring to FIG. 14 , the CMP process is adopted, with the Si cap layer 4 as the end point, part of the first interlayer dielectric layer 5 , the high-K gate dielectric material layer 7 and the metal gate material layer 8 are removed, and the Si cap layer 4 is exposed. of the upper surface. The remaining metal gate material layer 8 is formed into metal gates, ie, word lines 9 .

Next, referring to FIG. 15 , selective epitaxy is performed on the exposed upper surface of the Si cap layer 4 to form a Si epitaxial layer 10 . The Si epitaxial layer 10 is used as the drain region of the transistor, and its height is 10 to 50 nm. During the epitaxial process, in-situ doping, such as arsenic doping, can be used to form the Si epitaxial layer 10 with a doping concentration of 1*10 ²⁰ cm ⁻³ . In this way, a bottom-up layered doping structure is formed: first 1*10 ¹⁵ cm ^-3 boron-doped SiGe layer 3, and then transitions to 1*10 ¹⁵ cm ^-3 arsenic-doped Si cap layer 4 , and finally transition to the uppermost 1*10 ²⁰ cm^ ^-3 arsenic-doped Si epitaxial layer 10 gradually. Such a structure is beneficial to form a structure in which the drain gate does not overlap and extend (drain to gate underlap), and is beneficial to improving the retention time of the 1T-DRAM.

Next, referring to FIG. 16 , the Si epitaxial layer 10 is thermally oxidized to form a silicon oxide layer 11 surrounding the Si epitaxial layer 10 . Because the thermal oxidation process can consume part of the Si epitaxial layer 10, therefore, after this step, the size of the Si epitaxial layer 10 will shrink, like this, the diameter of the Si epitaxial layer 10 is smaller than the diameter of the SiGe nano-column 31, which also avoids being a leak. The Si epitaxial layer 10 in the pole region is short-circuited with the word line 9 (ie, the metal gate).

Next, referring to FIG. 17 , the second interlayer dielectric layer 12 is formed. The second interlayer dielectric layer 12 is made of silicon oxide, therefore, it is combined with the silicon oxide layer 11 to form a whole silicon oxide layer, which is designated by reference numeral 12 .

Next, referring to FIG. 18 , a part of the second interlayer dielectric layer 12 is removed by a CMP process until the upper surface of the Si epitaxial layer 10 is exposed.

Next, as shown in FIGS. 19 and 20 , the first metal wiring layer is deposited on the entire surface, and the third layer mask is used for patterning, thereby forming the bit line 13 . The material of the bit line 13 is aluminum, for example. Before forming the bit line 13, a drain contact, such as metal silicide, is formed on the Si epitaxial layer 10, so that the bit line 13 is electrically connected to the Si epitaxial layer 10 as a drain region.

So far, according to an embodiment of the present invention, the method of the present invention has been described in detail. Next, according to another aspect of the present invention, a semiconductor device is provided.

Referring to accompanying drawings 19 and 20, the semiconductor device of the present invention includes a 1T-DRAM cell array, wherein each cell specifically includes: a semiconductor substrate 1; an N+ doped layer 3 located on the semiconductor substrate 1, which is the source of the transistor Region; the SiGe nanocolumn 31 on the N+ doped layer 3 is the channel region of the transistor; the Si epitaxial layer 10 on the SiGe nanocolumn 31 is the drain region of the transistor; the high K gate dielectric material layer 7 And the word line 9 surrounds the SiGe nanocolumn 31, which is the annular gate of the transistor; the bit line 13 is located on the Si epitaxial layer. The cell array in the present invention is uniformly distributed nanocolumns, and the word line 9 is composed of connected metal gates. Since the metal gates in the present invention form the word line 9, a row of 1T-DRAM cells can be connected. In addition, the bit line 13 in the present invention is formed by etching the first metal wiring layer, connected to the drain region of the transistor, and the bit line 13 can be connected to a column of 1T-DRAM cells.

According to the present invention, the channel region and the drain region can also be formed by epitaxy combinations of other kinds of materials, so as to achieve the purpose of improving the performance of the DRAM. In the present invention, SiGe is used as the channel region, and Si is used as the drain region, which utilizes the difference between the valence band of the SiGe material and the valence band of the Si material to form a potential barrier of holes. Similarly, designers can also use Si material as the channel region, and SiC with a wide bandgap as the epitaxial drain region.

So far, the method and device of the present invention have been described in detail. In the present invention, the floating body effect is realized by using the vertical nanocolumn transistor whose source end is connected to the bulk silicon substrate, and the fabrication of the transistor is based on the bulk silicon substrate, avoiding the use of expensive SOI substrates, reducing the array area, and achieving high Integration level; vertical nano-column transistors are adopted, and the stacked layers formed by epitaxy are channel region and drain region respectively, which provides a large space for the design of channel region and drain region, which provides a great guarantee for the improvement of 1T-DRAM performance Many implementations; at the same time, the structure of the vertical transistor is conducive to the integration of the SiGe channel region. Epitaxial SiGe is used as the channel region, and the potential well of holes is created in the channel region by using the difference between SiGe and Si valence bands, which can Effectively increase the current difference between the read 1 state and the read 0 state of 1T-DRAM.

The present invention has been described above with reference to the embodiments of the present invention. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present invention. The scope of the invention is defined by the appended claims and their equivalents. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present invention, and these substitutions and modifications should all fall within the scope of the present invention.

Claims (8)

1. A method for manufacturing a semiconductor device, used to manufacture a 1T-DRAM cell array, comprising the steps of: Step 1, forming an N+ doped layer on the semiconductor substrate as the source region of the transistor; Step 2, epitaxially forming a SiGe layer on the semiconductor substrate; Step 3, using the first mask plate to etch the SiGe layer to form a SiGe nano-column as a channel region of the transistor; Step 4, depositing a Si cap layer; Step 5, depositing the first interlayer dielectric layer; Step 6, using a second layer mask to etch the first interlayer dielectric layer; Step 7, sequentially depositing a high-K gate dielectric material layer and a metal gate material layer; Step 8, using a CMP process to remove part of the first interlayer dielectric layer, the high-K gate dielectric material layer and the metal gate material layer until the upper surface of the Si cap layer is exposed, and the remaining The metal gate material layer is formed into a metal gate, that is, a word line; Step 9, performing selective epitaxy on the exposed upper surface of the Si cap layer to form an Si epitaxial layer; Step 10, performing thermal oxidation treatment on part of the Si epitaxial layer; Step 11, depositing a second interlayer dielectric layer; Step 12, using a CMP process to remove part of the second interlayer dielectric layer until the upper surface of the Si epitaxial layer is exposed; Step 13, depositing the first metal wiring layer, and patterning using the third layer mask to form bit lines. 2. A semiconductor device manufactured by the conductor device manufacturing method according to claim 1, comprising a 1T-DRAM cell array, wherein each cell comprises: semiconductor substrate; The N+ doped layer on the semiconductor substrate is the source region of the transistor; The SiGe nanocolumn on the N+ doped layer is the channel region of the transistor; The Si epitaxial layer on the SiGe nanocolumn is the drain region of the transistor; A high-K gate dielectric material layer and a word line, surrounding the SiGe nanocolumn, are ring-shaped gates of transistors; a bit line on top of the Si epitaxial layer. 3. The device according to claim 2, characterized in that, the SiGe nanocolumns have a height of 10-50 nm and a diameter of 10-40 nm. 4. The device according to claim 2, characterized in that the content of Ge in the SiGe nanocolumns is between 20% and 30% by atomic percentage. 5 . The device according to claim 2 , wherein the impurity of the N+ doped layer is arsenic, and the doping concentration is 1*10 ²⁰ cm ⁻³ . 6. The device according to claim 2, wherein each unit further comprises a first interlayer dielectric layer, and the first interlayer dielectric layer isolates the word lines between adjacent units. 7. The device according to claim 2, wherein the word line is connected to a row of 1T-DRAM cells, and the bit line is connected to a column of 1T-DRAM cells. 8. The device according to claim 2, wherein the diameter of the Si epitaxial layer is smaller than the diameter of the SiGe nanocolumn.