CN111710713B - Fin type field effect transistor, manufacturing method thereof and electronic equipment - Google Patents

Abstract

The invention discloses a fin field effect transistor, a manufacturing method thereof and electronic equipment, and relates to the technical field of semiconductors. The fin field effect transistor includes a substrate, an isolation layer, a fin structure, and a gate stack structure. An isolation layer is formed on the substrate. The fin structure is formed on the isolation layer. The fin structure extends in a first direction. The fin structure includes a source region, a drain region, and a channel region in contact with the source region and the drain region, respectively. The area of the isolation layer covering the substrate is smaller than or equal to the area of the fin structure covering the substrate. The gate stack structure is formed at an outer periphery of the channel region. The gate stack extends in a second direction. The manufacturing method of the fin field effect transistor is used for manufacturing the fin field effect transistor provided by the technical scheme. The fin field effect transistor provided by the invention is applied to electronic equipment.

Description

Fin field effect transistor and manufacturing method thereof, electronic equipment

Technical field

The present invention relates to the field of semiconductor technology, and in particular to a fin field effect transistor, a manufacturing method thereof, and electronic equipment.

Background technique

When making fin field effect transistors, in order to suppress parasitic channels and source-drain leakage, a silicon-on-insulator (SOI) substrate is generally selected as the substrate of the fin field effect transistor. Structures such as source and drain regions in fin field effect transistors are formed on the buried oxide layer. The buried oxide layer is a non-conductive insulating layer that can solve the leakage problems of parasitic channels and source and drain.

However, due to the high cost of existing SOI substrates, the production cost of fin field effect transistors is high.

Contents of the invention

The object of the present invention is to provide a fin field effect transistor, a manufacturing method thereof, and electronic equipment, which can suppress parasitic channels and source-drain leakage by forming an isolation layer between the fin-shaped structure and the substrate without requiring high use costs. SOI substrate, thereby reducing the production cost of fin field effect transistors.

In order to achieve the above object, the present invention provides a fin field effect transistor, which includes:

substrate,

an isolation layer, the isolation layer is formed on the substrate;

A fin-shaped structure is formed on the isolation layer. The fin-shaped structure extends along the first direction. The fin-shaped structure includes a source region, a drain region and a channel region. The channel region is located between the source region and the drain region. The channel The areas are in contact with the source area and the drain area respectively, and the area of the substrate covered by the isolation layer is less than or equal to the area of the substrate covered by the fin-shaped structure;

and a gate stack structure, the gate stack structure is formed on the periphery of the channel region, and the gate stack structure extends along the second direction.

Compared with the prior art, the fin field effect transistor provided by the present invention has an isolation layer formed between the substrate and the fin structure. When the gate stack structure is loaded with an appropriate voltage, the existence of the isolation layer can cause the source and drain regions to be conductive only through the channel region and not to be conductive to the substrate located under the isolation layer, thereby solving the problem of parasitic channels. And the problem of source leakage and leakage. At the same time, since the isolation layer is a film layer that is subsequently formed on the substrate and does not constitute a part of the substrate, under the above circumstances, in the process of manufacturing fin field effect transistors, a silicon substrate with a lower cost than an SOI substrate can be used. Other substrates that meet the requirements, such as bottom or silicon germanium substrates, can not only solve the problems of parasitic channels and source-drain leakage, but also reduce the production cost of fin field effect transistors.

The invention also provides a method for manufacturing a fin field effect transistor, which method includes:

provide a substrate;

forming an isolation layer on the substrate;

A fin-shaped structure is formed on the isolation layer. The fin-shaped structure extends along the first direction. The fin-shaped structure includes a source region, a drain region and a channel region. The channel region is located between the source region and the drain region. The channel region is connected to the source region respectively. The area and the drain area are in contact, and the area of the substrate covered by the isolation layer is less than or equal to the area of the substrate covered by the fin structure;

A gate stack structure is formed on the outer periphery of the channel region, and the gate stack structure extends along the second direction.

Compared with the existing technology, the beneficial effects of the manufacturing method of the fin field effect transistor provided by the present invention are the same as those of the fin field effect transistor provided by the above technical solution, and will not be described again here.

The present invention also provides an electronic device, which includes the fin field effect transistor provided by the above technical solution.

Compared with the prior art, the beneficial effects of the electronic device provided by the present invention are the same as those of the fin field effect transistor provided by the above technical solution, and will not be described again here.

Description of drawings

The drawings described here are used to provide a further understanding of the present invention and constitute a part of the present invention. The illustrative embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the attached picture:

Figure 1 is a schematic structural diagram of a fin field effect transistor provided by an embodiment of the present invention;

Figure 2 is a schematic structural diagram after the material layer to be oxidized and the pre-semiconductor material layer are formed on the substrate in an embodiment of the present invention;

Figure 3 is a schematic structural diagram after forming a material layer to be oxidized, a pre-semiconductor material layer and a silicon material layer on a substrate in an embodiment of the present invention;

Figure 4 is a schematic structural diagram after the layer to be oxidized, the semiconductor material layer and the hard mask pattern are formed on the substrate in an embodiment of the present invention;

Figure 5 is a schematic structural diagram after forming a layer to be oxidized, a semiconductor material layer, a silicon layer and a hard mask pattern on a substrate in an embodiment of the present invention;

Figure 6 is a cross-sectional view along the B-B direction of the structure shown in Figure 4;

Figure 7 is a cross-sectional view along the B-B direction of the structure shown in Figure 5;

Figure 8 is a cross-sectional view along the A-A direction of the structure shown in Figure 4;

Figure 9 is a cross-sectional view along the A-A direction of the structure shown in Figure 5;

Figure 10 is a cross-sectional view of the structure along the B-B direction after the isolation layer is formed in the embodiment of the present invention;

Figure 11 is another structural cross-sectional view along the B-B direction after the isolation layer is formed in the embodiment of the present invention;

Figure 12 is a cross-sectional view of the structure along the A-A direction after the isolation layer is formed in the embodiment of the present invention;

Figure 13 is another structural cross-sectional view along the A-A direction after the isolation layer is formed in the embodiment of the present invention;

Figure 14 is a cross-sectional view of the structure along the B-B direction after removing the hard mask pattern and the oxidized portion of the semiconductor material layer in an embodiment of the present invention;

Figure 15 is a cross-sectional view of the structure along the B-B direction after removing the hard mask pattern, the semiconductor material layer and the oxidized portion of the silicon layer in an embodiment of the present invention;

Figure 16 is a cross-sectional view of the structure along the A-A direction after removing the hard mask pattern and the oxidized portion of the semiconductor material layer in an embodiment of the present invention;

Figure 17 is a cross-sectional view of the structure along the A-A direction after removing the hard mask pattern, the semiconductor material layer and the oxidized part of the silicon layer in an embodiment of the present invention;

Figure 18 is a cross-sectional view of the structure along the B-B direction after shallow trench isolation is formed in the embodiment of the present invention;

Figure 19 is another structural cross-sectional view along the B-B direction after shallow trench isolation is formed in the embodiment of the present invention;

Figure 20 is a cross-sectional view of the structure along the A-A direction after shallow trench isolation is formed in the embodiment of the present invention;

Figure 21 is another structural cross-sectional view along the A-A direction after shallow trench isolation is formed in the embodiment of the present invention;

Figure 22 is a structural cross-sectional view along the B-B direction after the sacrificial gate is formed in the embodiment of the present invention;

Figure 23 is another structural cross-sectional view along the B-B direction after the sacrificial gate is formed in the embodiment of the present invention;

Figure 24 is a cross-sectional view of the structure along the A-A direction after the sacrificial gate is formed in the embodiment of the present invention;

Figure 25 is another structural cross-sectional view along the A-A direction after the sacrificial gate is formed in the embodiment of the present invention;

Figure 26 is a cross-sectional view of the structure along the A-A direction in the embodiment of the present invention after removing the source region formation region and the drain region formation region;

Figure 27 is another cross-sectional view of the structure along the A-A direction after removing the source region formation region and the drain region formation region in the embodiment of the present invention;

Figure 28 is a cross-sectional view of the structure along the A-A direction after forming the source region and the drain region in the embodiment of the present invention;

Figure 29 is another structural cross-sectional view along the A-A direction after forming the source region and the drain region in the embodiment of the present invention;

Figure 30 is a cross-sectional view of the structure along the A-A direction after the first dielectric layer and the second dielectric layer are formed in the embodiment of the present invention;

Figure 31 is another structural cross-sectional view along the A-A direction after the first dielectric layer and the second dielectric layer are formed in the embodiment of the present invention;

Figure 32 is a cross-sectional view of the structure along the A-A direction after the gate stack structure is formed in the embodiment of the present invention;

Figure 33 is another structural cross-sectional view along the A-A direction after the gate stack structure is formed in the embodiment of the present invention;

Figure 34 is another structural cross-sectional view along the B-B direction after the gate stack structure is formed in the embodiment of the present invention;

FIG. 35 is a flow chart of a method for manufacturing a fin field effect transistor according to an embodiment of the present invention.

Reference signs:

1 is the substrate, 2 is the isolation layer, 3 is the fin structure, 31 is the source area, 32 is the drain area, 33 is the channel area, 4 is the gate stack structure, 41 is the gate dielectric layer, 42 is the gate electrode, 5 is the layer to be oxidized, 6 semiconductor material layers, 61 is the source region formation area, 62 is the drain region formation area, 7 is the silicon layer, 8 is the hard mask pattern, 9 is the sacrificial gate, 10 is the first spacer, 11 is For the second spacer, 12 is the first dielectric layer, 13 is the second dielectric layer, and 14 is shallow trench isolation.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood, however, that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. Furthermore, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily confusing the concepts of the present disclosure.

Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. The drawings are not drawn to scale, with certain details exaggerated and may have been omitted for purposes of clarity. The shapes of the various regions and layers shown in the figures, as well as the relative sizes and positional relationships between them are only exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art will base their judgment on actual situations. Additional regions/layers with different shapes, sizes, and relative positions can be designed as needed.

In the context of this disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present between them. element. Additionally, if one layer/element is "on" another layer/element in one orientation, then the layer/element can be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer, the present invention will be further described in detail below with reference to the drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention and are not intended to limit the present invention.

In addition, the terms “first” and “second” are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present invention, "plurality" means two or more than two, unless otherwise explicitly and specifically limited. "Several" means one or more than one, unless otherwise expressly and specifically limited.

In the description of the present invention, it should be noted that, unless otherwise clearly stated and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be an internal connection between two elements or an interaction between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

The leakage problem of parasitic channels and source-drain has always been one of the main factors affecting the performance of fin field effect transistors. In the existing technology, the following two methods are generally used to solve the leakage problem of parasitic channels and source and drain:

Specifically, one is to select an SOI substrate as the substrate of the fin field effect transistor. At this time, the source and drain regions in the fin field effect transistor are formed on the buried oxide layer of the SOI substrate. Since the buried oxide layer is a non-conductive insulating layer, it can solve the leakage problems of parasitic channels and source and drain. However, due to the high cost of existing SOI substrates, the production cost of fin field effect transistors is high.

The other method is to perform an anti-punch-through injection process on the fin after forming the fin (the fin is composed of a semiconductor material layer) to form a punch-through barrier layer at the bottom of the fin. Structures such as the source region, drain region, and channel region in the fin field effect transistor are formed on the through barrier layer. Since the through barrier layer is injected with high concentrations of impurities that are opposite to the impurity types in the source and drain regions, it can Leakage current is isolated through a reverse-biased PN junction, thereby suppressing parasitic channels and source-drain leakage. However, in the process of forming the punch-through barrier layer, punch-through prevention implantation will cause uneven impurity concentration distribution in various regions in the channel region. For example, the impurities in the punch-through barrier layer are affected by subsequent high-temperature annealing and diffuse into the channel region, resulting in degradation of carrier mobility inside the channel region and degradation of the driving performance of the fin field effect transistor.

In order to solve the above technical problems, embodiments of the present invention provide a fin field effect transistor, a manufacturing method thereof, and electronic equipment. Among them, in the fin field effect transistor provided by the embodiment of the present invention, an isolation layer is formed between the substrate and the fin structure. The existence of the isolation layer can solve the leakage problems of parasitic channels and source and drain. Moreover, the isolation layer is a film layer subsequently formed on the substrate, and there is no need to use a higher-cost SOI substrate, thereby reducing the manufacturing cost of the fin field effect transistor.

The embodiment of the present invention provides a fin field effect transistor. For details, see Figure 1, Figure 33 and Figure 34. The fin field effect transistor includes a substrate 1, an isolation layer 2, a fin structure 3 and a gate stack structure 4. . The above-mentioned substrate 1 may be a lower-cost semiconductor substrate such as a silicon substrate or a germanium-silicon substrate. In some cases, shallow trench isolations 14 for defining each active area are formed on the above-mentioned substrate 1 . The material contained in the shallow trench isolation 14 can be insulating materials such as SiN, Si ₃ N ₄ , SiO ₂ or SiCO.

As shown in Figure 1, Figure 33 and Figure 34, the above-mentioned isolation layer 2 is formed on the substrate 1. That is to say, the isolation layer 2 in the embodiment of the present invention is a film layer subsequently formed on the substrate 1 and is not a composition. part of substrate 1. At this time, lower-cost semiconductor substrates such as silicon substrates can be used in the production of fin field effect transistors. And forming the isolation layer 2 on the semiconductor substrate can also solve the leakage problem of parasitic channels and source and drain, without using an SOI substrate containing a buried oxide layer.

Whether the isolation layer 2 has a single-layer structure or a multi-layer structure, the materials contained in the isolation layer 2 , and the thickness of the isolation layer 2 can be designed according to actual application scenarios, and are not specifically limited here. For example, the material contained in the isolation layer 2 is silicon oxide or silicon germanium oxide. The layer thickness of the isolation layer 2 is 5 nm to 50 nm. Furthermore, the preferred layer thickness of the isolation layer 2 is 10 nm to 20 nm.

It should be noted that the shallow trench isolation 14 is formed on a portion of the substrate 1 where the isolation layer 2 is not correspondingly formed.

As shown in FIG. 1 , FIG. 33 and FIG. 34 , the above-mentioned fin-shaped structure 3 is formed on the isolation layer 2 . The fin-shaped structure 3 extends along the first direction, and includes a source region 31 , a drain region 32 and a channel region 33 . The channel region 33 is located between the source region 31 and the drain region 32, and is in contact with the source region 31 and the drain region 32 respectively. The area of the isolation layer 2 covering the substrate 1 is less than or equal to the area of the fin structure 3 covering the substrate 1 . It should be understood that in the process of manufacturing the above-mentioned fin field effect transistor, if after the sacrificial gate 9, the first spacer 10 and the second spacer 11 are formed, the source region formation region 61 and the source region included in the semiconductor material layer 6 are directly formed. The drain region forming region 62 (or the region corresponding to the source region forming region 61 and the drain region forming region 62 based on the semiconductor material layer 6 and the silicon layer 7) forms the source region 31 and the drain region 32 respectively, then the isolation layer 2 covers the substrate at this time The area of 1 is equal to the area of substrate 1 covered by fin structure 3. In another case, as shown in Figures 26 to 29, in the process of manufacturing the above-mentioned fin field effect transistor, if after the sacrificial gate 9, the first spacer 10 and the second spacer 11 are formed, the The source region forming region 61 and the drain region forming region 62 included in the semiconductor material layer 6 (or the regions corresponding to the source region forming region 61 and the drain region forming region 62 of the semiconductor material layer 6 and the silicon layer 7 are removed). After that, the source region 31 and the drain region 32 are respectively formed at positions corresponding to the source region formation region 61 and the drain region formation region 62 and on part of the shallow trench isolation 14 by epitaxial growth. The area of the subsequently formed source region 31 covering the substrate 1 is larger than the area of the source region forming region 61 covering the substrate 1 , and the subsequently formed drain region 32 covering the substrate 1 is larger than the area of the drain region forming region 62 covering the substrate 1 . At this time, the area of the substrate 1 covered by the isolation layer 2 is smaller than the area of the substrate 1 covered by the fin-shaped structure 3 . It can be seen from the above that no matter which method is used to form the source region 31 and the drain region 32 , the isolation layer 2 is only formed below the fin-shaped structure 3 . At the same time, the bottoms of the source region 31 and the drain region 32 are both in contact with the isolation layer 2 , or both are in contact with the isolation layer 2 and the shallow trench isolation 14 . The isolation layer 2 and the shallow trench isolation 14 are made of non-conductive insulating materials, so the existence of the isolation layer 2 can solve the problem of parasitic channels and source-drain leakage.

As for the material contained in the source region 31 and the drain region 32, it is a semiconductor material, and the semiconductor material can be Si, SiGe or Ge, etc. The materials contained in the source region 31 and the drain region 32 may be the same or different. The material contained in the channel region 33 may be Si or Si _1-x Ge _x , where 0<x≤0.6. The specific content of Ge in the channel region 33 can be selected according to actual conditions. Specifically, the higher the Ge content in the channel region 33 , the higher the carrier mobility of the channel region 33 .

It should be noted that the above-mentioned first direction can be set according to the actual situation, and is not specifically limited here.

As shown in Figure 1, Figure 33 and Figure 34, the part of the isolation layer 2 located under the source region 31 and the part of the isolation layer 2 located under the drain region 32, the tops of the two parts can be flush, or the two parts can be flush with each other. The top heights of the sections vary slightly. Specifically, the height of each part of the isolation layer 2 can be designed according to the actual application scenario, as long as it can be applied to the fin field effect transistor provided by the embodiment of the present invention. It should be pointed out that when the tops of the above two parts are flush, knot depth changes can be avoided. Moreover, the isolation layer 2 is a solid structure, and its position will not change due to the influence of high-temperature annealing and other treatments, that is, there will be no problem like impurities in the punch-through barrier layer being affected by subsequent high-temperature annealing and diffusing into the channel region 33 , making the working performance of fin field effect transistors more stable.

As shown in FIGS. 1 , 33 and 34 , the gate stack structure 4 described above is formed on the outer periphery of the channel region 33 . Furthermore, the gate stack structure 4 extends along the second direction. Specifically, the above gate stack structure 4 may include a gate dielectric layer 41 and a gate electrode 42 formed around the channel region 33 . The material contained in the gate dielectric layer 41 may be a material with a relatively high dielectric constant such as HfO ₂ , ZrO ₂ , TiO ₂ or Al ₂ O ₃ . The material contained in the gate 42 may be a conductive material such as TiN, TaN or TiSiN. Furthermore, the second direction intersects the first direction. For example: the second direction is orthogonal to the first direction.

The manufacturing process of the fin field effect transistor provided by the embodiment of the present invention will be described in detail below with reference to Figure 35:

Step S101: Provide a substrate 1.

Step S102: Form isolation layer 2 on substrate 1.

Step S103: Form the fin-shaped structure 3 on the isolation layer 2. The fin-shaped structure 3 extends along the first direction. The fin-shaped structure 3 includes a source region 31 , a drain region 32 and a channel region 33 . The channel region 33 is located between the source region 31 and the drain region 32 . Channel region 33 is in contact with source region 31 and drain region 32 respectively. The area of the isolation layer 2 covering the substrate 1 is less than or equal to the area of the fin structure 3 covering the substrate 1 .

Step S104: Form the gate stack structure 4 located on the outer periphery of the channel region 33. The gate stack structure 4 extends along the second direction.

Based on the structure and manufacturing process of the fin field effect transistor provided by the embodiment of the present invention, it can be known that an isolation layer 2 is formed between the substrate 1 and the fin structure 3 in the fin field effect transistor provided by the embodiment of the present invention. When the gate stack structure 4 is loaded with an appropriate voltage, the presence of the isolation layer 2 can cause the source region 31 and the drain region 32 to be conductive only through the channel region 33 without being conductive to the substrate 1 located under the isolation layer 2 , which can solve the problem of parasitic channel and source-drain leakage. At the same time, the isolation layer 2 is a film layer subsequently formed on the substrate 1 and does not constitute a part of the substrate 1 . Under the above circumstances, in the process of making fin field effect transistors, silicon substrates with lower costs than SOI substrates or silicon germanium substrates and other substrates that meet the requirements can be used, and the problems of parasitic channels and source and drain can also be solved. To solve the leakage problem, there is no need to use a higher-cost SOI substrate, thereby reducing the production cost of fin field effect transistors.

In an optional manner, as shown in FIG. 1 , FIG. 33 and FIG. 34 , the above-mentioned fin field effect transistor further includes a first spacer 10 and a second spacer 11 formed on the substrate 1 . The first side wall 10 and the second side wall 11 extend along the second direction. The gate stack structure 4 is formed between the first spacer 10 and the second spacer 11 .

For the above-mentioned first sidewall 10 and second sidewall 11, the material contained in the first sidewall 10 and the second sidewall 11 may be an insulating material such as SiN or _SiO2 . The width of the first side wall 10 and the second side wall 11 can be designed according to the actual application scenario, and is not specifically limited here.

In an optional manner, as shown in FIG. 1 , FIG. 33 and FIG. 34 , the above-mentioned fin field effect transistor further includes a first dielectric layer 12 and a second dielectric layer 13 . The first dielectric layer 12 covers the source region 31 . The second dielectric layer 13 covers the drain region 32 . It should be understood that during the process of manufacturing the fin field effect transistor, the existence of the first dielectric layer 12 and the second dielectric layer 13 can protect the source region 31 and the drain region 32 from being etched when the sacrificial gate 9 is etched. , cleaning and other operations.

The materials contained in the first dielectric layer 12 and the second dielectric layer 13 may be insulating materials such as SiO ₂ or SiN.

An embodiment of the present invention also provides a method for manufacturing a fin field effect transistor. As shown in Figure 35, the manufacturing method further includes:

Step S101: Provide a substrate 1. As for the selection of substrate 1, please refer to the previous article and will not be described in detail here.

Step S102: As shown in Figures 2 to 17, an isolation layer 2 is formed on the substrate 1.

Specifically, as shown in Figures 2 to 17, forming the isolation layer 2 on the substrate 1 includes:

Step S102.1: As shown in Figures 2 and 4, a layer to be oxidized 5 and a semiconductor material layer 6 located on the layer to be oxidized 5 are formed on the substrate 1. The semiconductor material layer 6 includes a source region forming region 61 , a drain region forming region 62 and a channel region 33 . The channel region 33 is located between the source region forming region 61 and the drain region forming region 62 .

For example, as shown in FIG. 2 , a material layer to be oxidized covering the substrate 1 and a pre-semiconductor material layer covering the material layer to be oxidized are sequentially formed on the substrate 1 through chemical vapor deposition or other methods. A hard mask covering the pre-semiconductor material layer is formed on the pre-semiconductor material layer, and photolithography and etching processes are used to etch the hard mask according to a preset plan to form a hard mask pattern 8 . Afterwards, based on the hard mask pattern 8, the substrate 1, the material layer to be oxidized and the pre-semiconductor material layer are etched to form the first fin. As shown in Figure 4, along the bottom-up direction, the first fin includes a second fin formed by etching part of the substrate 1, a layer to be oxidized 5 formed by etching the material layer to be oxidized, and a pre-semiconductor etched The semiconductor material layer 6 is formed by the material layer.

For the layer 5 to be oxidized, the material contained in the layer 5 to be oxidized needs to have a certain oxidation selectivity ratio with the material contained in the semiconductor material layer 6 . Specifically, the material contained in the layer 5 to be oxidized may be Si _1-y Ge _y , where 0.2≤y≤0.8. Of course, the materials contained in the layer to be oxidized 5 can also be set according to actual conditions. The layer 5 to be oxidized will subsequently form the isolation layer 2 accordingly, so the thickness of the layer 5 to be oxidized can be set with reference to the thickness of the isolation layer 2 mentioned above. As for the semiconductor material layer 6, the material contained in the semiconductor material layer 6 may be Si or Si _1-x Ge _x , where 0<x≤0.6. The thickness of the semiconductor material layer 6 determines the height of the subsequently formed channel region 33 , so the thickness of the semiconductor material layer 6 can be set according to the height of the channel region 33 . For example, the thickness of the semiconductor material layer 6 is 15 nm to 70 nm.

It should be noted that if the material contained in the semiconductor material layer 6 is Si _{1-x Ge} The Ge content in is at least 20% lower than the Ge content in the material layer to be oxidized.

In addition, as shown in Figures 3 and 5, when the material contained in the semiconductor material layer 6 is Si _{1-x Ge} After forming a hard mask on the pre-semiconductor material layer, a silicon material layer is formed on the pre-semiconductor material layer. In the above case, based on the hard mask pattern 8, the first fin obtained includes the second fin formed by etching part of the substrate 1, the layer to be oxidized 5 formed by etching the material layer to be oxidized, and the pre-semiconductor material etched. The semiconductor material layer 6 is formed by etching the silicon material layer, and the silicon layer 7 is formed by etching the silicon material layer. The existence of the silicon layer 7 can protect the channel area 33 from subsequent etching, cleaning and other processes, and avoid damage to the channel area 33 . Specifically, the thickness of the silicon layer 7 can be set according to actual conditions. For example, the thickness of the silicon layer 7 is 2 nm to 10 nm.

Step S102.2: As shown in Figures 10 to 17, the layer 5 to be oxidized is oxidized to obtain the isolation layer 2.

In one example, the gas used when oxidizing the layer 5 to be oxidized may be a mixed gas of O ₂ and N ₂ , or may be a gas containing O ₃ . In addition, the method used to oxidize the layer to be oxidized 5 can be a furnace tube oxidation treatment method, or it can also be a rapid heat treatment method.

Among them, when the furnace tube oxidation treatment method is selected to oxidize the oxide layer 5, the treatment conditions of the furnace tube oxidation treatment method are: the treatment temperature is 500°C to 850°C, and the treatment time is 10min to 60min. Specifically, the processing temperature and processing time can be set according to the actual application scenario.

When the rapid heat treatment method is selected to oxidize the oxide layer 5 to be oxidized, the treatment conditions of the rapid heat treatment method are: the treatment temperature is 600°C to 850°C, the treatment time is 30s to 60s, and the treatment cycle is 1 to 10 times. Specifically, the processing temperature, processing time and processing cycle can be set according to the actual application scenario.

It should be noted that, as shown in FIGS. 10 to 13 , when the to-be-oxidized layer 5 is oxidized, the surface of the semiconductor material layer 6 and the substrate 1 (when a silicon layer 7 is formed, the surface of the silicon layer 7 is also included) Will not be oxidized or will be partially oxidized. When the above structure is partially oxidized, it is necessary to remove the hard mask pattern 8 and simultaneously remove the semiconductor material layer 6 and the substrate 1 (or remove the semiconductor material layer 6 as shown in FIGS. 14 to 17 ) after the isolation layer 2 is formed. , substrate 1 and silicon layer 7) are oxidized parts.

It is worth noting that the isolation layer 2 is obtained by oxidizing the layer to be oxidized 5 formed on the substrate 1 . That is to say, the isolation layer 2 is a film layer subsequently formed on the substrate 1 and does not constitute a part of the substrate 1 . At this time, lower-cost semiconductor substrates such as silicon substrates can be used in the production of fin field effect transistors. Forming the isolation layer 2 on the semiconductor substrate can also solve the problem of parasitic channel and source-drain leakage without using an SOI substrate containing a buried oxide layer, thereby reducing the manufacturing cost of fin field effect transistors.

In addition, as shown in FIGS. 18 to 21 , after the above operation is completed and before the lower operation is performed, a shallow groove isolation 14 needs to be formed in the groove between the first fins. The materials contained in the shallow trench isolation 14 can be referred to the above. The top height of the shallow trench isolation 14 may be less than or equal to the top height of the isolation layer 2 . Of course, the height of the shallow trench isolation 14 can also be set according to the actual application scenario, and is not specifically limited here.

In an optional manner, as shown in Figures 22 to 25, after forming the isolation layer 2 on the substrate 1 and before forming the fin structure 3 on the isolation layer 2, the above-mentioned method for manufacturing the fin field effect transistor Also includes:

Step S102-3: As shown in Figures 22 to 25, form a sacrificial gate 9 in a region of the semiconductor material layer 6 corresponding to the channel region 33, or in a region of the isolation layer 2 and the semiconductor material layer 6 corresponding to the channel region 33. .

Specifically, when the top height of the shallow trench isolation 14 is equal to the top height of the isolation layer 2 , the gate material of the sacrificial gate 9 needs to be formed on the semiconductor material layer 6 . The above-mentioned gate material is etched to form the sacrificial gate 9 only in the region of the semiconductor material layer 6 corresponding to the channel region 33 . When the top height of the shallow trench isolation 14 is less than the top height of the isolation layer 2 , the gate material of the sacrificial gate 9 needs to be formed on the semiconductor material layer 6 and the exposed isolation layer 2 . The above-mentioned gate material is etched to form a sacrificial gate 9 in a region of the isolation layer 2 and the semiconductor material layer 6 corresponding to the channel region 33 .

The gate material of the sacrificial gate 9 may be polysilicon, amorphous silicon or other materials. The above-mentioned sacrificial gate 9 extends along the second direction. As for the specific direction of the second direction, please refer to the previous article and will not be described in detail here.

It should be noted that, as shown in FIGS. 23 and 25 , when the silicon layer 7 is formed on the semiconductor material layer 6 , the silicon layer 7 and the semiconductor material layer 6 need to be in a region corresponding to the channel region 33 , or, in the silicon layer 7 7. The semiconductor material layer 6 and the isolation layer 2 form a sacrificial gate 9 in the area corresponding to the channel region 33.

In addition, after forming the sacrificial gate 9 and before performing subsequent operations, the first spacers 10 and the second spacers 11 extending in the second direction may be formed. The sacrificial gate 9 is located between the first spacer 10 and the second spacer 11 . As for the materials contained in the first side wall 10 and the second side wall 11 and their widths, please refer to the above description and will not be described again here.

Step S103: As shown in Figures 22 to 28, form a fin-shaped structure 3 on the isolation layer 2. The fin-shaped structure 3 extends along the first direction. The fin-shaped structure 3 includes a source region 31 , a drain region 32 and a channel region 33 . Channel region 33 is located between source region 31 and drain region 32 . Channel region 33 is in contact with source region 31 and drain region 32 respectively. The area of the isolation layer 2 covering the substrate 1 is less than or equal to the area of the fin structure 3 covering the substrate 1 . As for the specific direction of the first direction, the area of the substrate 1 covered by the isolation layer 2, etc., please refer to the above, and will not be described again here.

In an optional manner, as shown in Figures 26 to 28, forming the fin structure 3 on the isolation layer 2 includes:

Step S103.1: As shown in FIGS. 26 and 27 , remove the portion of the semiconductor material layer 6 located in the source region formation region 61 and the drain region formation region 62 . For example, wet etching or dry etching may be used to etch the portion of the semiconductor material layer 6 located in the source region formation region 61 and the drain region formation region 62 to facilitate the subsequent epitaxial formation of the source region 31 and the drain region 32 .

It should be noted that, as shown in FIGS. 25 and 27 , when the silicon layer 7 is formed on the semiconductor material layer 6 , the silicon layer 7 and the semiconductor material layer 6 corresponding to the source region formation region 61 and the drain region formation region 62 need to be removed. part.

Step S103.2: As shown in Figure 28 and Figure 29, source region 31 and drain region 32 are formed in source region formation region 61 and drain region formation region 62 respectively, and channel region 33 is in contact with source region 31 and drain region 32 respectively. .

For example, as shown in FIGS. 28 and 29 , the source region 31 can be formed in the source region forming region 61 by epitaxy, and the drain region 32 can be formed in the drain region forming region 62 . Channel region 33 is in contact with source region 31 and drain region 32 respectively. Specifically, the materials contained in the source region 31 and the drain region 32 can be referred to the above, and will not be described again here.

It should be noted that, as shown in FIGS. 30 and 31 , after the source region 31 and the drain region 32 are formed and before the sacrificial gate 9 is removed, a dielectric material may be deposited on the formed structure. The dielectric material is planarized until the top of the sacrificial gate 9 is exposed. At this time, the remaining dielectric material on the source region 31 forms the first dielectric layer 12 accordingly. The remaining dielectric material on the drain region 32 forms the second dielectric layer 13 accordingly.

Step S104: As shown in FIGS. 32 to 34 , a gate stack structure 4 located on the outer periphery of the channel region 33 is formed. The gate stack structure 4 extends along the second direction. Exemplarily, after the above-mentioned first dielectric layer 12 and second dielectric layer 13 are formed, the sacrificial gate 9 is removed. After that, the gate dielectric layer 41 and the gate electrode 42 can be sequentially formed on the outer periphery of the channel region 33 by means such as atomic layer deposition (ALD). As for the materials contained in the gate dielectric layer 41 and the gate electrode 42, please refer to the above.

It should be noted that, as mentioned above, if the silicon layer 7 is formed on the semiconductor material layer 6, after the sacrificial gate 9 is removed and before the gate stack structure 4 is formed, the remaining silicon located on the channel region 33 should be removed. Layer 7.

An embodiment of the present invention also provides an electronic device, which includes the fin field effect transistor provided in the above embodiment. The electronic device may be a terminal device or a communication device, but is not limited thereto. Further, terminal devices include mobile phones, smart phones, tablets, computers, artificial intelligence devices, mobile power supplies, etc. Communication equipment includes base stations, etc., but is not limited to these.

The beneficial effects of the electronic device provided by the embodiments of the present invention are the same as the beneficial effects of the fin field effect transistor provided by the above embodiments, and will not be described again here.

In the above description, there is no detailed explanation of the technical details such as patterning and etching of each layer. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. in desired shapes. In addition, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as those described above. In addition, although each embodiment is described separately above, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present disclosure.

Claims (13)

1. A fin field effect transistor, comprising:

the substrate is provided with a plurality of holes,

an isolation layer formed on the substrate; the isolation layer is formed by adopting selective oxidation treatment, and the object of the selective oxidation treatment is a layer to be oxidized; the material contained in the layer to be oxidized is Si _1-y Ge _y Wherein y is more than or equal to 0.2 and less than or equal to 0.8;

a fin structure formed on the isolation layer, the fin structure extending in a first direction, the fin structure including a source region, a drain region, and a channel region, the channel region being located between the source region and the drain region, the channel region being in contact with the source region and the drain region, respectively, the area of the isolation layer covering the substrate being less than or equal to the area of the fin structure covering the substrate; the channel region contains Si or Si as material _1-x Ge _x Wherein x is more than 0 and less than or equal to 0.6; when the material of the channel region is Si _1-x Ge _x When the content of Ge in the channel region is at least 20% lower than the content of Ge in the layer to be oxidized;

and a gate stack structure formed at an outer circumference of the channel region, the gate stack structure extending in the second direction.

2. The fin field effect transistor of claim 1, wherein the substrate is a silicon substrate, a silicon germanium substrate.

3. The finfet of claim 1, wherein a portion of the spacer under the source region is flush with a top of a portion of the spacer under the drain region.

4. The fin field effect transistor of any one of claims 1-3, wherein the isolation layer comprises a material selected from the group consisting of silicon oxide, silicon germanium oxide; and/or the number of the groups of groups,

the thickness of the isolation layer is 5 nm-50 nm.

5. The fin field effect transistor of claim 1, wherein the channel region comprises a material that is Si or Si _1-x Ge _x Wherein x is more than 0 and less than or equal to 0.6.

6. A method for fabricating a fin field effect transistor, comprising:

providing a substrate;

forming an isolation layer on the substrate;

forming a fin structure on the isolation layer, wherein the fin structure extends along a first direction and comprises a source region, a drain region and a channel region, the channel region is positioned between the source region and the drain region, the channel region is respectively contacted with the source region and the drain region, and the area of the isolation layer covering the substrate is smaller than or equal to the area of the fin structure covering the substrate;

forming a gate stack structure located at the periphery of the channel region, the gate stack structure extending in a second direction; wherein,

the forming an isolation layer on the substrate includes:

forming a layer to be oxidized and a semiconductor material layer positioned on the layer to be oxidized on the substrate, wherein the semiconductor material layer comprises a source region forming region, a drain region forming region and a channel region, and the channel region is positioned between the source region forming region and the drain region forming region; by a means ofThe material contained in the layer to be oxidized is Si _1-y Ge _y Wherein y is more than or equal to 0.2 and less than or equal to 0.8; the semiconductor material layer contains Si or Si _1-x Ge _x Wherein x is more than 0 and less than or equal to 0.6; when the material of the semiconductor material layer is Si _1-x Ge _x The Ge content in the semiconductor material layer is at least 20% lower than the Ge content in the layer to be oxidized

Selectively oxidizing the layer to be oxidized to obtain the isolation layer.

7. The method of claim 6, wherein when the semiconductor material layer contains Si _1-x Ge _x After the step of providing the substrate and before the step of oxidizing the layer to be oxidized, the manufacturing method of the fin field effect transistor further comprises the following steps:

a silicon layer is formed on the semiconductor material layer.

8. The method of claim 6, wherein the gas used to oxidize the layer to be oxidized is O ₂ And N ₂ Or, O ₃ And (3) gas.

9. The method of manufacturing a fin field effect transistor according to claim 6, wherein the method of oxidizing the layer to be oxidized is a furnace tube oxidation method or a rapid thermal processing method;

the treatment conditions of the furnace tube oxidation treatment mode are as follows: the treatment temperature is 500-850 ℃ and the treatment time is 10-60 min;

the treatment conditions of the rapid thermal treatment mode are as follows: the treatment temperature is 600-850 ℃, the treatment time is 30-60 s, and the treatment period is 1-10.

10. The method for fabricating a finfet according to any one of claims 6-9, wherein after forming an isolation layer on the substrate, before forming a fin structure on the isolation layer, the method for fabricating a finfet further comprises:

and forming a sacrificial gate in a region of the semiconductor material layer corresponding to the channel region, or in a region of the isolation layer and the semiconductor material layer corresponding to the channel region.

11. The method of claim 10, wherein forming a fin structure on the spacer layer comprises:

removing portions of the semiconductor material layer located in the source region forming region and the drain region forming region;

and forming a source region and a drain region in the source region forming region and the drain region forming region respectively, wherein the channel region is respectively contacted with the source region and the drain region.

12. An electronic device comprising a fin field effect transistor according to any one of claims 1 to 5.

13. The electronic device of claim 12, wherein the electronic device comprises a communication device or a terminal device.