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CN108022923A - 半导体封装 - Google Patents

半导体封装 Download PDF

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Publication number
CN108022923A
CN108022923A CN201710878050.3A CN201710878050A CN108022923A CN 108022923 A CN108022923 A CN 108022923A CN 201710878050 A CN201710878050 A CN 201710878050A CN 108022923 A CN108022923 A CN 108022923A
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CN
China
Prior art keywords
substrate
semiconductor chip
package
connection substrate
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710878050.3A
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English (en)
Other versions
CN108022923B (zh
Inventor
金京范
文贤钟
车承勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of CN108022923A publication Critical patent/CN108022923A/zh
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Publication of CN108022923B publication Critical patent/CN108022923B/zh
Active legal-status Critical Current
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Abstract

一种半导体封装包括第一封装和堆叠在第一封装上的第二封装。第一封装包括再分配基板、再分配基板上的第一半导体芯片、设置在再分配基板上的用于在平面图中观察时包围第一半导体芯片的连接基板、以及设置在连接基板的第一区域内并通过再分配基板电连接到第一半导体芯片的电感器结构。第二封装包括与第一封装电连接的至少一个外部端子。外部端子设置在连接基板的第二区域上，并且当在平面图中观察时，第一区域和第二区域彼此间隔开。

Description

半导体封装
优先权声明
本申请要求于2016年10月31日向韩国知识产权局递交的韩国专利申请10-2016-0143499的优先权，其全部内容通过引用合并于此。
技术领域
本发明构思涉及半导体封装以及层叠封装(PoP)半导体器件。
背景技术
在半导体行业中，已经开发出各种封装技术，以满足能够存储大量信息并且薄和/或紧凑的半导体器件和/或电子设备的需求。这些封装技术中的许多典型是半导体封装，其包括印刷电路板(PCB)和集成电路(IC)芯片，所述IC芯片通过键合线或凸点设置在PCB上并与PCB电连接。集成电路(IC)芯片通常嵌入在PCB上的模塑料中。这些技术允许IC芯片容易地用作电子产品的控制系统的一部分。随着半导体行业的成熟，需要具有更高功能度的半导体封装，从而可以提高电子产品的性能和操作速度，同时产品保持相对紧凑。因此，需要在最小的占用空间和/或厚度内包括更多数量的IC芯片的封装技术。
发明内容
根据本发明构思的一方面，提供了一种半导体器件，包括：第一封装和堆叠在第一封装上的第二封装，其中第一封装包括再分配基板、设置在再分配基板上的第一半导体芯片、设置在再分配基板上的连接基板以及位于连接基板的第一区域内并通过再分配基板电连接到第一半导体芯片的电感器结构，所述连接基板在器件的平面图中包围第一半导体芯片，其中第二封装包括电连接到第一封装的至少一个外部端子，并且其中所述外部端子设置在连接基板的第二区域上，并且所述第一区域和所述第二区域在器件的平面图中彼此间隔开。
根据本发明构思的另一方面，还提供了一种半导体封装和包括该封装的半导体器件，其中该封装包括：再分配基板、设置在再分配基板上的连接基板(连接基板具有贯穿其中的孔)、在连接基板的孔内设置在再分配基板上的第一半导体芯片、以及位于连接基板的第一区域内并通过再分配基板电连接到第一半导体芯片的电感器结构，其中第一半导体芯片的底表面和连接基板的底表面与再分配基板的顶表面接触。
根据本发明构思的另一方面，提供了一种半导体封装和包括该封装的半导体器件，其中该封装包括：再分配基板、设置在再分配基板上的连接基板(连接基板具有贯穿其中的孔)、在连接基板的孔内设置在再分配基板上的第一半导体芯片、以及位于连接基板的第一区域内并通过再分配基板电连接到第一半导体芯片的电感器结构，其中第一半导体芯片包括通过再分配基板电连接到电感器结构的电压调节焊盘，所述第一区域与第一半导体芯片的第一侧表面相邻，所述电压调节焊盘与第一半导体芯片的所述第一侧表面相邻。
根据本发明构思的另一方面，还提供了一种半导体封装和包括该封装的半导体器件，其中该封装包括：再分配基板，包括绝缘基板和在绝缘基板内延伸的导电迹线的内部布线层；连接基板，设置在再分配基板上，并且包括限定从其顶表面朝再分配基板在竖直方向上延伸的开口的绝缘构件、嵌入在绝缘构件内的至少一个电感器以及在竖直方向上延伸穿过绝缘构件以提供从绝缘构件的顶表面到再分配基板的导电路径的至少一个电连接器；以及在绝缘构件中的开口内设置在再分配基板上并与再分配基板的布线层电连接的半导体芯片，其中连接基板具有至少一个第一区域和至少一个第二区域，连接基板的所述至少一个电连接器被限制于连接基板的所述至少一个第一区域，连接基板的所述至少一个电感器被限制于连接基板的所述至少一个第二区域并通过再分配基板电连接到半导体芯片，并且连接基板的每个所述至少一个第一区域在所述封装的平面图中与连接基板的每个所述至少一个第二区域横向间隔开，使得所述至少一个电感器的占用空间不与连接基板的所述至少一个电连接器的占用空间重叠。
附图说明
根据以下结合附图进行的对本发明构思的非限制示例的简要描述，将更清楚地理解本发明构思。
图1是示出了设置有根据本发明构思的一些示例的半导体封装的电子设备的平面图。
图2是示出了根据本发明构思的一些示例的半导体封装或第一封装的平面图。
图3A和图3B是分别沿图2的线I-I’和II-II’截取的截面图。
图4A是示出了在图3A的区域N中的封装上设置的电感器的示例的透视图。
图4B是示出了在图3A的区域M中的封装上设置的电感器的示例的透视图。
图5是根据本发明构思的一些示例的在制造半导体封装的方法的过程中半导体封装的布局。
图6A、图7A、图8A、图9A和图10A是沿图5的线I-I’截取的截面图，图6B、图7B、图8B、图9B和图10B是沿图5的线II-II’截取的截面图。
图11是沿图2的线II-II’截取的截面图，其被提供为示出根据本发明构思的其他示例的半导体封装。
图12是示出了根据本发明构思的一些其他示例的半导体封装或第一封装的平面图。
图13是示出了根据本发明构思的一些其他示例的半导体封装或第一封装的平面图。
图14是沿图13的线I-I’截取的截面图。
应当注意，这些附图旨在说明在某些示例中使用的方法、结构和/或材料的一般特征，并对下面提供的书面描述进行补充。然而，这些附图并不是按比例的，也可能不能精确地反映任何给定示例的精确的结构或性能特征，并且不应被解释为限定或限制示例所包含的值或属性的范围。例如，为了清楚起见，分子、层、区域和/或结构元件的相对厚度和定位可被减小或夸大。在各种附图中使用相似或相同的附图标记旨在表示存在相似或相同的元件或特征。
具体实施方式
图1是示出了设置有根据本发明构思的一些示例的半导体封装的电子设备的平面图。
参考图1，半导体封装20和电源管理设备30可以设置在板10上。板10可以被配置为提供将半导体封装20连接到电源管理设备30的至少一个电路径40。作为示例，板10可以是印刷电路板(PCB)。电源管理设备30可以被配置为向半导体封装20供应电力。电源管理设备30可以是本领域本身已知的任何电源管理设备，并没有特别限制。下面将描述半导体封装20的示例。
图2是示出了根据本发明构思的一些示例的半导体封装或第一封装的平面图。图3A和图3B是分别沿图2的线I-I’和II-II’截取的截面图。图4A是示出了在图3A中由附图标记N指定的器件区域中设置的电感器的示例的透视图。图4B是示出了在图3A中由附图标记M指定的器件区域中设置的电感器的示例的透视图。
参考图2、图3A和图3B，第二封装P200可以堆叠在第一封装P100上。第一封装P100可以包括再分配基板500、连接基板200、第一半导体芯片300、第一模制层400和下侧外部端子550。第二封装P200可以包括封装基板700、第二半导体芯片800、第二模制层900和上侧外部端子690。连接基板200和第一半导体芯片300可以设置在再分配基板500上。再分配基板500可以具有比连接基板200的厚度小的厚度。第二半导体芯片800可以设置在封装基板700上。
连接基板200可以具有面向再分配基板500的顶表面的第二表面200b和与第二表面200b相对的第一表面200a。第一半导体芯片300可以具有面向再分配基板500的顶表面的第二表面300b和与第二表面300b相对的第一表面300a。连接基板200的第二表面200b和第一半导体芯片300的第二表面300b可以与再分配基板500的顶表面接触。连接基板200的第二表面200b可以与第一半导体芯片300的第二表面300b位于相同高度处，即，连接基板200的第二表面200b可以与第一半导体芯片300的第二表面300b共面。作为示例，连接基板200的第一表面200a可以与第一半导体芯片300的第一表面300a位于相同水平面。也就是说，连接基板200的第一表面200a可以与第一半导体芯片300的第一表面300a共面。在特定示例中，连接基板200的第一表面200a可以与第一半导体芯片300的第一表面300a位于不同水平面。
再分配基板500可以包括可被视为绝缘基板的绝缘层510、导电图案520和保护层511。导电图案520可以包括设置在相应绝缘层510之间的界面处的导线或“迹线”、用于将导线在竖直方向上彼此连接的通孔以及设置在再分配基板500的下部处的外部焊盘。下侧外部端子550可以设置在再分配基板500的底表面上并且可以连接到外部焊盘。作为示例，下侧外部端子550中的每一个可以是焊球或焊块(solder bump)。再分配基板500的导电图案520可以将第一半导体芯片300、连接基板200和下侧外部端子550相互电连接。
保护层511可以设置在再分配基板500的底表面上以覆盖外部焊盘。保护层511可以设置为部分覆盖下侧外部端子550。保护层511可以包括绝缘聚合物(例如，环氧树脂)。
参考图2，孔290可以延伸穿过连接基板200。第一半导体芯片300可以设置在连接基板200的孔290中。当在平面图中观察时，连接基板200可以包围第一半导体芯片300。第一半导体芯片300可以具有第一侧壁300a(或者如下文中可用的简单的“侧”)、第二侧壁300b、第三侧壁300c和第四侧壁300d。第一侧壁300a和第二侧壁300b可以在第一方向D1上延伸并且可以彼此相对。第三侧壁300c和第四侧壁300d可以在与第一方向D1相交的第二方向D2上延伸并且可以彼此相对。孔290可以由连接基板200的内侧壁限定，并且连接基板200的内侧壁可以面向第一半导体芯片300的第一至第四侧壁300a、300b、300c和300d。
当在平面图中观察时，连接基板200可以包括与第一半导体芯片300的第三侧壁300c和第四侧壁300d相邻的第一区域RG1。此外，连接基板200可以包括与第一半导体芯片300的第一侧壁300a和第二侧壁300b相邻的第二区域RG2。第一区域RG1可以与第二区域RG2间隔开(即，不重叠)。例如，第一区域RG1可以通过在其间插入第一半导体芯片300而在第一方向D1上彼此间隔开。第二区域RG2可以通过在其间插入第一半导体芯片300而在第二方向D2上彼此间隔开。第二区域RG2可以插入在第一区域RG1之间，使得第一区域RG1在第一方向D1上彼此间隔开。
返回参考图2、图3A和图3B，连接基板200可以包括可被视为绝缘基底的基底层210、与基底层210成一体的导电结构220以及与基底层210成一体的电感器结构230。作为示例，连接基板200可以是印刷电路板。基底层210可以包括多个堆叠绝缘层。导电结构220可以局部地设置在连接基板200的第一区域RG1中，并且电感器结构230可以局部地设置在连接基板200的第二区域RG2中。
因此，连接基板200的第一区域RG1(或者全体地)在封装的平面图中与连接基板200的第二区域RG2横向间隔开，使得电感器结构230的占用空间不与导电结构220的占用空间重叠。
导电结构220可以包括下焊盘221、布线图案222、第一通孔223和上焊盘224。下焊盘221可以设置在连接基板200的第二表面200b上，并且上焊盘224可以设置在连接基板200的第一表面200a上。第一通孔223可以将下焊盘221、布线图案222和上焊盘224在竖直方向上连接。换言之，上焊盘224可以通过布线图案222和第一通孔223电连接到下焊盘221。上焊盘224可以局部地设置在第一区域RG1上，而非第二区域RG2上。上侧外部端子690可以设置在上焊盘224上。
电感器结构230可以包括用于调节电压的电感器231、232和234以及第二通孔233。作为示例，电感器231、232和234可以包括在竖直方向上堆叠的第一电感器231、第二电感器232和第三电感器234。第一电感器231可以设置在与下焊盘221相同的高度处，第二电感器232可以设置在与布线图案222相同的高度处，并且第三电感器234可以设置在与上焊盘224相同的高度处。这里，与各元件结合使用的术语“设置在相同的高度处”可以指元件的底表面共面的情况(即，元件形成在同一平面上)或者元件的底表面和顶表面分别共面的情况(即，元件形成在同一平面上并具有基本上相同的厚度)。
参考图3A，第一至第三电感器231、232和234可以在区域M中通过第二通孔233在竖直方向上相互连接。换言之，第一至第三电感器231、232和234可以在区域M中相互串联连接。作为对比，在区域N中，第一至第三电感器231、232和234可以不相互串联连接。堆叠电感器的数量不限于图3A所示的示例的数量(三个)。
电感器结构230可以被配置为允许从图1的电源管理设备30提供的电力以第一半导体芯片300和第二半导体芯片800所需的电压电平提供给第一半导体芯片300和第二半导体芯片800。电感器结构230可以通过再分配基板500电连接到第一半导体芯片300。第一半导体芯片300可以包括第一芯片焊盘301，并且第一芯片焊盘301可以包括电连接到电感器结构230的电压调节焊盘301vr。电压调节焊盘301vr可以连接到第一半导体芯片300的电压调整部(电路)。
当在平面图中观察时，电压调节焊盘301vr可以设置为与第一半导体芯片300的第一侧壁300a和第二侧壁300b相邻。当在平面图中观察时，电感器结构230可以设置为与第一半导体芯片300的第一侧壁300a和第二侧壁300b相邻。因此，可以使电感器结构230和第一半导体芯片300之间的电通路的长度最小化，从而在电感器结构230和第一半导体芯片300之间的电力传输中提供高效率。
根据具有图1的布置的本发明构思的一些示例，电感器被设置在半导体封装20中(即，与其集成)，而不是设置在板10中。这可以使得板10的尺寸最小化并且简化半导体封装20和电源管理设备30之间的电通路40。连接基板200的厚度可以大于再分配基板500的厚度，因此，连接基板200的每个电感器231、232和234的大小或厚度可以大于或等于再分配基板500中的每个导电图案520的大小或厚度。在一些示例中，作为连接基板200的组成部分提供的电感器231、232和234可以被配置为具有相对低的电阻和相对高的电感。
图4A示例性地示出了设置在图3A的基底层210和区域N中的电感器231、232和234之一。电感器231、232和234中的至少一个可以包括导电线圈CO、第一导电延伸件EP1和第二导电延伸件EP2。导电线圈CO可以被配置为允许电感器231、232或234具有特定的电感值。第一导电延伸件EP1和第二导电延伸件EP2可以分别用作电感器的输入端子和输出端子，以向电感器输入信号和从电感器输出信号。
导电线圈CO和第一导电延伸件EP1可以位于相同高度。第二导电延伸件EP2可以与导电线圈CO和第一导电延伸件EP1位于不同高度。作为示例，第二导电延伸件EP2可以位于比导电线圈CO和第一导电延伸件EP1低的高度。第一导电延伸件EP1和第二导电延伸件EP2可以彼此间隔开。第一导电延伸件EP1和第二导电延伸件EP2可以分别连接到导电线圈CO的端部。第一导电延伸件EP1和第二导电延伸件EP2中的每一个可以是沿远离导电线圈CO的方向纵向延伸的导电材料的线性条。
图4B示例性地示出了设置在图3A的基底层210和区域M中的电感器231、232和234之一。第二通孔233可以连接到第二电感器232的第一导电延伸件EP1。第一电感器231可以设置在第二通孔233之下，并且可以连接到第二通孔233。也就是说，第一电感器231和第二电感器232可以在竖直方向上相互串联连接。
在一些示例中，电感器231、232和234可以被配置为具有图4A和图4B所示的结构，但本发明构思不限于此。
返回参考图2、图3A和图3B，第一半导体芯片300还可以包括与第二表面300b相邻的第一电路层310，并且这里，第一芯片焊盘301可以设置在第一电路层310上。第一电路层310可以包括形成在第一半导体芯片300的硅衬底上的晶体管以及形成在晶体管上的互连线。第一电路层310可以通过第一芯片焊盘301电连接到再分配基板500。第一半导体芯片300可以通过倒装芯片接合方式安装在再分配基板500上。第一半导体芯片300可以是例如处理器芯片。
第一模制层400可以覆盖连接基板200和第一半导体芯片300。例如，第一模制层400可以覆盖连接基板200和第一半导体芯片300的顶表面。此外，第一模制层400可以填充连接基板200和第一半导体芯片300之间的间隙。换言之，第一模制层400可以填充连接基板200的孔290的剩余部分。第一模制层400可以包括绝缘聚合物(例如，环氧树脂)。第一模制层400可以具有暴露上焊盘224的开口401。第一模制层400还可以覆盖第三电感器234。
第一封装P100和第二封装P200可以通过上侧外部端子690彼此电连接。上侧外部端子690可以局部地设置在上焊盘224上，因此，上侧外部端子690可以仅局部地设置在连接基板200的第一区域RG1上。例如，上侧外部端子690可以不设置在第二区域RG2上。作为示例，上侧外部端子690中的每一个可以是焊球或焊块。
封装基板700可以包括绝缘层、导电图案和保护层。封装基板700可以将第二半导体芯片800电连接到上侧外部端子690。在一些示例中，封装基板700可以具有与上述再分配基板500的结构类似的结构。
第二半导体芯片800可以包括第二电路层810和其上的第二芯片焊盘801。第二电路层810可以包括形成在第二半导体芯片800的硅衬底上的晶体管以及形成在晶体管上的互连线。第二电路层810和封装基板700可以通过第二芯片焊盘801彼此电连接。第二半导体芯片800可以通过倒装芯片接合方式安装在封装基板700上。在一些示例中，第二半导体芯片800可以是例如存储器芯片。尽管未示出，但是在某些示例中，可以设置多个第二半导体芯片800。多个第二半导体芯片800可以在封装基板700上在竖直方向上堆叠或二维地布置。
第二模制层900可以覆盖封装基板700和第二半导体芯片800。第二模制层900可以包括绝缘聚合物(例如，环氧树脂)。
图5至图10B示出了根据本发明构思的示例实施例的制造半导体封装的方法。图5是在制造过程中封装的布局的平面图。图6A、图7A、图8A、图9A和图10A是沿图5的线I-I’截取的截面图，图6B、图7B、图8B、图9B和图10B是沿图5的线II-II’截取的截面图。
参考图5、图6A和图6B，连接基板200可以设置在载体基板100上。连接基板200可以通过粘合层150附着到载体基板100。连接基板200的第二表面200b可以与粘合层150接触。孔290可以形成为延伸穿过连接基板200。连接基板200可以包括基底层210、设置在基底层210中的导电结构220和设置在基底层210中的电感器结构230。在一些示例中，连接基板200可以具有与参考图2、图3A和图3B描述的连接基板200基本相同的结构。
参考图5、图7A和图7B，第一半导体芯片300可以设置在载体基板100上。第一半导体芯片300中的每一个可以设置在连接基板200的孔290中的相应一个孔中。第一半导体芯片300中的每一个可以包括设置在第二表面300b中的第一电路层310以及设置在第一电路层310上的第一芯片焊盘301。第一半导体芯片300的第二表面300b可以与粘合层150接触。第一半导体芯片300中的每一个可以具有与参考图2、图3A和图3B描述的第一半导体芯片300基本相同的结构。
参考图5、图8A和图8B，第一模制层400可以形成在载体基板100上。第一模制层400可以形成为覆盖连接基板200的顶表面和第一半导体芯片300的顶表面。此外，第一模制层400可以形成为填充连接基板200和第一半导体芯片300之间的间隙。换言之，第一模制层400可以填充连接基板200的孔290的剩余部分。第一模制层400可以包括绝缘聚合物(例如，环氧树脂)。开口401可以形成在第一模制层400的上部以暴露上焊盘224。
此后，如虚线所示，可以去除载体基板100和粘合层150。结果，可以暴露第一半导体芯片300的第二表面300b和连接基板200的第二表面200b。
参考图5、图9A和图9B，再分配基板500可以设置在第一半导体芯片300的第二表面300b和连接基板200的第二表面200b上。再分配基板500的设置可以包括：在第一半导体芯片300的第二表面300b和连接基板200的第二表面200b上形成绝缘层510和导电图案520，形成保护层511，并形成下侧外部端子550。再分配基板500可以具有比连接基板200的厚度小的厚度。再分配基板500可以被配置为具有与参考图2、图3A和图3B描述的示例基本相同的特征。
参考图5、图10A和图10B，可以执行切割处理以形成第一封装P100。第一封装P100中的每一个可以包括至少一个第一半导体芯片300。
返回参考图2、图3A和图3B，第二封装P200可以安装在第一封装P100上。第二封装P200可以包括封装基板700、第二半导体芯片800、第二模制层900和上侧外部端子690。例如，第二封装P200的上侧外部端子690可以设置在连接基板200的第一区域RG1的上焊盘224上并连接到上焊盘224。第二封装P200可以具有与前述示例的封装P200基本相同的特征。
图11是沿图2的线II-II’截取的截面图，其被提供为示出根据本发明构思的半导体封装的其他示例。为了简明描述，先前参考图2、图3A、图3B和图4描述的元件可以由相似或相同的附图标记来标识，以避免重复其描述。
参考图2和图11，第二半导体芯片800可以安装在封装基板700上。第二半导体芯片部分800可以通过键合线820电连接到封装基板700。第二半导体芯片800的第二电路层810和第二芯片焊盘801可以邻近于第二半导体芯片800的顶表面而设置。键合线820可以接触第二芯片焊盘801。尽管未示出，但是在某些示例中，可以设置多个第二半导体芯片800。多个第二半导体芯片800可以在封装基板700上在竖直方向上堆叠或二维地布置。
图12是示出了根据本发明构思的半导体封装或第一封装的一些其他示例的平面图。为了简明描述，先前参考图2、图3A、图3B和图4描述的元件可以由相似或相同的附图标记来标识，以避免重复其描述。
参考图12，连接基板200的第一区域RG1可以与第一半导体芯片300的第一至第四侧壁300a、300b、300c和300d相邻。第一区域RG1中的每一个可以与第一至第四侧壁300a、300b、300c和300d中的相应一个的中心相邻。第二区域RG2可以位于连接基板200的除第一区域RG1之外的其余区域。第二区域RG2中的每一个可以插入在一对相邻的第一区域RG1之间。第一区域RG1中的每一个可以插入在一对相邻的第二区域RG2之间。换言之，第一区域RG1和第二区域RG2可以沿着第一半导体芯片300的周长交替地布置。
一对第一区域RG1可以在第一方向D1上彼此间隔开，其中第一半导体芯片300插入在该一对第一区域之间。另一对第一区域RG1可以在第二方向D2上彼此间隔开，其中第一半导体芯片300插入在该另一对第一区域之间。一对第二区域RG2可以在第四方向D4上彼此间隔开，其中第一半导体芯片300插入在该一对第二区域之间。第四方向D4可以是与第一方向D1和第二方向D2两者相交(即，倾斜于第一方向D1和第二方向D2)的方向。
导电结构220及其上的上侧外部端子690可以设置在第一区域RG1中，并且电感器结构230可以设置在第二区域RG2中。
图13是示出了根据本发明构思的半导体封装或第一封装的一些其他示例的平面图。图14是沿图13的线I-I’截取的截面图。为了简明描述，先前参考图2、图3A、图3B和图4描述的元件可以由相似或相同的附图标记来标识，以避免重复其描述。
参考图13和图14，第一孔291和第二孔293可以延伸穿过连接基板200。第一半导体芯片300可以设置在连接基板200的第一孔291中，并且第三半导体芯片350可以设置在第二孔293中。连接基板200可以包围第一半导体芯片300和第三半导体芯片350。连接基板200的第一区域RG1和第二区域RG2可以分别邻近于第一半导体芯片300和第三半导体芯片350的侧壁。
当在平面图中观察时，连接基板200可以包围第一半导体芯片300和第三半导体芯片350。第三半导体芯片350可以具有第五侧壁350a、第六侧壁350b、第七侧壁350c和第八侧壁350d。第五侧壁350a和第六侧壁350b可以在第一方向D1上延伸并且可以彼此相对。第七侧壁350c和第八侧壁350d可以在与第一方向D1相交的第二方向D2上延伸并且可以彼此相对。连接基板200可以被设置为使得限定第二孔293的内侧壁面向第一半导体芯片300的第五至第八侧壁350a、350b、350c和350d。
当在平面图中观察时，连接基板200的第一区域RG1可以与第一半导体芯片300的第三侧壁300c和第四侧壁300d以及第三半导体芯片350的第七侧壁350c和第八侧壁350d相邻。连接基板200的第二区域RG2可以与第一半导体芯片300的第一侧壁300a和第二侧壁300b以及第三半导体芯片350的第五侧壁350a和第六侧壁350b相邻。
与第一半导体芯片300类似，第三半导体芯片350可以通过倒装芯片接合方式安装在再分配基板500上。第三半导体芯片350和再分配基板500可以通过第三半导体芯片350的第三芯片焊盘351彼此电连接。第三半导体芯片350可以通过再分配基板500电连接到电感器结构230。作为示例，第三半导体芯片350可以是图1的电源管理设备30。在一些示例中，图1的板10以及其上的半导体封装20和电源管理设备30可以以单个封装的形式集成。
第二封装P200可以堆叠在第一封装P100上。第二封装P200可以包括多个第二半导体芯片800。第二半导体芯片800可以是相同种类的。例如，第二半导体芯片800可以是存储器芯片。
根据本发明构思的一些示例，在半导体封装中设置电感器结构，这可以以高效率在电感器结构和半导体芯片之间传输电力。在根据本发明构思的一些示例的半导体封装中，电感器结构可以具有相对低的电阻和相对高的电感。
尽管已经具体示出和描述了本发明构思的示例，但是本领域普通技术人员将理解，在不脱离由权利要求限定的本发明构思的真实精神和范围的情况下，可以在其中进行形式和细节上的改变。

Claims (25)

1.一种半导体器件，包括：
第一封装，包括：
再分配基板，
设置在所述再分配基板上的第一半导体芯片，
设置在所述再分配基板上的连接基板，所述连接基板在所述器件的平面图中包围所述第一半导体芯片，以及
电感器结构，位于所述连接基板的第一区域内，并通过所述再分配基板与所述第一半导体芯片电连接；以及
第二封装，堆叠在所述第一封装上，
所述第二封装包括与所述第一封装电连接的至少一个外部端子，
其中，所述外部端子设置在所述连接基板的第二区域上，以及
所述第一区域和所述第二区域在所述器件的平面图中彼此间隔开。
2.根据权利要求1所述的半导体器件，其中，所述第一半导体芯片具有第一表面和沿所述第一表面延伸的有源电路区域，以及
所述第一半导体芯片在所述器件中被定向为使得所述第一表面面向所述再分配基板。
3.根据权利要求2所述的半导体器件，其中，所述第一半导体芯片的所述第一表面与所述连接基板的底表面设置在相同的高度。
4.根据权利要求1所述的半导体器件，其中，所述连接基板比所述再分配基板厚。
5.根据权利要求1所述的半导体器件，其中，所述电感器结构包括多个在竖直方向上堆叠的电感器。
6.根据权利要求1所述的半导体器件，其中，所述第一区域与所述第一半导体芯片的侧表面相邻，以及
所述第一半导体芯片包括电压调节焊盘，所述电压调节焊盘与所述侧表面相邻并电连接到所述电感器结构。
7.根据权利要求1所述的半导体器件，其中，所述第一封装还包括：模制层，填充所述第一半导体芯片与所述连接基板之间的间隙。
8.根据权利要求1所述的半导体器件，其中，所述第一封装还包括：导电结构，设置在所述连接基板的所述第二区域内，
其中，所述导电结构包括：
下焊盘，与所述连接基板的底表面相邻并且与所述再分配基板接触；
上焊盘，在所述连接基板的顶表面上；以及
至少一个布线图案和至少一个通孔，所述至少一个布线图案和所述至少一个通孔插入在所述下焊盘和所述上焊盘之间并将所述下焊盘电连接到所述上焊盘。
9.根据权利要求1所述的半导体器件，其中，所述第二封装还包括：
封装基板；以及
在所述封装基板上的第二半导体芯片，
其中，所述第一半导体芯片是处理器芯片，以及
所述第二半导体芯片是存储器芯片。
10.根据权利要求9所述的半导体器件，其中，所述第二半导体芯片具有第一表面和沿所述第一表面延伸的有源电路区域，以及
所述第二半导体芯片的所述第一表面面向所述封装基板。
11.根据权利要求9所述的半导体器件，其中，所述第二封装还包括：键合线，将所述第二半导体芯片电连接到所述封装基板。
12.根据权利要求1所述的半导体器件，其中，所述连接基板具有一对第一区域和一对第二区域，
所述第一区域在第一方向上彼此间隔开，其中所述第一半导体芯片插入在所述第一区域之间，
所述第二区域在与所述第一方向相交的第二方向上彼此间隔开，其中所述第一半导体芯片插入在所述第二区域之间。
13.根据权利要求1所述的半导体器件，其中，所述第一半导体芯片具有第一侧表面、第二侧表面、第三侧表面和第四侧表面，
所述第一侧表面和所述第二侧表面在第一方向上延伸并且彼此相对，
所述第三侧表面和所述第四侧表面在与所述第一方向相交的第二方向上延伸并且彼此相对，
所述第一区域与所述第一侧表面相邻，
所述第二区域与所述第二侧表面相邻。
14.根据权利要求1所述的半导体器件，其中，所述第一半导体芯片具有第一侧表面、第二侧表面、第三侧表面和第四侧表面，
所述第一侧表面和所述第二侧表面在第一方向上延伸并且彼此相对，
所述第三侧表面和所述第四侧表面在与所述第一方向相交的第二方向上延伸并且彼此相对，
多个第二区域与所述第一侧表面和所述第三侧表面相邻，以及
所述第一区域插入在所述第二区域之间。
15.一种半导体封装，包括：
再分配基板；
设置在所述再分配基板上的连接基板，所述连接基板具有贯穿其中的孔；
第一半导体芯片，在所述连接基板的所述孔内设置在所述再分配基板上；以及
电感器结构，位于所述连接基板的第一区域内，并通过所述再分配基板与所述第一半导体芯片电连接，
其中，所述第一半导体芯片的底表面和所述连接基板的底表面均接触所述再分配基板的顶表面。
16.根据权利要求15所述的半导体封装，其中，所述第一半导体芯片具有底表面和沿所述底表面延伸的电路层。
17.根据权利要求15所述的半导体封装，还包括：模制层，填充所述第一半导体芯片和所述连接基板之间的间隙。
18.一种包括根据权利要求15所述的半导体封装的半导体器件，所述半导体器件还包括：
设置在所述连接基板上的封装基板；
插入在所述连接基板和所述封装基板之间的外部端子；以及
在所述封装基板上的第二半导体芯片，
其中，所述外部端子与所述连接基板的第一区域间隔开。
19.一种半导体封装，包括：
再分配基板；
设置在所述再分配基板上的连接基板，所述连接基板具有贯穿其中的孔；
第一半导体芯片，在所述连接基板的所述孔内设置在所述再分配基板上；以及
电感器结构，位于所述连接基板的第一区域内，并通过所述再分配基板与所述第一半导体芯片电连接，
其中，所述第一半导体芯片包括电压调节焊盘，所述电压调节焊盘通过所述再分配基板电连接到所述电感器结构，
所述第一区域与所述第一半导体芯片的第一侧表面相邻，以及
所述电压调节焊盘与所述第一半导体芯片的所述第一侧表面相邻。
20.根据权利要求19所述的半导体封装，其中，所述第一半导体芯片还包括与所述电压调节焊盘连接的电压调节电路。
21.一种包括根据权利要求19所述的半导体封装的半导体器件，所述半导体器件还包括：
设置在所述连接基板上的封装基板；
插入在所述连接基板和所述封装基板之间的外部端子；以及
设置在所述封装基板上的第二半导体芯片，
其中，所述外部端子设置在所述连接基板的第二区域上，以及
所述第二区域在所述器件的平面图中与所述第一区域间隔开。
22.一种半导体封装，包括：
再分配基板，包括绝缘基板和在所述绝缘基板内延伸的导电迹线的内部布线层；
设置在所述再分配基板上的连接基板，所述连接基板包括绝缘构件、至少一个电感器和至少一个电连接器，所述绝缘构件具有面向所述再分配基板的底表面和背向所述再分配基板的顶表面并且限定从所述顶表面朝所述再分配基板在竖直方向上延伸的开口，所述至少一个电感器嵌入在所述绝缘构件内，所述至少一个电连接器在竖直方向上延伸穿过所述绝缘构件以提供从所述绝缘构件的顶表面到所述再分配基板的导电路径；以及
半导体芯片，在所述绝缘构件中的所述开口内设置在所述再分配基板上并且电连接到所述再分配基板的所述布线层，
其中，所述连接基板具有至少一个第一区域和至少一个第二区域，
所述连接基板的所述至少一个电连接器被限制于所述连接基板的所述至少一个第一区域，
所述连接基板的所述至少一个电感器被限制于所述连接基板的所述至少一个第二区域并通过所述再分配基板电连接到所述半导体芯片，以及
所述连接基板的所述至少一个第一区域中的每一个在所述封装的平面图中与所述连接基板的所述至少一个第二区域中的每一个横向间隔开，使得所述至少一个电感器的占用空间不与所述连接基板的所述至少一个电连接器的占用空间重叠。
23.根据权利要求22所述的半导体封装，其中，所述半导体芯片具有面向所述再分配基板的底表面、背向所述再分配基板的顶表面、以及在所述顶表面和所述底表面之间延伸并面向相反方向的第一侧和第二侧，
所述连接基板的所述至少一个电连接器包括面向所述半导体芯片的所述第一侧的电连接器，以及
所述连接基板的所述至少一个电感器包括面向所述半导体芯片的所述第二侧的电感器。
24.根据权利要求22所述的半导体封装，其中，所述半导体芯片具有面向所述再分配基板的矩形底表面、背向所述再分配基板的矩形顶表面、第一侧、第二侧、第三侧和第四侧以及各侧相交处的角，
所述连接基板的所述至少一个电连接器包括如下电连接器，所述电连接器面向位于所述半导体芯片的一侧中的在所述半导体芯片的两个角之间的中心部分，以及
所述连接基板的所述至少一个电感器包括如下电感器，所述电感器沿着穿过所述半导体芯片的位于相对于所述半导体芯片的所述矩形顶表面和底表面的斜对角方向上的两个角的平面。
25.根据权利要求22所述的半导体封装，其中，所述连接基板的所述绝缘构件包括第一绝缘层和设置在所述第一绝缘层上的第二绝缘层，
所述至少一个电连接器包括在所述连接基板的所述第一区域中延伸穿过所述第一绝缘层和所述第二绝缘层的通孔，以及
所述至少一个电感器包括沿着所述连接基板的所述第一绝缘层和所述第二绝缘层之间的界面延伸并且通过所述绝缘构件与所述通孔电绝缘的线圈形式的导电迹线。
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