CN107994071A - A kind of hetero-junctions channel insulation grid-type field-effect tube - Google Patents

Abstract

The invention discloses a kind of hetero-junctions channel insulation grid-type field-effect tube, belong to semiconductor power device technology field.The present invention using silicon materials by the channel body region of traditional Si C UMOS devices and source region by replacing hetero-junctions UMOS devices, utilize the low energy gap of interfacial state and silicon materials good between silicon and silica, while ensureing reversely pressure-resistant, reduce conducting resistance, improve forward current, and in additional grid voltage channel MOS capacitance is reduced rapidly, after grid voltage reaches threshold voltage, reverse transfer capacitance reduces, so as to be improved the switching speed of device, the switching loss of device is reduced.And by rationally setting protection zone and JFET areas; solve the problems, such as since SiC and Si interface potential barriers damage device forward conduction performance and since voltage endurance is insufficient caused by trench gate structure bottom electric field concentration effect, gate oxide stability difference and the low energy gap of silicon the problem of so that device has good reverse voltage endurance capability.

Description

A Heterojunction Trench Insulated Gate Field Effect Transistor

technical field

The invention belongs to the technical field of semiconductor power devices, in particular to a heterojunction trench insulated gate field effect transistor.

Background technique

Silicon carbide (SiC), a wide bandgap semiconductor material, is an ideal material for preparing high-voltage power electronic devices. Compared with silicon materials, SiC materials have high breakdown electric field strength (4×10 ⁶ V/cm), carrier saturation drift velocity High (2×10 ⁷ cm/s), high thermal conductivity and good thermal stability, so it is especially suitable for the production of high-power, high-voltage, high-temperature and radiation-resistant electronic devices. The U-groove gate field effect transistor (SiC UMOS) made of SiC material is one of the power MOS devices with the best development prospects at present. Compared with the other two typical vertical power MOS devices-VVMOS and VDMOS, UMOS solves the problem of VVMOS The V-groove of the device is difficult to corrode, the gate oxide layer is exposed, the threshold voltage is unstable, and the reliability is not high. At the same time, it also avoids the JFET effect of VDMOS, so it has a lower opening than VVMOS and VDMOS. State resistance and lower power loss; in addition, because UMOS has a smaller cell size, it is beneficial to achieve higher channel density.

However, a common problem with SiC MOS devices is that the carrier channel mobility is very low. The root cause of this problem lies in the high interface states at the SiC/ _SiO2 interface. For SiC MOS devices, the high interface state trapping charges at the channel will form a large number of scattering centers, disturbing the transport of carriers in the channel, thereby greatly reducing the average drift velocity and mobility of carriers in the inversion layer. On the one hand, when the ohmic contact resistance of the electrode is ignored, the forward conduction resistance of the UMOS device is mainly the drift region resistance plus the channel resistance, because the channel electron mobility is much lower than the bulk mobility, so the channel The resistance is far greater than the resistance of the drift region, so the channel electron mobility is the most important factor affecting the on-resistance. The problem of high device on-resistance caused by low channel carrier mobility has become the biggest problem faced by SiC MOS devices, and it is also a technical problem to be solved urgently by those skilled in the art. On the other hand, the high interface state and wide bandgap width will also cause the problem of large channel capacitance, which will lead to slower switching speed and increased loss of the device.

Contents of the invention

In view of the deficiencies in the prior art, the purpose of the invention is to propose a heterojunction trench insulated gate field effect transistor for the problems of low carrier mobility and large channel capacitance of SiC MOS devices. By replacing the channel body region and source region of traditional SiCUMOS devices with silicon materials, the good interface state between silicon and silicon dioxide and the narrow bandgap width of silicon materials are used to increase the forward current of the device and reduce the reverse current. to transfer capacitance and reduce switching losses.

The technical solution adopted by the present invention to solve the above problems is as follows: a heterojunction trench insulated gate field effect transistor, comprising: a semiconductor drain ohmic contact region 8 of the first conductivity type, the front and back of which are sequentially provided with first Conduction type semiconductor drift region 7 and drain electrode 9, the center of the top layer of the first conductivity type semiconductor drift region 7 has a trench arranged along the vertical direction of the device, a gate electrode 1 is arranged in the trench, and a gap between the gate electrode 1 and the inner wall of the trench A gate oxide layer 2 is provided, and the top layer of the first conductivity type semiconductor drift region 7 on both sides of the trench is respectively provided with a second conductivity type semiconductor channel body region 6 in contact with the gate oxide layer 2, and the second conductivity type semiconductor channel body region 6 is respectively provided. The top layer of the channel body region 6 is provided with the first conductivity type semiconductor source region 3 in contact with the gate oxide layer 2, and the first conductivity type semiconductor source region 3 and the second conductivity type semiconductor channel body region 6 are both arranged above it. The source electrode 4 is equipotential; it is characterized in that: the material of the first conductivity type semiconductor source region 3 and the second conductivity type semiconductor channel body region 6 is silicon material, the first conductivity type semiconductor drift region 7 and the first conductivity type semiconductor The material of the drain ohmic contact region 8 is silicon carbide.

Further, in the present invention, the channel body region 6 of the semiconductor of the second conductivity type is connected to the source electrode 4 through the source ohmic contact region 5 of the semiconductor of the second conductivity type to achieve equipotentiality.

Further, in order to avoid the electric field in the gate oxide layer 2 and the channel body region 6 of the second conductivity type semiconductor being too high, the present invention sets the second conductivity type semiconductor protection region 10 in the first conductivity type semiconductor drift region 7 To shield the electric field, the second conductivity type semiconductor protection region 10 is located below the bottom of the trench.

Further, in order to avoid the formation of the JEFT effect due to the excessive width of the barrier region of the PN junction formed by the second conductivity type semiconductor protection region 10 and the first conductivity type semiconductor drift region 7, in the present invention, the first conductivity type semiconductor drift region 7 A first conductivity type semiconductor JFET region 11 in contact with the second conductivity type semiconductor protection region 10 is provided in the middle to ensure the forward characteristics of the device. Specifically, the doping concentration of the first conductivity type semiconductor JFET region 11 is greater than that of the first conductivity type The doping concentration of the semiconductor drift region 7 ; the first conductivity type semiconductor JFET region 11 is located above the second conductivity type semiconductor protection region 10 and/or between the second conductivity type semiconductor protection regions 10 .

Specifically, in the present invention, the first conductive type semiconductor is an N-type semiconductor, and the second conductive type semiconductor is a P-type semiconductor; or in the present invention, the first conductive type semiconductor is a P-type semiconductor, and the second conductive type semiconductor is an N-type semiconductor.

As a preferred manner, in the present invention, the doping concentration of the P-type semiconductor channel body region 6 is 1×10 ¹⁷ cm ⁻³ , and the doping concentration of the N-type semiconductor drift region 7 is 4×10 ¹⁵ cm ⁻³ .

As a preferred mode, the thickness of the P-type semiconductor protection region 10 in the present invention is 1.5 μm, and the doping concentration is 1×10 ¹⁸ cm ^-3 ;

As a preferred mode, the second conductivity type semiconductor protection area 10 is groove-shaped, so that the source electrode 4 extends into the second conductivity type semiconductor protection area 10, and the width of the source electrode 4 is 0.6 μm, which goes deep into the P-type semiconductor protection area 10 The depth is 1.2 μm.

As a preferred manner, the thickness of the N-type semiconductor JFET region 11 is 1.5 μm, and the doping concentration is 2×10 ¹⁶ cm ⁻³ .

The technical solution of the present invention aims to solve the problem of existing SiC UMOS devices caused by the low carrier mobility in the channel inversion layer at the contact interface between the gate oxide layer and the second conductivity type semiconductor channel body region 6 For the problem of excessive on-resistance, the interface formed by the silicon material and the gate oxide layer material, namely silicon dioxide, has good interface characteristics, and the interface state density of the channel layer is very low, so the carrier mobility of the channel is higher than that of the silicon material body. About half of the mobility, which is much higher than the carrier mobility at the interface between silicon carbide and silicon dioxide under the existing process, thereby effectively reducing the on-resistance and increasing the forward current of the device; moreover, due to the silicon The small band gap of the material greatly increases the carrier density of the channel under the same gate voltage, and at the same time, the channel MOS capacitance decreases rapidly under the action of the external gate voltage, so that after the gate voltage reaches the threshold voltage, the reverse transmission capacitance decreases , so as to obtain better switching characteristics; in addition, an accumulation layer is formed on the silicon carbide side by using an external gate voltage, and the energy band is lowered, so that the electron potential formed at the interface between silicon and silicon carbide, two materials with different electron affinities The barrier is narrowed, and the carriers (electrons or holes) pass through the electronic potential barrier under the action of the quantum tunneling effect, thereby avoiding adverse effects on the forward characteristics of the device.

Compared with prior art, the beneficial effect of the present invention is:

The heterojunction UMOS device formed by the two materials of SiC and Si provided by the present invention can reduce the on-resistance and increase the forward current while ensuring the reverse withstand voltage. After the gate voltage reaches the threshold voltage, the reverse transmission capacitance decreases, thereby improving the switching speed of the device and reducing the switching loss of the device.

Description of drawings

FIG. 1 is a schematic diagram of the structure of a traditional SiC U-shaped trench insulated gate field effect transistor (abbreviated as SiC UMOS).

2 is a schematic structural diagram of a SiC/Si heterojunction U-shaped trench insulated gate field effect transistor (abbreviated as SiC/Si UMOS) provided by Embodiment 1 of the present invention.

3 is a schematic structural diagram of a SiC/Si heterojunction U-shaped trench insulated gate field effect transistor provided by Embodiment 2 of the present invention.

4 is a schematic structural diagram of a SiC/Si heterojunction U-shaped trench insulated gate field effect transistor provided by Embodiment 3 of the present invention.

Fig. 5 is a comparison diagram of the reverse withstand voltage of the traditional SiC UMOS structure and the SiC/Si UMOS provided by Example 3 of the present invention.

FIG. 6 is a comparison diagram of the forward conduction resistance of the traditional SIC UMOS structure and the SiC/Si UMOS provided by Embodiment 3 of the present invention.

Fig. 7 is a schematic diagram of the energy band structure and tunneling effect at the heterojunction interface of SiC/Si UMOS provided by the present invention.

Fig. 8 is a comparison of the conduction band of the heterojunction interface under the condition of no gate voltage and external positive gate voltage (the position and x coordinate are shown by the arrows in Fig. 2).

FIG. 9 is a comparison diagram of the mobility distribution of the traditional SiC UMOS structure and the SiC/Si UMOS provided by Example 3 of the present invention.

FIG. 10 is a comparison diagram of switches between the SiC/Si UMOS provided by Embodiment 3 of the present invention and the DTMOS structure without SiC/Si heterojunction.

Fig. 11 is a diagram of the electric field simulation results when the P-type semiconductor protection area is added and the reverse drain voltage is 1200V.

FIG. 12 is a comparison diagram of reverse breakdown characteristics under two conditions without adding a P-type semiconductor protection area and adding a P-type semiconductor protection area.

FIG. 13 is a comparison diagram of the forward conduction resistance without adding the N-type JFET region and adding the N-type JFET region.

Detailed ways

The principle and characteristics of this technical solution will be further described below in conjunction with the embodiments of the present invention and the drawings of the description, so as to help understand the technical problems solved by the concept of the present invention, the technical means used and the technical effects achieved:

The embodiments provided below all take the N-channel UMOS device as an example. Those skilled in the art can obtain the working principle and performance of the P-channel UMOS device through simple replacement on this basis, and the present invention will not repeat them here.

Example 1:

As shown in Figure 2, a heterojunction trench insulated gate field effect transistor provided in this embodiment includes: a first conductivity type semiconductor drain ohmic contact region 8, and its front and back are sequentially provided with the first conductivity type Semiconductor drift region 7 and drain electrode 9, the center of the top layer of the semiconductor drift region 7 of the first conductivity type has a trench arranged along the vertical direction of the device, a gate electrode 1 is arranged in the trench, and a gate electrode 1 is arranged between the gate electrode 1 and the inner wall of the trench. The gate oxide layer 2, the top layer of the first conductivity type semiconductor drift region 7 on both sides of the trench are respectively provided with the second conductivity type semiconductor channel body region 6 in contact with the gate oxide layer 2, the second conductivity type semiconductor channel body region 6 The top layer of the region 6 is provided with a first conductivity type semiconductor source region 3 in contact with the gate oxide layer 2 and a second conductivity type source ohmic contact region 5 in contact with the first conductivity type semiconductor source region 3, the first conductivity type The top of the semiconductor source region 3 and the second conductivity type source ohmic contact region 5 is connected to the source electrode 4; it is characterized in that: the material of the first conductivity type semiconductor source region 3 and the second conductivity type semiconductor channel body region 6 is silicon Material, the material of the drift region 7 of the semiconductor of the first conductivity type and the drain ohmic contact region 8 of the semiconductor of the first conductivity type is silicon carbide.

In this embodiment, the semiconductor of the first conductivity type is an N-type semiconductor, and the semiconductor of the second conductivity type is a P-type semiconductor.

According to the above technical solutions, it can be seen that the gist of the present invention is to replace the SiC/ _SiO2 of the traditional SiC MOS device with a Si/ _SiO2 channel to reduce the forward conduction resistance of the device. It is known to those skilled in the art that: to reduce the UMOS The on-resistance of the device must increase the mobility of carriers in the channel inversion layer at the contact interface between the gate oxide layer 2 and the first conductivity type semiconductor channel body region 6, and currently affects the inversion layer carrier The main factor of mobility is attributed to the high interface state at the interface between SiC and SiO ₂ . This interface state is limited by the existing technology level. Under the current technology level, the carrier mobility at the interface between SiC and SiO ₂ is very low, but the present invention adopts the heterojunction structure formed by Si/SiC, and adopts Si material in the first conductivity type semiconductor source region 3 and the second conductivity type semiconductor channel body region 6 of the UMOS device, thereby avoiding the SiC trench Due to the high interface state problem of the channel layer, the channel carrier mobility of the device can reach about half of the bulk mobility. For N-channel UMOS devices, compared with the electron mobility at the contact interface between Si and SiO ₂ , SiC and SiO 2 The highest electron mobility at the contact interface of SiO ₂ can only reach about one-tenth of it; and the Si material with a low bandgap width acts as a channel, which can increase the channel inversion carrier density. Therefore, Si/SiC The on-resistance of heterojunction UMOS devices is much lower than conventional SiC UMOS. In addition, the low band gap and low interface state of the Si material make the channel MOS capacitance decrease rapidly under the action of the external gate voltage. When the gate voltage reaches the threshold voltage, the reverse transmission capacitance is significantly reduced, thus obtaining a better performance. good switching characteristics.

However, while using Si and SiC heterojunction structures to improve carrier mobility, there are also some problems that need to be solved to take into account the improvement of forward and reverse performance. The specific problems are as follows:

Problem 1: Due to the SiC and Si interface barrier, the forward conduction of the device is adversely affected;

Problem 2: premature breakdown of the gate oxide layer at the bottom of the trench gate and premature breakdown of the body region of the channel of the second conductivity type semiconductor.

In view of the above two problems, the present invention proposes the technical solutions disclosed in Embodiment 2 and Embodiment 3.

Example 2:

As shown in Figure 3, a heterojunction trench insulated gate field effect transistor provided in this embodiment includes: a first conductivity type semiconductor drain ohmic contact region 8, and its front and back are sequentially provided with the first conductivity type Semiconductor drift region 7 and drain electrode 9, the center of the top layer of the semiconductor drift region 7 of the first conductivity type has a trench arranged along the vertical direction of the device, a gate electrode 1 is arranged in the trench, and a gate electrode 1 is arranged between the gate electrode 1 and the inner wall of the trench. The gate oxide layer 2, the top layer of the first conductivity type semiconductor drift region 7 on both sides of the trench are respectively provided with the second conductivity type semiconductor channel body region 6 in contact with the gate oxide layer 2, the second conductivity type semiconductor channel body region 6 The top layer of the region 6 is provided with a first conductivity type semiconductor source region 3 in contact with the gate oxide layer 2 and a second conductivity type source ohmic contact region 5 in contact with the first conductivity type semiconductor source region 3, the first conductivity type The top of the semiconductor source region 3 and the second conductivity type source ohmic contact region 5 is connected to the source electrode 4; it is characterized in that: the first conductivity type semiconductor drift region 7 also has a second conductivity type semiconductor protection region 10 to realize electric field shielding , the second conductivity type semiconductor protection area 10 is located below the two ends of the trench bottom; type semiconductor JFET region 11 to ensure the forward characteristics of the device, specifically, the doping concentration of the first conductivity type semiconductor JFET region 11 is greater than the doping concentration of the first conductivity type semiconductor drift region 7, and the first conductivity type semiconductor JFET region 11 is located above the second conductivity type semiconductor protection area 10 and/or between the second conductivity type semiconductor protection area 10; the material of the first conductivity type semiconductor source region 3 and the second conductivity type semiconductor channel body region 6 is silicon material The material of the first conductivity type semiconductor drift region 7 and the first conductivity type semiconductor drain ohmic contact region 8 , the second conductivity type semiconductor protection region 10 and the first conductivity type semiconductor JFET region 11 is silicon carbide.

In this embodiment, the semiconductor of the first conductivity type is an N-type semiconductor, and the semiconductor of the second conductivity type is a P-type semiconductor;

The design of this embodiment can solve the problem of premature breakdown of the device caused by the U-shaped trench gate structure and the characteristics of the Si material. Specifically, the electric field concentration will appear at the sharp corner of the bottom of the gate oxide layer 2 of the U-shaped trench gate structure. Therefore, the gate oxide layer 2 is easy to break down in advance; and the Si material has a narrow band gap, so the withstand voltage is an order of magnitude lower than that of SiC, so the second conductivity type semiconductor channel body region 6 is also easy to break down in advance. The present invention controls most of the electric field in the first conductivity type semiconductor drift region 7 by adding the second conductivity type semiconductor protection region 10 in the first conductivity type semiconductor drift region 7: the second conductivity type semiconductor protection region 10 and its below The first conductive type semiconductor drift region 7 forms a P+N junction. When a reverse voltage is applied, the P+N junction is reverse-biased, and the barrier region of the P+N junction will bear most of the reverse electric field, thereby greatly reducing the gate voltage. The electric field strength of the oxide layer 2 and the second conductivity type semiconductor channel body region 6 avoids the early breakdown of these two places, and limits the breakdown region to the first conductivity type semiconductor drift region below the second conductivity type semiconductor protection region 10 7, so the breakdown region of this structure is the barrier region of the P+N junction, and mainly depends on the concentration and thickness of the first conductivity type semiconductor drift region 7; meanwhile, the P+N junction will be in the N-type A relatively wide potential barrier region is formed in the region. If the potential barrier region is too wide, the conductive channel will be narrowed or even pinched, which will affect the magnitude of the forward current. Therefore, the present invention increases A highly doped semiconductor JFET region of the first conductivity type, which can narrow the barrier region to avoid the formation of the JEFT effect, thereby reducing its influence on the forward current.

Example 3:

As shown in Figure 4, a heterojunction trench insulated gate field effect transistor provided in this embodiment includes: a first conductivity type semiconductor drain ohmic contact region 8, and its front and back are sequentially provided with the first conductivity type Semiconductor drift region 7 and drain electrode 9, the center of the top layer of the semiconductor drift region 7 of the first conductivity type has a trench arranged along the vertical direction of the device, a gate electrode 1 is arranged in the trench, and a gate electrode 1 is arranged between the gate electrode 1 and the inner wall of the trench. The gate oxide layer 2, the top layer of the first conductivity type semiconductor drift region 7 on both sides of the trench are respectively provided with the second conductivity type semiconductor channel body region 6 in contact with the gate oxide layer 2, the second conductivity type semiconductor channel body region 6 The top layer of the region 6 is provided with a first conductivity type semiconductor source region 3 in contact with the gate oxide layer 2, and the first conductivity type semiconductor source region 3 and the second conductivity type semiconductor channel body region 6 are connected to the source electrode 4; It is characterized in that: the source electrode 4 and part of the second conductivity type semiconductor channel body region 6 are provided with a second conductivity type semiconductor protection area 10, in practice, the second conductivity type semiconductor protection area 10 can be made into a groove shape , so that the source electrode 4 extends into the second conductivity type semiconductor protection region 10; the first conductivity type semiconductor JFET region 11 is provided under the gate oxide layer 2, and the first conductivity type semiconductor JFET region 11 is between the second conductivity type semiconductor region 10 Between the two conductivity type semiconductor protection regions 10 and connected thereto; the material of the first conductivity type semiconductor source region 3 and the second conductivity type semiconductor channel body region 6 is silicon material, the first conductivity type semiconductor drift region 7 and the first The conductive type semiconductor drain ohmic contact region 8, the second conductive type semiconductor protection region 10 and the first conductive type semiconductor JFET region 11 are made of silicon carbide;

In this embodiment, the semiconductor of the first conductivity type is an N-type semiconductor, and the semiconductor of the second conductivity type is a P-type semiconductor.

The position, size and doping concentration of the second conductivity type semiconductor protection area 10 and the second conductivity type semiconductor protection area 11 will affect the forward and reverse characteristics of the Si/SiC UMOS device. In this embodiment, parameters such as:

The device width is 4 μm, and its thickness is 9 μm;

The depth of the gate electrode 1 and its oxide layer 2 is 1 μm;

The width of the N-type semiconductor source region 3 is 0.7 μm, its thickness is 0.2 μm, and the doping concentration of the N-type semiconductor source region 3 is 1×10 ²⁰ cm ⁻³ ;

The width of the P-type semiconductor channel body region 6 is 0.7 μm, its thickness is 0.6 μm, and the doping concentration of the P-type semiconductor channel body region 6 is 1×10 ¹⁷ cm ⁻³ .

The P-type semiconductor protection region 10 is located inside the drift region below the channel region, has a size of 1.5 μm×0.7 μm, and a doping concentration of 1×10 ¹⁸ cm ⁻³ ;

The thickness of the N-type semiconductor JFET region is 1.5 μm and the doping concentration is 2×10 ¹⁶ cm ^-3 ;

When the device is turned on, the accumulation layer formed in the N-type semiconductor JFET region 11 has a longitudinal dimension of 0.2 μm.

The beneficial technical effects produced by this embodiment will be analyzed in detail below in combination with the data and physical principles obtained from the simulation:

(1) The structure of the present invention can ensure the reverse withstand voltage of the traditional SiC UMOS. Figure 5 is a comparison of the reverse breakdown curves of the simulated Si/SiC UMOS structure and the traditional SiC UMOS structure. It can be seen from this that The breakdown voltage is similar. At the same time, the present invention can also greatly reduce the on-resistance of the device. FIG. 6 is a graph of the specific on-resistance of the simulated Si/SiC UMOS structure and the traditional UMOS structure as a function of the gate-source voltage. The variation range is 7V to 15V. This comparison was performed under similar breakdown voltage conditions as shown in Figure 3. Among them, curve 31 is a traditional SiC UMOS, and curve 32 is a heterojunction UMOS. It can be seen from the figure that the forward specific on-resistance of the two structures has the same trend of changing with the gate-source voltage, and both decrease with increasing Small, and the rate of reduction gradually slows down. Under the same conditions, the specific on-resistance of heterojunction UMOS is significantly lower than that of traditional SiC UMOS.

In SiC MOS devices, the most important factor determining the conduction current is the mobility of the carrier channel, and the reason for the sharp decrease of the carrier mobility in the channel layer is the high interface at the SiC/SiO ₂ interface. The states will bring a large number of traps, which will greatly affect the directional movement of carriers; therefore, as long as the problem of high interface states in the channel layer can be solved, the on-current of SiC UMOS can be greatly improved and its on-resistance can be reduced.

It should be pointed out that: as shown in FIG. 7, at the Si/SiC heterojunction interface where the second conductivity type semiconductor channel body region 6 and the first conductivity type semiconductor JFET region 11 contact Affinity, that is, the energy of the conduction band is different, which will form an interface barrier, and the conduction band will bend at the interface, and the conduction band will bend down on the side of the second conductivity type semiconductor channel body region 6 on the Si side, forming an electron accumulation layer. The conduction band on the side of the drift region 7 on the SiC side bends up, forming an electron barrier with a height of ΔEc, which will hinder the movement of electrons, increase the on-resistance, and greatly reduce the electron mobility at the interface.

In this embodiment, by rationally designing the structure, the region where the gate oxide layer 2 is in contact with the first conductivity type semiconductor drift region 7 or the first conductivity type semiconductor JFET region 11 can form a heavily doped accumulation layer under the action of the gate voltage, so that the The regional energy band decreases, thus forming an energy band structure similar to ohmic contact at the heterojunction interface, and the width of the heterojunction barrier becomes very narrow. According to the quantum tunneling effect, the probability of electrons passing through the barrier is proportional to the barrier width Therefore, when the potential barrier width is very narrow, electrons can easily pass through the potential barrier. Therefore, when the device is turned on in the forward direction, the heterojunction barrier hardly causes damage to the forward characteristics of the device. As shown in FIG. 8, a comparison diagram of the conduction band of the heterojunction with and without an applied forward gate voltage obtained based on the simulation of the device structure provided by Example 3 is shown. The position and direction are indicated by the x arrows in FIG. 4 As shown, the curve 91 is the conduction band curve obtained under the condition of applying a forward gate voltage of 15V, while the curve 92 is obtained under the condition of no external gate voltage. It can be seen from the figure that in the absence of an external gate voltage, the conduction band structure of the heterojunction is a pN heterojunction, and the interface barrier width is wide, so it is difficult for carriers to tunnel through the interface; After the forward gate voltage, the following two changes occurred: one is the inversion of the channel on the Si side, and the heterojunction becomes an nN homotype heterojunction, and the other is the formation of an accumulation layer on the SiC side, which makes the conduction The band decreases, so the width of the heterojunction barrier is greatly reduced, and the carriers can easily pass through the interface barrier by tunneling.

Based on the technical means of the present invention, the on-resistance can be reduced, and the forward current of the UMOS device can be significantly increased. As shown in FIG. 9, the comparison diagram of the mobility distribution between the traditional SiC UMOS structure and the SiC/Si UMOS provided by Example 3 of the present invention is Obtained under the condition of an external gate voltage of 15V, it can be seen that the channel mobility of the Si/SiC UMOS of the present invention is about 660cm/Vs, while the traditional UMOS is very low, only about 20cm/Vs, and the interface carrier migration The rate is about half of the material bulk mobility, much higher than the SiC/SiO ₂ interface carrier mobility.

(2), the present invention utilizes the low band gap and low interface state of the Si material, so that the channel MOS capacitance is rapidly reduced under the effect of the external gate voltage, and when the gate voltage reaches the threshold voltage, the reverse transmission capacitance is significantly reduced , resulting in better switching characteristics. As shown in Figure 10, it is a switch comparison diagram of the DTMOS structure of the SiC/Si junction of the present invention and the DTMOS structure without the heterojunction. The DTMOS without the heterojunction refers to the first The conductivity type semiconductor source region 3 and the second conductivity type semiconductor channel body region 6 are made of the same SiC material as other regions, and the doping concentration and size of each region are consistent with HDTMOS structure. Since the addition of the P-shield region will also optimize the switching characteristics to a certain extent, the optimization effect of the heterojunction structure on the switching characteristics can be clearly seen through such a comparison. Among them: Figures (a), (b), (c), and (d) are HDTMOS turn-on and turn-off processes, and DTMOS turn-on and turn-off processes respectively. The gray curve is the drain-source voltage change process during the switching process, black For the leakage current change process. It can be seen that compared with the traditional DTMOS without heterojunction structure, the turn-on time of the HDTMOS of the present invention is greatly reduced, the turn-off time is basically equal, and the total switching loss is reduced by about 30%.

(3) In the present invention, the second conductivity type semiconductor protection region 10 and the first conductivity type semiconductor JFET region 11 are formed by ion implantation in the first conductivity type semiconductor drift region 7 . The P+N junction formed by the second conductivity type semiconductor protection region 10 and the N- region below it is reverse-biased under the reverse drain voltage, and there is a strong electric field in the barrier region, which bears most of the drain voltage, so The second conductivity type semiconductor protection area 10 has played a good role in shielding the electric field. As shown in Figure 11, the electric field simulation results when the P-type semiconductor protection area is added and the reverse drain voltage is 1200V, the increase of this structure makes the gate The electric field in the oxide layer 2 and the semiconductor channel body region 6 of the second conductivity type is greatly reduced to prevent the early breakdown of these two places, thereby limiting the breakdown region inside the SiC, so the present invention has a performance similar to that of the traditional SiC UMOS Pressure resistance. As shown in Figure 12, the curve 71 is the reverse breakdown curve when the P-type semiconductor protection area 10 is not added, and the curve 72 is the reverse breakdown curve after adding the P-type semiconductor protection area 10, it can be seen that the P-type semiconductor protection area is not added. When the type semiconductor protection area is 10, the device breaks down in advance at about 300V, and the device maintains the high withstand voltage characteristics of SiC devices after the addition. However, P+N junctions will also be formed with the N-drift region 7 between the P-type semiconductor protection regions 10, and the potential barrier regions of these P+N junctions are mainly distributed in the N-type semiconductor drift region 7, which is too wide The potential barrier region of the N-type semiconductor drift region 7 can effectively reduce the barrier width of the P+N junction in the N-type semiconductor drift region 7, thereby reducing the pressure of the JFET. effect, reduce the damage caused by the P-type semiconductor protection area 10 to the forward characteristics of the UMOS device, increase the forward conduction current of the UMOS device, and reduce the forward conduction resistance, as shown in Figure 13, and the curve 81 in Figure 8 is to increase the N After the N-type semiconductor JFET region 11, the curve of the specific on-resistance changing with the gate-source voltage, the curve 82 is the curve of the specific on-resistance changing with the gate-source voltage when there is no N-type semiconductor JFET region 11. It can be seen that this structure can effectively reduce the UMOS The on-resistance of the device, especially when the gate-source voltage is larger (than when the on-resistance is already small), the effect is more obvious.

Claims (7)

1. a kind of hetero-junctions channel insulation grid-type field-effect tube, including：First conductive type semiconductor drain ohmic contact area (8), its front and back is equipped with the first conductive type semiconductor drift region (7) and drain electrode (9), the first conduction type half successively The top central of conductor drift region (7) has the groove set along device vertical direction, and gate electrode (1), grid electricity are equipped with groove Pole (1) is equipped with gate oxide (2), the top of the first conductive type semiconductor drift region (7) of groove both sides between trench wall Layer is respectively equipped with the second conductive type semiconductor channel body region (6) being in contact with gate oxide (2), and the second conduction type is partly led The top layer in bulk channel body area (6) is equipped with the first conductive type semiconductor source region (3) being in contact with gate oxide (2), and first leads Electric type semiconductor source region (3) and the second conductive type semiconductor channel body region (6) with source electrode (4) equipotential；Its feature It is：The material of first conductive type semiconductor source region (3) and the second conductive type semiconductor channel body region (6) is silicon materials, The material in the first conductive type semiconductor drift region (7) and the first conductive type semiconductor drain ohmic contact area (8) is carbonization Silicon.

A kind of 2. hetero-junctions channel insulation grid-type field-effect tube according to claim 1, it is characterised in that：Second conductive-type It is connected between type semiconductor channel body area (6) and source electrode (4) by the second conductive type semiconductor source electrode ohmic contact regions (5) Realize equipotential.

A kind of 3. hetero-junctions channel insulation grid-type field-effect tube according to claim 1, it is characterised in that：Described first leads Also there is the second conductive type semiconductor protection zone (10), second conduction type half in electric type semiconductor drift region (7) Conductor protection zone (10) is located at below channel bottom.

A kind of 4. hetero-junctions channel insulation grid-type field-effect tube according to claim 3, it is characterised in that：Described second leads Electric type semiconductor protection zone (10) is connected with source electrode (4) and the second conductive type semiconductor channel body region (6), and second Conductive type semiconductor channel body region (6) causes source electrode (4) to extend into it for groove-like.

A kind of 5. hetero-junctions channel insulation grid-type field-effect tube according to claim 3 or 4, it is characterised in that：Described Also have be in contact with the second conductive type semiconductor protection zone (10) first to lead in one conductive type semiconductor drift region (7) Electric type semiconductor JFET areas (11), the first conductive type semiconductor JFET areas (11) are located at the second conductive type semiconductor Between the top of protection zone (10) and/or the second conductive type semiconductor protection zone (10).

A kind of 6. hetero-junctions channel insulation grid-type field-effect tube according to any one of claims 1 to 5, it is characterised in that： First conductive type semiconductor is N-type semiconductor, and the second conductive type semiconductor is P-type semiconductor.

A kind of 7. hetero-junctions channel insulation grid-type field-effect tube according to any one of claims 1 to 5, it is characterised in that： First conductive type semiconductor is P-type semiconductor, and the second conductive type semiconductor is N-type semiconductor.