CN116825824B - LDMOS device and manufacturing method of silicon carbide and silicon heterojunction - Google Patents

Abstract

The application relates to the field of semiconductors, and provides an LDMOS device of silicon carbide and silicon heterojunction and a manufacturing method thereof. The LDMOS device comprises: the semiconductor device includes a silicon substrate, a first conductivity type well region, a second conductivity type body region, a first conductivity type drift region, a source region, a drain region, and a gate structure, and further includes: a buried layer of a second conductivity type; the second conductive type buried layer and the second conductive type body region are made of silicon, and the first conductive type drift region and the first conductive type drain region are made of silicon carbide; the first conductive type drift region is longitudinally connected with the second conductive type buried layer so as to form a heterojunction of silicon carbide and silicon in a longitudinally connected interface region in a conductive state; the first conductivity type drift region laterally interfaces with the second conductivity type body region to form a silicon carbide to silicon heterojunction at a laterally interface region in a conductive state. The application utilizes the longitudinal and transverse double heterojunctions to improve the breakdown voltage of the device, improve the mobility of carriers and reduce the on-resistance.

Description

LDMOS device and manufacturing method of silicon carbide and silicon heterojunction

Technical field

The present invention relates to the field of semiconductors, and specifically relates to an LDMOS device of silicon carbide and silicon heterojunction, a manufacturing method of an LDMOS device of silicon carbide and silicon heterojunction, and a power chip.

Background technique

In recent years, with the vigorous development of clean energy, related power electronic devices have put forward higher requirements for indicators such as operating voltage and power density. Traditional Si-based LDMOS (Lateral Double-diffused MOSFET, lateral double-diffused metal oxide semiconductor field effect transistor) power devices are limited by the bandgap width, temperature characteristics, critical breakdown electric field and other characteristics of the Si material, which is not conducive to further improvement of performance. . Compared with Si materials, SiC materials have characteristics such as wide bandgap, high breakdown field strength, high saturation electron velocity, high thermal conductivity, good chemical stability, and strong radiation resistance. It is an ideal material for realizing high-performance power devices. , and LDMOS devices made using a single SiC epitaxial substrate are high in cost and have poor compatibility with traditional Si-based semiconductor processes, which is not conducive to improving device integration.

The breakdown voltage and on-resistance of LDMOS devices are the most important electrical parameters. Increasing the breakdown voltage and reducing the on-resistance are important indicators. In the existing technology, the breakdown voltage of the device is increased by arranging a shallow trench isolation structure (STI) or a field oxide layer structure on the surface of the LDMOS drift region, but it also causes the problem of increased on-resistance, and STI isolation The accumulation of Si-SiO2 interface states at the interface between the trench or field oxide layer structure and the Si substrate will cause long-term degradation of device performance.

How to use the characteristics of SiC materials to improve the LDMOS structure, and how to use SiC materials to make LDMOS devices based on the traditional Si-based semiconductor process to increase the breakdown voltage of the device and reduce the on-resistance are currently urgent problems that need to be solved.

Contents of the invention

The object of the present invention is to provide an LDMOS device and a manufacturing method of silicon carbide and silicon heterojunction, so as to increase the breakdown voltage of the device and reduce the on-resistance.

In order to achieve the above object, on the one hand, the present invention provides an LDMOS device of silicon carbide and silicon heterojunction, including: a silicon substrate, a first conductive type well region, a second conductive type body region, a first conductive type drift region, The source region, drain region and gate structure also include: a second conductivity type buried layer;

The material of the second conductivity type buried layer and the second conductivity type body region is silicon, and the material of the first conductivity type drift region and the drain region is silicon carbide;

The first conductivity type drift region is longitudinally connected to the second conductivity type buried layer to form a heterojunction of silicon carbide and silicon in the longitudinally connected interface region when in the conductive state;

The first conductive type drift region and the second conductive type body region are laterally connected to form a heterojunction of silicon carbide and silicon in the laterally connected interface region in the conductive state.

In the embodiment of the present invention, the first conductivity type drift region includes: a first conductivity type ion-doped silicon carbide drift region and an undoped silicon carbide transition region; the first conductivity type ion doped silicon carbide The drift region is vertically connected to the second conductive type buried layer and laterally connected to the second conductive type body region; the undoped silicon carbide transition region is located in the first conductive type ion-doped The surface of the silicon carbide drift region is laterally connected to the second conductive type body region.

In an embodiment of the present invention, a first conductivity type accumulation region is provided between the first conductivity type drift region and the second conductivity type body region.

In the embodiment of the present invention, the gate structure includes: a polysilicon gate, a gate oxide layer and silicon nitride sidewalls, the gate oxide layer is disposed between the polysilicon gate and the second conductive type body region , the silicon nitride spacers are disposed on both sides of the polysilicon gate.

In the embodiment of the present invention, the above-mentioned LDMOS device further includes: a substrate electrode and a metal electrode, the substrate electrode is connected to the source region, and the metal electrode is disposed on the substrate electrode, the source region, The drain region and the surface of the polysilicon gate.

Another aspect of the present invention provides a method for manufacturing an LDMOS device of silicon carbide and silicon heterojunction, including:

Perform ion implantation into the first conductivity type well region of the silicon substrate;

Form a trench above the first conductivity type well region, and epitaxially grow silicon carbide inside and outside the trench to form a silicon carbide drift region;

A second conductivity type buried layer is formed in the vertical region adjacent to the silicon carbide drift region, and a second conductivity type body region is formed in the lateral region adjacent to the silicon carbide drift region;

A gate structure and a source region are formed on the surface of the second conductive type body region, and a drain region is formed on the surface of the silicon carbide drift region.

In the embodiment of the present invention, the ion implantation into the first conductive type well region of the silicon substrate includes: selecting a P-type silicon substrate, and injecting N-type ions into a predetermined area of the P-type silicon substrate to form an N-type well district.

In the embodiment of the present invention, forming a trench above the first conductive type well region, epitaxially growing silicon carbide inside and outside the trench to form a silicon carbide drift region includes: etching the silicon substrate, A trench is formed above the well region; a chemical vapor deposition method is used to epitaxially grow first conductive type ion-doped silicon carbide inside and outside the trench to form a first conductive type ion-doped silicon carbide drift region; in the first conductive type Undoped silicon carbide is epitaxially grown on the surface of the ion-doped silicon carbide drift region to form an undoped silicon carbide transition region.

In the embodiment of the present invention, forming a gate structure on the surface of the second conductivity type body region includes: using a thermal oxidation method to form a gate oxide layer on the surface of the second conductivity type body region; depositing polysilicon on the surface of the gate oxide layer to form polysilicon Gate; deposit silicon nitride on the surface of the polysilicon gate, etch the silicon nitride, and retain the silicon nitride on both sides of the polysilicon gate to form silicon nitride sidewalls.

In an embodiment of the present invention, the above-mentioned manufacturing method of a silicon carbide and silicon heterojunction LDMOS device further includes: forming a first conductivity type accumulation region between the silicon carbide drift region and the second conductivity type body region.

In the embodiment of the present invention, the ion doping concentration of the silicon carbide drift region is 1×10 ¹⁶ ~1×10 ¹⁷ cm ^-3 , and the ion doping concentration of the second conductive type buried layer is 3×10 ¹⁷ ~ 6×10 ¹⁷ cm ^-3 , and the ion doping concentration of the second conductivity type body region is 1×10 ¹⁷ ~5×10 ¹⁷ cm ^-3 .

The present invention also provides a power chip, which includes the above-mentioned LDMOS device of silicon carbide and silicon heterojunction.

The present invention improves the traditional LDMOS structure. The drift area and the drain area are made of silicon carbide material, and a buried layer is provided under the body area and the silicon carbide drift area, so that the drift area and the buried layer form an interface area between the silicon carbide and the buried layer in the longitudinal direction. Heterojunction of silicon, and the heterojunction of silicon carbide and silicon is formed in the interface area where the drift region and the body region are connected laterally, that is, a vertical and horizontal double heterojunction is formed, which increases the breakdown voltage of the device and increases the load capacity. Carrier mobility, thereby reducing the on-resistance; since the drain and drift regions of LDMOS are the main voltage-resistant regions of the device, silicon carbide (SiC) has high breakdown field strength characteristics, so the drift region and drain region of the silicon carbide material It can significantly improve the breakdown voltage and long-term reliability of the device.

Description of drawings

The drawings are used to provide a further understanding of the embodiments of the present invention, and constitute a part of the description. Together with the following specific embodiments, they are used to explain the embodiments of the present invention, but do not constitute a limitation to the embodiments of the present invention. In the attached picture:

Figure 1 is a schematic structural diagram of an LDMOS device with silicon carbide and silicon heterojunction provided in Embodiment 1 of the present invention;

Figure 2 is a schematic structural diagram of an LDMOS device with silicon carbide and silicon heterojunction provided in Embodiment 2 of the present invention;

Figure 3 is a flow chart of a manufacturing method of a silicon carbide and silicon heterojunction LDMOS device provided by an embodiment of the present invention;

Figure 4a is a schematic structural diagram of a well region formed in the manufacturing method provided by an embodiment of the present invention;

Figure 4b is a schematic structural diagram of the silicon carbide drift region formed in the manufacturing method provided by the embodiment of the present invention;

Figure 4c is a schematic structural diagram of the buried layer and body region formed in the manufacturing method provided by the embodiment of the present invention;

Figure 4d is a schematic structural diagram of an LDMOS device formed by the manufacturing method provided by an embodiment of the present invention.

Explanation of reference signs

101-P type silicon substrate, 102-N type well region, 103-P type buried layer, 104-P type body region,

105a-N-type ion doped silicon carbide drift region, 105b-undoped silicon carbide transition region,

106-N-type accumulation area, 107-polysilicon gate, 108-gate oxide layer, 109-silicon nitride sidewall,

110-substrate electrode, 111-source region, 112-drain region, 113-metal electrode.

Detailed ways

Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described here are only used to illustrate and explain the present invention, and are not intended to limit the present invention.

In the description of this article, it needs to be understood that the terms "center", "vertical", "horizontal", "upper", "lower", "front", "back", "left", "right", "top" ", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply what is meant. Devices or elements must have a specific orientation, be constructed and operate in a specific orientation and therefore are not to be construed as limiting. In this article, unless otherwise explicitly stipulated and limited, terms such as "connected", "connected" and "connected" should be understood in a broad sense. For example, it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be two The connection within a structure or region can also be the interaction between two structures or regions. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

Furthermore, the terms “first”, “second”, “third”, etc. are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of indicated technical features. Therefore, features defined as "first" and "second" may explicitly or implicitly include one or more of these features.

The embodiment of the present invention provides a silicon carbide and silicon heterojunction LDMOS device, including: a silicon substrate, a first conductivity type (N) well region, a second conductivity type (P) buried layer, a second conductivity type (P) ) body region, first conductivity type (N) drift region, source region, drain region and gate structure. The materials of the second conductivity type buried layer and the second conductivity type body region are both silicon, and the materials of the first conductivity type drift region and the drain region are both silicon carbide. The first conductivity type drift region and the second conductivity type buried layer are vertically connected to form a heterojunction of silicon carbide and silicon in the vertically connected interface region in the conductive state; the first conductivity type drift region and the second conductivity type The body regions are laterally connected to form a heterojunction between silicon carbide and silicon in the laterally connected interface region in the conductive state. The present invention improves the traditional LDMOS structure. The drift area and the drain area are made of silicon carbide material, and a buried layer is provided under the body area and the silicon carbide drift area, so that the drift area and the buried layer form an interface area between the silicon carbide and the buried layer in the longitudinal direction. Heterojunction of silicon, and the heterojunction of silicon carbide and silicon is formed in the interface area where the drift region and the body region are connected laterally, that is, a vertical and horizontal double heterojunction is formed, which increases the breakdown voltage of the device and increases the load capacity. Carrier mobility, thereby reducing the on-resistance; since the drain and drift regions of LDMOS are the main voltage-resistant regions of the device, silicon carbide (SiC) has high breakdown field strength characteristics, so the drift region and drain region of the silicon carbide material It can significantly improve the breakdown voltage and long-term reliability of the device.

The above-mentioned LDMOS devices include N-type LDMOS devices (NLDMOS for short) and P-type LDMOS devices (PLDMOS for short). In the above description, the first conductivity type and the second conductivity type refer to two carrier types, namely P type (carriers are holes) and N type (carriers are electrons). In the above-mentioned LDMOS device, if the silicon substrate is a P-type silicon substrate, the first conductivity type is N-type, the second conductivity type is P-type, and the formed semiconductor device is NLDMOS; if the silicon substrate is N-type silicon If the substrate is used, the first conductivity type is P type, the second conductivity type is N type, and the formed semiconductor device is PLDMOS. The following uses the NLDMOS device as an example to elaborate on the technical solution of the present invention.

FIG. 1 is a schematic structural diagram of a silicon carbide and silicon heterojunction LDMOS device provided in Embodiment 1 of the present invention. As shown in Figure 1, the LDMOS device improved in this embodiment includes a P-type silicon substrate 101, an N-type well region 102, a P-type buried layer 103, a P-type body region 104, an N-type drift region, a source region 111, a drain region The materials of region 112 and gate structure, N-type well region 102, P-type buried layer 103 and P-type body region 104 are all silicon, and the materials of N-type drift region and drain region 112 are all silicon carbide (SiC). The N-type drift region is vertically connected to the P-type buried layer 103. In the conductive state, the interface area between the N-type drift region and the P-type buried layer 103 forms a heterojunction between silicon carbide and silicon; the N-type drift region Laterally connected to the P-type body region 104, in the conductive state, the interface region of the N-type drift region and the P-type body region 104 laterally connected forms a heterojunction between silicon carbide and silicon. This LDMOS device uses the drift region and drain region of silicon carbide material to form vertical and horizontal double heterojunctions, which can increase the breakdown voltage of the device, increase carrier mobility, and thereby reduce on-resistance.

In this embodiment, the N-type drift region includes an N-type ion-doped silicon carbide drift region 105a and an undoped silicon carbide transition region 105b. The N-type ion-doped silicon carbide drift region 105a is vertically connected to the P-type buried layer 103 and laterally connected to the P-type body region 104; the undoped silicon carbide transition region 105b is located in the N-type ion-doped silicon carbide The upper surface of the drift region 105a is laterally connected to the P-type body region 104. The drift region of the LDMOS device in this embodiment has a two-layer structure. The lower layer is N-type doped SiC, which serves as a conductive channel in the drift region. The upper layer is undoped SiC, which serves as a buffer zone and a withstand voltage zone. The SiC material has a critical breakdown electric field. The strength is ten times that of silicon material. Using SiC material as the buffer zone and voltage withstand zone can avoid the need to set up a field plate when using Si material as the drift zone (using the field plate to increase the breakdown voltage), and the introduced Si-SiO ₂ interface It will deteriorate the long-term reliability of the device, that is, the undoped SiC drift region can significantly improve the long-term reliability of the device.

In this embodiment, the gate structure includes a polysilicon gate 107, a gate oxide layer 108, and silicon nitride (Si ₃ N ₄ ) spacers 109. The gate oxide layer 108 is disposed between the polysilicon gate 107 and the P-type body region 104 , silicon nitride spacers 109 are provided on both sides of the polysilicon gate 107 . The above-mentioned LDMOS device also includes a substrate electrode 110 and a metal electrode 113. The substrate electrode 110 is connected to the source region 111. The metal electrode 113 is disposed on the surfaces of the substrate electrode 110, the source region 111, the drain region 112 and the polysilicon gate 107. This LDMOS device uses polysilicon gate and sidewall technology that is compatible with conventional CMOS devices to form silicon nitride sidewalls for the gate. The silicon nitride sidewalls are used to introduce local stress in the channel area to improve the carrier mobility of the device.

FIG. 2 is a schematic structural diagram of an LDMOS device with silicon carbide and silicon heterojunction provided in Embodiment 2 of the present invention. As shown in Figure 2, the LDMOS device improved in this embodiment includes a P-type silicon substrate 101, an N-type well region 102, a P-type buried layer 103, a P-type body region 104, an N-type drift region, and an N-type accumulation region 106 , source region 111, drain region 112 and gate structure. The N-type accumulation region 106 is provided between the N-type drift region and the gate structure. The N-type well region 102, the P-type buried layer 103 and the P-type body region 104 are all made of silicon. The N-type drift region and the drain region 112 are all made of silicon. The materials are all silicon carbide. The N-type drift region is vertically connected to the P-type buried layer 103. In the conductive state, the interface region between the N-type drift region and the P-type buried layer 103 is vertically connected to form a heterojunction between silicon carbide and silicon. The N-type drift region and the P-type body region 104 are laterally connected. In the conductive state, the interface region between the N-type drift region and the P-type body region 104 is laterally connected to form a heterojunction between silicon carbide and silicon. Among them, the N-type drift region includes an N-type ion-doped silicon carbide drift region 105a and an undoped silicon carbide transition region 105b. The N-type ion-doped silicon carbide drift region 105a is vertically connected to the P-type buried layer 103. And is laterally connected to the P-type body region 104; the undoped silicon carbide transition region 105b is located on the upper surface of the N-type ion-doped silicon carbide drift region 105a, and is laterally connected to the P-type body region 104. The gate structure includes a polysilicon gate 107, a gate oxide layer 108, and a silicon nitride spacer 109. The gate oxide layer 108 is disposed between the polysilicon gate 107 and the P-type body region 104, and the silicon nitride spacer 109 is disposed on the polysilicon gate. pole 107 on both sides. The LDMOS device also includes a substrate electrode 110 and a metal electrode 113. The substrate electrode 110 is connected to the source region 111. The metal electrode 113 is disposed on the surfaces of the substrate electrode 110, the source region 111, the drain region 112 and the polysilicon gate 107.

Compared with Embodiment 1, Embodiment 2 adds an N-type accumulation area 106 . The N-type accumulation region 106 is located between the N-type ion-doped silicon carbide drift region 105a and the polysilicon gate 107. As an electron accumulation layer between the two, it can greatly improve the conductivity of the device and thereby reduce the on-resistance of the device. .

The manufacturing method of the above-mentioned silicon carbide and silicon heterojunction LDMOS device will be described in detail below.

As shown in Figure 3, the manufacturing method of a silicon carbide and silicon heterojunction LDMOS device provided by an embodiment of the present invention includes the following steps:

Step 201, perform ion implantation into the silicon substrate into a first conductive type well region.

Taking the NLDMOS device as an example, a P-type silicon substrate is selected, and N-type ions (ion doping concentration is 3×10 ¹⁶ ~1.5×10 ¹⁷ cm ^-3 ) are injected into a predetermined area of the P-type silicon substrate 101 to form N Well region 102 is formed to obtain a structure as shown in Figure 4a.

Step 202: Form a trench above the first conductivity type well region, and epitaxially grow silicon carbide inside and outside the trench to form a silicon carbide drift region.

Specifically, the P-type silicon substrate 101 is etched to form a trench above the N-type well region 102; a chemical vapor deposition method is used to epitaxially grow N-type ion-doped silicon carbide (ion doping concentration: is 1×10 ¹⁶ ~1×10 ¹⁷ cm ^-3 ), forming an N-type ion-doped silicon carbide drift region 105a; epitaxially growing undoped silicon carbide on the surface of the N-type ion-doped silicon carbide drift region 105a, The filled silicon carbide is polished by chemical mechanical polishing method to form an undoped silicon carbide transition region 105b, and the structure shown in Figure 4b is obtained.

Step 203: Form a second conductive type buried layer in the vertical region adjacent to the silicon carbide drift region, and form a second conductive type body region in the lateral region adjacent to the silicon carbide drift region.

Specifically, an ion implantation method is used to implant P-type ions in a predetermined buried layer region to form the P-type buried layer 103, and P-type ions are implanted in a predetermined body region to form a P-type body region 104, resulting in a structure as shown in Figure 4c. Among them, the ion doping concentration of the P-type buried layer 103 is 3×10 ¹⁷ ~6×10 ¹⁷ cm ^-3 , and the ion doping concentration of the P-type body region 104 is 1×10 ¹⁷ ~5×10 ¹⁷ cm ^-3 .

Step 204: Form a gate structure and a source region on the surface of the second conductive type body region, and form a drain region on the surface of the silicon carbide drift region.

Specifically, a thermal oxidation method is used to form a gate oxide layer 108 of a predetermined length on the surface of the P-type body region 104, a chemical vapor deposition (CVD) method is used to deposit polysilicon on the surface of the gate oxide layer 108, and it is heavily doped with ions ( The doping concentration is 1×10 ¹⁹ ~1×10 ²⁰ cm ^-3 ) to form a polysilicon gate 107. Silicon nitride is deposited on the surface of the polysilicon gate 107, and the silicon nitride is etched to retain the polysilicon gate electrodes on both sides. Silicon nitride is used to form silicon nitride sidewalls 109, resulting in a gate structure as shown in Figure 4d.

P-type ions (ion doping concentration is 1×10 ¹⁹ ~1×10 ²⁰ cm ^-3 ) are implanted into a predetermined substrate electrode area on the surface of the P-type body region 104 to form the substrate electrode 110 ; The source region is implanted with N-type ions (ion doping concentration is 1×10 ¹⁹ ~1×10 ²⁰ cm ^-3 ) to form the source region 111; on the surface of the silicon carbide drift region (undoped silicon carbide transition region 105b), a predetermined The drain region is implanted with N-type ions (ion doping concentration is 1×10 ¹⁹ ~1×10 ²⁰ cm ^-3 ) to form the drain region 112; in the substrate electrode 110, the source region 111, the drain region 112 and the polysilicon gate 107 Metal is deposited on the surface to form a metal electrode 113, resulting in a structure as shown in Figure 4d.

In the above steps, after forming the substrate electrode 110, the source region 111, the drain region 112 and the metal electrode 113, chemical vapor deposition (CVD) can also be used to deposit silicon nitride on the surface of the polysilicon gate 107 and etch it. Etching and planarization are performed to retain the silicon nitride on both sides of the polysilicon gate to form silicon nitride sidewalls 109.

In another embodiment, after the silicon carbide drift region is formed, N-type ions (ion doping concentration is 1×10 ¹⁶ ~5× 10 ¹⁶ cm ^-3 ) to form the N-type accumulation region 106. After the N-type accumulation region 106 is formed, the P-type buried layer 103 and the P-type body region 104 are formed to obtain the LDMOS device structure as shown in Figure 2.

The above-mentioned manufacturing method of LDMOS devices forms a heterojunction between SiC and Si materials by epitaxially extending SiC materials on a silicon substrate. The silicon substrate can be integrated with other mature silicon material devices on the same substrate, which can improve device integration. ,cut costs. The drain region and drift region of the device are made on epitaxial SiC material. The substrate, accumulation region, body region, source region, channel region, gate and gate oxide layer are made on Si substrate material. SiC material is used to make the drain region. The region and drift region can increase the breakdown voltage of the device, increase the carrier mobility, and reduce the on-resistance. The above method uses P-type buried layer technology under the drift region to modulate the electric field distribution in the drift region through P-type doping under the drift region, improve device breakdown voltage, and suppress parasitic transistor conduction; and, the method is compatible with conventional CMOS devices Polysilicon gate and spacer technology, while using Si ₃ N ₄ gate spacers can introduce local stress in the channel area to improve device carrier mobility.

The present invention also provides a power chip, which includes the above-mentioned LDMOS device of silicon carbide and silicon heterojunction. The power chip has the advantages of high breakdown voltage, low on-resistance, and good long-term reliability.

Although the preferred embodiments of the present invention have been described, those skilled in the art will be able to make additional changes and modifications to these embodiments once the basic inventive concepts are apparent. Therefore, it is intended that the appended claims be construed to include the preferred embodiments and all changes and modifications that fall within the scope of the invention.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the invention. In this way, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims (10)

1. An LDMOS device of silicon carbide and silicon heterojunction, including: a silicon substrate, a first conductivity type well region, a second conductivity type body region, a first conductivity type drift region, a source region, a drain region and a gate electrode The structure is characterized in that it also includes: a second conductive type buried layer; The material of the second conductivity type buried layer and the second conductivity type body region is silicon, and the material of the first conductivity type drift region and the drain region is silicon carbide; The first conductivity type drift region is longitudinally connected to the second conductivity type buried layer to form a heterojunction of silicon carbide and silicon in the longitudinally connected interface region when in the conductive state; The first conductive type drift region and the second conductive type body region are laterally connected to form a heterojunction of silicon carbide and silicon in the laterally connected interface region in the conductive state. 2. The LDMOS device of silicon carbide and silicon heterojunction according to claim 1, characterized in that the first conductivity type drift region includes: a first conductivity type ion-doped silicon carbide drift region and an undoped silicon carbide drift region. Silicon carbide transition zone; The first conductivity type ion-doped silicon carbide drift region is longitudinally connected to the second conductivity type buried layer, and is laterally connected to the second conductivity type body region; The undoped silicon carbide transition region is located on the surface of the first conductivity type ion-doped silicon carbide drift region and is laterally connected to the second conductivity type body region. 3. The LDMOS device of silicon carbide and silicon heterojunction according to claim 1, characterized in that the gate structure includes: a polysilicon gate, a gate oxide layer and a silicon nitride sidewall, the gate oxide layer Disposed between the polysilicon gate and the second conductive type body region, the silicon nitride spacers are disposed on both sides of the polysilicon gate. 4. The LDMOS device of silicon carbide and silicon heterojunction according to claim 3, further comprising: a substrate electrode and a metal electrode, the substrate electrode is connected to the source region, and the metal electrode Electrodes are provided on the surfaces of the substrate electrode, the source region, the drain region and the polysilicon gate. 5. A method for manufacturing a silicon carbide and silicon heterojunction LDMOS device, which is characterized by including: Perform ion implantation into the first conductivity type well region of the silicon substrate; Form a trench above the first conductivity type well region, and epitaxially grow silicon carbide inside and outside the trench to form a silicon carbide drift region; A second conductivity type buried layer is formed in the vertical region adjacent to the silicon carbide drift region, and a second conductivity type body region is formed in the lateral region adjacent to the silicon carbide drift region. The silicon carbide drift region and the second conductivity type buried layer are in The vertically connected interface region forms a heterojunction between silicon carbide and silicon, and the silicon carbide drift region and the second conductive type body region form a transversely connected interface region forming a heterojunction between silicon carbide and silicon; A gate structure and a source region are formed on the surface of the second conductive type body region, and a drain region of silicon carbide material is formed on the surface of the silicon carbide drift region. 6. The manufacturing method of an LDMOS device of silicon carbide and silicon heterojunction according to claim 5, characterized in that the ion implantation of the first conductivity type well region into the silicon substrate includes: A P-type silicon substrate is selected, and N-type ions are injected into a predetermined area of the P-type silicon substrate to form an N-type well region. 7. The method for manufacturing a silicon carbide and silicon heterojunction LDMOS device according to claim 5, wherein a trench is formed above the first conductive type well region, and silicon carbide is epitaxially grown inside and outside the trench. , forming a silicon carbide drift region, including: Etch the silicon substrate to form a trench above the first conductivity type well region; Using a chemical vapor deposition method to epitaxially grow silicon carbide doped with first conductive type ions inside and outside the trench to form a drift region of silicon carbide doped with first conductive type ions; Undoped silicon carbide is epitaxially grown on the surface of the first conductive type ion-doped silicon carbide drift region to form an undoped silicon carbide transition region. 8. The method for manufacturing a silicon carbide and silicon heterojunction LDMOS device according to claim 5, wherein forming a gate structure on the surface of the second conductivity type body region includes: Using thermal oxidation method to form a gate oxide layer on the surface of the second conductivity type body region; Deposit polysilicon on the surface of the gate oxide layer to form a polysilicon gate; Silicon nitride is deposited on the surface of the polysilicon gate, and the silicon nitride is etched to retain the silicon nitride on both sides of the polysilicon gate to form silicon nitride sidewalls. 9. The method for manufacturing a silicon carbide and silicon heterojunction LDMOS device according to claim 5, wherein the ion doping concentration of the silicon carbide drift region is 1×10 ¹⁶ ~ 1×10 ¹⁷ cm ^{- 3.} The ion doping concentration of the second conductivity type buried layer is 3×10 ¹⁷ ~6×10 ¹⁷ cm ^-3 , and the ion doping concentration of the second conductivity type body region is 1×10 ¹⁷ ~5× 10 ¹⁷ cm ^-3 . 10. A power chip, characterized by comprising the LDMOS device of silicon carbide and silicon heterojunction according to any one of claims 1-4.