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CN107994026A - A kind of technique of the protective side wall in the etching of high-aspect-ratio raceway groove hole - Google Patents

A kind of technique of the protective side wall in the etching of high-aspect-ratio raceway groove hole Download PDF

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Publication number
CN107994026A
CN107994026A CN201711140438.XA CN201711140438A CN107994026A CN 107994026 A CN107994026 A CN 107994026A CN 201711140438 A CN201711140438 A CN 201711140438A CN 107994026 A CN107994026 A CN 107994026A
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CN
China
Prior art keywords
raceway groove
groove hole
side wall
protective film
stacked structure
Prior art date
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Application number
CN201711140438.XA
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Chinese (zh)
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CN107994026B (en
Inventor
方振
王猛
刘隆冬
苏恒
朱喜峰
陈保友
戴绍龙
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Priority to CN201711140438.XA priority Critical patent/CN107994026B/en
Publication of CN107994026A publication Critical patent/CN107994026A/en
Application granted granted Critical
Publication of CN107994026B publication Critical patent/CN107994026B/en
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The technique of protective side wall, comprises the following steps in being etched the present invention provides a kind of high-aspect-ratio raceway groove hole:Substrate stacked structure is provided;Etching forms raceway groove hole on the substrate stacked structure;Filling is deposited in the raceway groove hole and forms raceway groove hole side wall stacked structure function film;Protective film is deposited on the surface of the side wall stacked structure, and make it that the thickness in thickness ratio raceway groove bottom hole portion of the protective film at the top of raceway groove hole is big.The thickness in thickness ratio raceway groove bottom hole portion of the present invention process due to protective film at the top of raceway groove hole is big;So that during follow-up dry etching; protective film of the protective film at top particularly at the upper opening of raceway groove hole is more resistant to damage; in the end of a period of dry etching; remain to the residue of protective film; so as to protect the stacked structure function film of raceway groove hole side wall from the bombardment damage of plasma; the yield of raceway groove hole etching technics processing procedure is improved, improves the electric property of device.

Description

A kind of technique of the protective side wall in the etching of high-aspect-ratio raceway groove hole
Technical field
The present invention relates to improve raceway groove hole etching in field of semiconductor manufacture, more particularly to a kind of 3D NAND flash memory structures The method of technique.
Background technology
With the development of plane flash memories, the production technology of semiconductor achieves huge progress.But recently Several years, the development of plane flash memory encountered various challenges:Physics limit, the existing developing technique limit and storage electron density Limit etc..In this context, to solve the difficulty that runs into of planar flash memory and most ask being produced into for lower unit storage unit This, a variety of three-dimensional (3D) flash memories structures are come into being, such as 3D NOR (3D or non-) flash memories and 3D NAND (3D with non-) flash memory.At present, in the evolution of 3D NAND, with the increase of stacking number, prepared to etching, depositing etc. Technique proposes the requirement of higher.
Wherein, in the etching technics of high-aspect-ratio raceway groove hole, generally use is protected along the technique of side wall deposition protective film Side wall, for example, in the manufacturing process of 3D NAND, in order to form raceway groove, after channel thin-film deposition, bottom source should be by Etching is opened, so as to cause in the etching technics of this high-aspect-ratio, it is necessary to deposit some kinds of protective film to protect side Wall.
In high aspect ratio technique, top protective film is easier the damage that is etched than bottom protective film;Such as showing for Fig. 1 Shown in micro- photo.For another example the schematic diagram of Fig. 2 a, it is shown that the raceway groove hole functional memory cell film 2 of stacked structure 1 deposits one above Layer protective film 3, the schematic diagram after dry etching is as shown in Figure 2 b, it is seen then that protective film at the top-open of raceway groove hole by Damage, functional memory cell film is exposed, and protective film above is more serious than following damage.Just due to this reason, Plasma is by the function film of damaged memory unit, such as makes to produce room in function film, after this causes wet etching Performance deteriorates, and may cause the failure of electrical property.
Therefore, the depositing operation of protective film how is improved, so that the raceway groove hole for preparing higher yield is this area skill always Art personnel endeavour the direction of research.
The content of the invention
It is an object of the invention to provide a kind of technique of protective side wall in being etched in high-aspect-ratio raceway groove hole, by protecting The improvement of cuticula depositing operation, overcomes the drawbacks described above of the prior art, so as to improve the technique of raceway groove hole etching;And then improve ditch Road hole process rate.
To achieve these goals, the technical solution adopted by the present invention is as follows:
The technique of protective side wall, comprises the following steps in a kind of high-aspect-ratio raceway groove hole etching:
Substrate stacked structure is provided;
Etching forms raceway groove hole on the substrate stacked structure;
Filling is deposited in the raceway groove hole and forms raceway groove hole side wall stacked structure function film;
Protective film is deposited on the surface of the side wall stacked structure, and causes thickness of the protective film at the top of raceway groove hole Thickness than raceway groove bottom hole portion is big.
Further, the transition gradual from the top to the bottom of the thickness of the protective film causes in raceway groove hole longitudinal cross-section one side Protective film is in back taper.
Further, depositing operation is controlled so that the thickness of thickness of the protective film at the top of raceway groove hole to raceway groove bottom hole portion Degree is of substantially equal in the thickness of the remaining protective film after dry etching.
Further, the substrate stacked structure includes the spaced silicon oxide-silicon nitride heap that substrate surface is formed Laminate film (O/N) and hard mask (HM) above.
Further, the raceway groove hole side wall stacked structure function film is included as barrier layer, accumulation layer and tunnel layer Oxidenitride oxide structure (ONO).
Compared with prior art, the beneficial effects are mainly as follows:
When depositing protective film, since the thickness in thickness ratio raceway groove bottom hole portion of the protective film at the top of raceway groove hole is big;So that During follow-up dry etching, the protective film of the protective film at top particularly at the upper opening of raceway groove hole is more resistant to damage, in dry etching End of a period, remain to the residue of protective film, thus protect the stacked structure function film of raceway groove hole side wall from plasma Hong Damage is hit, improves the yield of raceway groove hole etching technics processing procedure, improves the electric property of device.
Brief description of the drawings
By reading the detailed description of hereafter preferred embodiment, it is various other the advantages of and benefit it is common for this area Technical staff will be clear understanding.Attached drawing is only used for showing the purpose of preferred embodiment, and is not considered as to the present invention Limitation.And in whole attached drawing, identical component is denoted by the same reference numerals.In the accompanying drawings:
Fig. 1, the microphoto for the damage that is etched for protective film of the display in the prior art at the top of raceway groove hole;
Fig. 2 a, to show the layer protecting film that deposits above of raceway groove hole functional memory cell film of prior art stacked structure Structure diagram;
Fig. 2 b, to show that protective film of the protective film of the prior art after dry etching at the upper opening of raceway groove hole is etched The structure diagram of damage;
Fig. 3 a, to show deposit above one layer of raceway groove hole functional memory cell film of embodiment of the present invention stacked structure The structure diagram of protective film;
Fig. 3 b, to show protective film of the protective film of embodiment of the present invention after dry etching at the upper opening of raceway groove hole Be not etched the structure diagram of damage.
Embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although this public affairs is shown in attached drawing The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here The mode of applying is limited.Conversely, there is provided these embodiments are to be able to be best understood from the disclosure, and can be by this public affairs The scope opened completely is communicated to those skilled in the art.
For clarity, whole features of practical embodiments are not described.In the following description, it is not described in detail known function And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments In hair, it is necessary to a large amount of implementation details are made to realize the specific objective of developer, such as according to related system or related business Limitation, another embodiment is changed into by one embodiment.Additionally, it should think that this development is probably complicated and expends Time, but it is only to those skilled in the art routine work.
More specifically description is of the invention by way of example referring to the drawings in the following passage.Will according to following explanation and right Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is using very simplified form and using non- Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
According to the embodiment of the present invention, there is provided the technique of protective side wall in a kind of high-aspect-ratio raceway groove hole etching, including Following steps:
S100, referring to Fig. 3 a, there is provided substrate stacked structure;The substrate stacked structure includes the mutual of substrate surface formation Silicon oxide-silicon nitride stacked film (O/N) 100 spaced apart and hard mask (HM) 200 above;
S200, etching forms raceway groove hole 300 on the substrate stacked structure;
S300, in the raceway groove hole deposit filling form raceway groove hole side wall stacked structure function film 400;The raceway groove Hole side wall stacked structure function film includes the oxidenitride oxide structure as barrier layer, accumulation layer and tunnel layer (ONO);
S400, protective film 500 is deposited on the surface of the side wall stacked structure, and the protective film is pushed up in raceway groove hole The thickness in the thickness ratio raceway groove bottom hole portion in portion is big;The transition gradual from the top to the bottom of the thickness of the protective film causes in raceway groove hole The protective film of longitudinal cross-section one side is in back taper, and controls depositing operation so that thickness of the protective film at the top of raceway groove hole Spend to thickness of substantially equal, protection after dry etching in the thickness of the remaining protective film after dry etching in raceway groove bottom hole portion The form of film is as shown in Figure 3b.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto, Any one skilled in the art the invention discloses technical scope in, the change or replacement that can readily occur in, It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim Subject to enclosing.

Claims (5)

1. the technique of protective side wall in a kind of high-aspect-ratio raceway groove hole etching, it is characterised in that comprise the following steps:
Substrate stacked structure is provided;
Etching forms raceway groove hole on the substrate stacked structure;
Filling is deposited in the raceway groove hole and forms raceway groove hole side wall stacked structure function film;
Protective film is deposited on the surface of the side wall stacked structure, and causes thickness ratio ditch of the protective film at the top of raceway groove hole The thickness in road bottom hole portion is big.
2. the technique of protective side wall as claimed in claim 1, it is characterised in that the thickness of the protective film is from the top to the bottom Gradual transition make it that the protective film in raceway groove hole longitudinal cross-section one side is in back taper.
3. the technique of protective side wall as claimed in claim 1, it is characterised in that control depositing operation so that the protective film Thickness of the thickness to raceway groove bottom hole portion at the top of raceway groove hole is of substantially equal in the thickness of the remaining protective film after dry etching.
4. the technique of the protective side wall as described in claim 1-3 any one, it is characterised in that the substrate stacked structure bag Include the spaced silicon oxide-silicon nitride stacked film (O/N) of substrate surface formation and hard mask (HM) above.
5. the technique of the protective side wall as described in claim 1-3 any one, it is characterised in that raceway groove hole side wall stacks Structure function film includes the oxidenitride oxide structure (ONO) as barrier layer, accumulation layer and tunnel layer.
CN201711140438.XA 2017-11-16 2017-11-16 Process for protecting side wall in etching high depth-to-width ratio trench hole Active CN107994026B (en)

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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109524415A (en) * 2018-11-14 2019-03-26 长江存储科技有限责任公司 The manufacturing method and three-dimensional storage of three-dimensional storage
CN110808251A (en) * 2019-11-12 2020-02-18 中国科学院微电子研究所 A kind of channel preparation method of three-dimensional memory
WO2020061810A1 (en) * 2018-09-26 2020-04-02 Yangtze Memory Technologies Co., Ltd. Step coverage improvement for memory channel layer in 3d nand memory
CN111769119A (en) * 2020-06-08 2020-10-13 长江存储科技有限责任公司 Memory manufacturing method and memory
CN113725228A (en) * 2021-08-26 2021-11-30 长江存储科技有限责任公司 Three-dimensional memory and manufacturing method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1197414A (en) * 1997-09-25 1999-04-09 Sony Corp Plasma etching method for silicon-oxide based insulating film
CN1723549A (en) * 2002-10-11 2006-01-18 兰姆研究有限公司 Method for plasma etching performance enhancement
CN103972153A (en) * 2013-01-31 2014-08-06 华邦电子股份有限公司 Contact hole plug manufacture method
CN104766866A (en) * 2015-04-10 2015-07-08 武汉新芯集成电路制造有限公司 3D flash memory channel manufacturing method
CN106298784A (en) * 2015-05-29 2017-01-04 旺宏电子股份有限公司 Memory element and manufacturing method thereof
CN107316807A (en) * 2016-04-22 2017-11-03 中芯国际集成电路制造(上海)有限公司 The preparation method of semiconductor devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1197414A (en) * 1997-09-25 1999-04-09 Sony Corp Plasma etching method for silicon-oxide based insulating film
CN1723549A (en) * 2002-10-11 2006-01-18 兰姆研究有限公司 Method for plasma etching performance enhancement
CN103972153A (en) * 2013-01-31 2014-08-06 华邦电子股份有限公司 Contact hole plug manufacture method
CN104766866A (en) * 2015-04-10 2015-07-08 武汉新芯集成电路制造有限公司 3D flash memory channel manufacturing method
CN106298784A (en) * 2015-05-29 2017-01-04 旺宏电子股份有限公司 Memory element and manufacturing method thereof
CN107316807A (en) * 2016-04-22 2017-11-03 中芯国际集成电路制造(上海)有限公司 The preparation method of semiconductor devices

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020061810A1 (en) * 2018-09-26 2020-04-02 Yangtze Memory Technologies Co., Ltd. Step coverage improvement for memory channel layer in 3d nand memory
US10707221B2 (en) 2018-09-26 2020-07-07 Yangtze Memory Technologies Co., Ltd. Step coverage improvement for memory channel layer in 3D NAND memory
CN109524415A (en) * 2018-11-14 2019-03-26 长江存储科技有限责任公司 The manufacturing method and three-dimensional storage of three-dimensional storage
CN109524415B (en) * 2018-11-14 2021-03-30 长江存储科技有限责任公司 Manufacturing method of three-dimensional memory and three-dimensional memory
CN110808251A (en) * 2019-11-12 2020-02-18 中国科学院微电子研究所 A kind of channel preparation method of three-dimensional memory
CN111769119A (en) * 2020-06-08 2020-10-13 长江存储科技有限责任公司 Memory manufacturing method and memory
CN113725228A (en) * 2021-08-26 2021-11-30 长江存储科技有限责任公司 Three-dimensional memory and manufacturing method thereof
CN113725228B (en) * 2021-08-26 2023-08-08 长江存储科技有限责任公司 Three-dimensional memory and manufacturing method thereof

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