[go: up one dir, main page]

CN107994026B - Process for protecting side wall in etching high depth-to-width ratio trench hole - Google Patents

Process for protecting side wall in etching high depth-to-width ratio trench hole Download PDF

Info

Publication number
CN107994026B
CN107994026B CN201711140438.XA CN201711140438A CN107994026B CN 107994026 B CN107994026 B CN 107994026B CN 201711140438 A CN201711140438 A CN 201711140438A CN 107994026 B CN107994026 B CN 107994026B
Authority
CN
China
Prior art keywords
channel hole
protective film
etching
side wall
thickness
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201711140438.XA
Other languages
Chinese (zh)
Other versions
CN107994026A (en
Inventor
方振
王猛
刘隆冬
苏恒
朱喜峰
陈保友
戴绍龙
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yangtze Memory Technologies Co Ltd
Original Assignee
Yangtze Memory Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd
Priority to CN201711140438.XA priority Critical patent/CN107994026B/en
Publication of CN107994026A publication Critical patent/CN107994026A/en
Application granted granted Critical
Publication of CN107994026B publication Critical patent/CN107994026B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The invention provides a process for protecting a side wall in etching a trench hole with a high depth-to-width ratio, which comprises the following steps: providing a substrate stacking structure; etching and forming a channel hole on the substrate stacking structure; depositing and filling a functional film with a channel hole side wall stacking structure in the channel hole; and depositing a protective film on the surface of the side wall stacking structure, wherein the thickness of the protective film at the top of the channel hole is larger than that at the bottom of the channel hole. The thickness of the protective film at the top of the channel hole is larger than that at the bottom of the channel hole; during subsequent dry etching, the protective film on the top, particularly the protective film at the opening at the upper part of the channel hole, is more resistant to damage, and the protective film still remains at the end of the dry etching, so that the functional film of the stacking structure on the side wall of the channel hole is protected from being bombarded and damaged by plasma, the yield of the etching process of the channel hole is improved, and the electrical performance of the device is improved.

Description

Process for protecting side wall in etching high depth-to-width ratio trench hole
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a method for improving a channel hole etching process in a 3D NAND flash memory structure.
Background
With the development of the planar flash memory, the manufacturing process of the semiconductor has been greatly improved. In recent years, however, the development of planar flash memories has met with various challenges: physical limits, existing development technology limits, and storage electron density limits, among others. In this context, to solve the difficulties encountered by flat flash memories and to maximize the lower production cost of a unit cell, various three-dimensional (3D) flash memory structures, such as 3D NOR (3D NOR) flash memory and 3D NAND (3D NAND) flash memory, have come into force. At present, in the development process of 3D NAND, with the increase of the number of stacked layers, higher requirements are put forward on the preparation processes such as etching, deposition, and the like.
Among them, in the high aspect ratio channel hole etching process, a process of depositing a protective film along the sidewall is generally adopted to protect the sidewall, for example, in the 3D NAND manufacturing process, in order to form the channel, after the channel film is deposited, the bottom source should be etched and opened, so that in such a high aspect ratio etching process, some kind of protective film must be deposited to protect the sidewall.
In the high aspect ratio etching process, the top protective film is more easily damaged by etching than the bottom protective film; as shown in the micrograph of figure 1. Referring again to the schematic diagram of fig. 2a, which shows a protective film 3 deposited on the functional film 2 of the memory cell in the channel hole of the stacked structure 1, the schematic diagram after dry etching is shown in fig. 2b, it can be seen that the protective film at the opening above the channel hole has been damaged, the functional film of the memory cell has been exposed, and the upper protective film is more serious than the lower protective film. For this reason, the plasma damages the functional film of the memory cell, for example, generates voids in the functional film, which deteriorates the performance after wet etching and may cause failure of the electrical performance.
Therefore, how to improve the deposition process of the protective film to prepare a channel hole with higher yield has been the direction of research effort of those skilled in the art.
Disclosure of Invention
The invention aims to provide a process for protecting a side wall in etching a high-aspect-ratio trench hole, which overcomes the defects in the prior art by improving a deposition process of a protective film so as to improve the process for etching the trench hole; thereby increasing the yield of the channel hole process.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a process for protecting sidewalls in high aspect ratio trench hole etching, comprising the steps of:
providing a substrate stacking structure;
etching and forming a channel hole on the substrate stacking structure;
depositing and filling a functional film with a channel hole side wall stacking structure in the channel hole;
and depositing a protective film on the surface of the side wall stacking structure, wherein the thickness of the protective film at the top of the channel hole is larger than that at the bottom of the channel hole.
Further, the thickness of the protective film gradually transits from the top to the bottom so that the protective film on one side of the longitudinal section of the channel hole is in an inverted cone shape.
Further, the deposition process is controlled so that the thickness of the protective film at the top of the channel hole to the thickness of the protective film at the bottom of the channel hole are substantially equal to the thickness of the remaining protective film after the dry etching.
Further, the substrate stack structure comprises a silicon oxide-silicon nitride stack film (O/N) formed on the surface of the substrate and spaced apart from each other, and a Hard Mask (HM) thereon.
Further, the channel hole sidewall stack structure functional film includes an oxide-nitride-oxide structure (ONO) serving as a blocking layer, a memory layer, and a tunneling layer.
Compared with the prior art, the invention has the following beneficial effects:
when the protective film is deposited, the thickness of the protective film at the top of the channel hole is larger than that at the bottom of the channel hole; during subsequent dry etching, the protective film on the top, particularly the protective film at the opening at the upper part of the channel hole, is more resistant to damage, and the protective film still remains at the end of the dry etching, so that the functional film of the stacking structure on the side wall of the channel hole is protected from being bombarded and damaged by plasma, the yield of the etching process of the channel hole is improved, and the electrical performance of the device is improved.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a photomicrograph showing the etching damage of a protective film on the top of a channel hole in the prior art;
FIG. 2a is a schematic diagram showing a structure of a protective film deposited on a functional film of a trench hole memory cell in a prior art stacked structure;
FIG. 2b is a schematic structural diagram showing the damage of the protective film at the upper opening of the trench hole after dry etching;
FIG. 3a is a schematic structural diagram illustrating a protective film deposited on a functional film of a trench hole memory cell in a stacked structure according to an embodiment of the present invention;
fig. 3b is a schematic structural diagram showing that the protective film at the upper opening of the trench hole is not damaged by etching after the protective film is subjected to dry etching according to the embodiment of the present invention.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the interest of clarity, not all features of an actual implementation are described. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific details must be set forth in order to achieve the developer's specific goals, such as compliance with system-related and business-related constraints, which will vary from one implementation to another. Moreover, it will be appreciated that such a development effort might be complex and time-consuming, but would nevertheless be a routine undertaking for those of ordinary skill in the art.
The invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
According to an embodiment of the present invention, a process for protecting sidewalls in high aspect ratio trench hole etching is provided, which includes the following steps:
s100, referring to fig. 3a, providing a substrate stack structure; the substrate stack structure comprises a silicon oxide-silicon nitride stack film (O/N)100 and a Hard Mask (HM)200, wherein the silicon oxide-silicon nitride stack film (O/N)100 and the Hard Mask (HM) are formed on the surface of a substrate and are spaced from each other;
s200, etching the upper surface of the substrate stacking structure to form a channel hole 300;
s300, depositing and filling the channel hole to form a channel hole side wall stacking structure functional film 400; the channel hole sidewall stacking structure functional thin film comprises an oxide-nitride-oxide structure (ONO) serving as a blocking layer, a storage layer and a tunneling layer;
s400, depositing a protective film 500 on the surface of the side wall stacking structure, wherein the thickness of the protective film on the top of the channel hole is larger than that of the protective film on the bottom of the channel hole; the thickness of the protective film is gradually transited from the top to the bottom so that the protective film on one side of the longitudinal section of the channel hole is in an inverted cone shape, the deposition process is controlled so that the thickness of the protective film on the top of the channel hole is basically equal to the thickness of the residual protective film on the bottom of the channel hole after dry etching, and the form of the protective film after dry etching is shown in fig. 3 b.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.

Claims (4)

1. A process for protecting sidewalls in high aspect ratio trench hole etching, comprising the steps of:
providing a substrate stacking structure;
etching and forming a channel hole on the substrate stacking structure;
depositing and filling a functional film with a channel hole side wall stacking structure in the channel hole;
depositing a protective film on the surface of the side wall stacking structure, wherein the thickness of the protective film at the top of the channel hole is larger than that at the bottom of the channel hole;
the thickness of the protective film is gradually transited from the top to the bottom, so that the protective film on one side of the longitudinal section of the channel hole is in an inverted cone shape.
2. The process for protecting sidewalls as claimed in claim 1, wherein the deposition process is controlled such that the thickness of the protective film at the top of the channel hole to the thickness of the protective film at the bottom of the channel hole are substantially equal to the thickness of the remaining protective film after the dry etching.
3. The process for protecting sidewalls as claimed in claim 1 or 2, wherein the substrate stack structure comprises a silicon oxide-silicon nitride stack film (O/N) spaced apart from each other and a Hard Mask (HM) thereon formed on the surface of the substrate.
4. The process for protecting sidewalls as claimed in claim 1 or 2, wherein the channel hole sidewall stack structure functional film comprises an oxide-nitride-oxide structure (ONO) functioning as a blocking layer, a memory layer and a tunneling layer.
CN201711140438.XA 2017-11-16 2017-11-16 Process for protecting side wall in etching high depth-to-width ratio trench hole Active CN107994026B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201711140438.XA CN107994026B (en) 2017-11-16 2017-11-16 Process for protecting side wall in etching high depth-to-width ratio trench hole

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201711140438.XA CN107994026B (en) 2017-11-16 2017-11-16 Process for protecting side wall in etching high depth-to-width ratio trench hole

Publications (2)

Publication Number Publication Date
CN107994026A CN107994026A (en) 2018-05-04
CN107994026B true CN107994026B (en) 2020-07-10

Family

ID=62030808

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201711140438.XA Active CN107994026B (en) 2017-11-16 2017-11-16 Process for protecting side wall in etching high depth-to-width ratio trench hole

Country Status (1)

Country Link
CN (1) CN107994026B (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111261508B (en) 2018-09-26 2021-02-09 长江存储科技有限责任公司 Step coverage improvement of memory channel layer in 3D NAND memory
CN109524415B (en) * 2018-11-14 2021-03-30 长江存储科技有限责任公司 Manufacturing method of three-dimensional memory and three-dimensional memory
CN110808251A (en) * 2019-11-12 2020-02-18 中国科学院微电子研究所 A kind of channel preparation method of three-dimensional memory
CN113314541B (en) * 2020-06-08 2022-12-02 长江存储科技有限责任公司 Memory device
CN113725228B (en) * 2021-08-26 2023-08-08 长江存储科技有限责任公司 Three-dimensional memory and manufacturing method thereof

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1197414A (en) * 1997-09-25 1999-04-09 Sony Corp Plasma etching method for silicon-oxide based insulating film
CN1723549A (en) * 2002-10-11 2006-01-18 兰姆研究有限公司 Method for plasma etching performance enhancement
CN103972153A (en) * 2013-01-31 2014-08-06 华邦电子股份有限公司 Contact hole plug manufacture method
CN104766866A (en) * 2015-04-10 2015-07-08 武汉新芯集成电路制造有限公司 3D flash memory channel manufacturing method
CN106298784A (en) * 2015-05-29 2017-01-04 旺宏电子股份有限公司 Memory element and manufacturing method thereof
CN107316807A (en) * 2016-04-22 2017-11-03 中芯国际集成电路制造(上海)有限公司 The preparation method of semiconductor devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1197414A (en) * 1997-09-25 1999-04-09 Sony Corp Plasma etching method for silicon-oxide based insulating film
CN1723549A (en) * 2002-10-11 2006-01-18 兰姆研究有限公司 Method for plasma etching performance enhancement
CN103972153A (en) * 2013-01-31 2014-08-06 华邦电子股份有限公司 Contact hole plug manufacture method
CN104766866A (en) * 2015-04-10 2015-07-08 武汉新芯集成电路制造有限公司 3D flash memory channel manufacturing method
CN106298784A (en) * 2015-05-29 2017-01-04 旺宏电子股份有限公司 Memory element and manufacturing method thereof
CN107316807A (en) * 2016-04-22 2017-11-03 中芯国际集成电路制造(上海)有限公司 The preparation method of semiconductor devices

Also Published As

Publication number Publication date
CN107994026A (en) 2018-05-04

Similar Documents

Publication Publication Date Title
CN107994026B (en) Process for protecting side wall in etching high depth-to-width ratio trench hole
CN107946310B (en) A preparation method of 3D NAND flash memory using air gap as dielectric layer and flash memory
US20130032908A1 (en) Hybrid Film for Protecting MTJ Stacks of MRAM
CN108091562B (en) ONO etching method of SONOS memory
US8835279B2 (en) Method of manufacturing semiconductor device
US9048139B2 (en) Method for fabricating non-volatile memory device
CN107994027B (en) Method for reducing load effect influence in SONO etching
CN105742171B (en) A kind of floating boom and preparation method thereof
US10868022B2 (en) Flash memory device and fabrication method thereof
CN107658222B (en) Planarization process of 3D NAND flash memory channel hole
CN107482016B (en) 3D NAND preparation method for preventing silicon damage of selective epitaxial growth and obtained 3D NAND flash memory
CN107369688B (en) Preparation method of flash memory
CN109326600B (en) Three-dimensional memory device and preparation method thereof
US10121669B2 (en) Flash memory fabrication method
CN107968050B (en) Method for etching bottom of channel hole
TWI748406B (en) Memory device and forming method thereof
CN105405809B (en) A kind of manufacturing method of flash memory
CN107527858B (en) Method for fabricating shallow trench in flash memory
TW201725705A (en) Method for fabricating memory
CN107994033B (en) 3D NAND channel hole forming method based on oxide-polycrystalline silicon thin film stacking
CN107946311B (en) Method for controlling critical dimension of channel in 3D NAND flash memory structure
CN111199979B (en) Preparation method of three-dimensional memory
WO2007026391A1 (en) Semiconductor device and fabrication method thereof
CN107994029B (en) Preparation method of 3D NAND flash memory adopting novel trench hole electric connection layer material and flash memory
CN107507772B (en) Method for etching bottom of channel hole

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant