CN107731671B - The technique for improving the injection boron element diffusion of growing epitaxial silicon intermediate ion - Google Patents
The technique for improving the injection boron element diffusion of growing epitaxial silicon intermediate ion Download PDFInfo
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- CN107731671B CN107731671B CN201710733222.8A CN201710733222A CN107731671B CN 107731671 B CN107731671 B CN 107731671B CN 201710733222 A CN201710733222 A CN 201710733222A CN 107731671 B CN107731671 B CN 107731671B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
- H01L21/2253—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase by ion implantation
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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Abstract
The present invention provides the techniques for improving the injection boron element diffusion of growing epitaxial silicon intermediate ion in a kind of 3D NAND flash memory structure, corona treatment is carried out by using silicon slot interface of the gas containing F and/or Cl to growing epitaxial silicon, the monocrystalline silicon at growing epitaxial silicon interface effectively can be destroyed and then be converted into amorphous silicon, and the growing epitaxial silicon speed at amorphous silicon interface is slower than the growing epitaxial silicon speed of monocrystalline silicon interface, to advantageously form the vacancy (Void) between silicon epitaxy layer and substrate；The vacancy (Void) of formation becomes the barrier (Barrier) of boron element interface diffusion, the boron element for effectively blocking ion implantation doping diffuses to silicon substrate from silicon epitaxy layer, to improve threshold voltage (Vt) characteristic of silicon epitaxy layer, and then finally improve the overall performance of 3D nand flash memory.
Description
Technical field
The present invention relates to field of semiconductor manufacture more particularly to a kind of 3D NAND flash memory structure and preparation method thereof, especially
It is a kind of technique that can improve the injection boron element diffusion of silicon epitaxy intermediate ion.
Background technique
With the development of plane flash memories, the production technology of semiconductor achieves huge progress.But recently
Several years, the development of plane flash memory encountered various challenges: physics limit, the existing developing technique limit and storage electron density
Limit etc..In this context, to solve the difficulty that encounters of planar flash memory and most ask being produced into for lower unit storage unit
This, a variety of different three-dimensional (3D) flash memories structures are come into being, such as 3D NOR (3D or non-) flash memory and 3D NAND
(3D and non-) flash memory.
Wherein, in the 3D flash memory of NOR type structure, storage unit is arranged in parallel between bit line and ground wire, and in NAND
In the 3D flash memory of type structure, storage unit tandem between bit line and ground wire is arranged.NAND-type flash memory tool with cascaded structure
There are lower reading speed, but writing speed with higher, so that NAND-type flash memory is suitable for storing data, it is excellent
Point is that small in size, capacity is big.Flush memory device can be divided into stacked grid type and separate gate type according to the structure of storage unit, and
And floating gate device and silicon-oxide-nitride-oxide (SONO) device are divided into according to the shape of charge storage layer.Its
In, SONO type flush memory device has reliability more preferably than floating grid polar form flush memory device, and can be executed with lower voltage
Programming and erasing operation, and ONOS type flush memory device has very thin unit, and convenient for manufacture.
In the preparation of 3D NAND (3D and non-) flash memory, it usually needs one layer of degree of purity of extension is higher on a silicon substrate
Silicon epitaxial layer, or mix up silicon substrate growing epitaxial layers in height and asked with latch (Latch Up) effect etc. for preventing device
Topic, specific growing epitaxial silicon technique generally include following steps:
S1: channel etching, referring to Fig. 1 a, specifically, providing substrate 1, the substrate surface is formed with multi-layer intercrossed stacking
Interlayer dielectric layer 2 and sacrificial dielectric layer 3, the sacrificial dielectric layer 3 be formed between adjacent interlayer dielectric layer 2；The layer
Between dielectric layer 2 be oxide skin(coating), the sacrificial dielectric layer 3 be nitride layer, to form NO stacked structure (NO Stacks)；
After NO stacked structure surface deposited hard mask oxide skin(coating) (Hard Mask Oxide), the interlayer dielectric layer 2 and sacrificial is etched
To form channel 4, the channel 4 passes to the substrate 1 and forms the silicon slot 5 of certain depth domestic animal dielectric layer 3.
S2: etching post-processing (Post Etch Treatment) (not shown), specifically, using nitrogen (N2), nitrogen
(N2) and carbon monoxide (CO) or nitrogen (N2) and hydrogen (H2) the silicon slot region being etched is purged, after this etching
The method of reason has better polymer removal effect than common cleaning.
S3: growing epitaxial silicon, referring to Fig. 1 b, specifically, firstly, using wet-cleaning and/or plasma clean to silicon
Slot region carries out prerinse processing；Silicon is then carried out at silicon slot 5 is epitaxially-formed silicon epitaxy layer 6 (SEG).
S4: ion implantation doping boron element specially carries out ion implanting processing to the silicon epitaxy layer 6 referring to Fig. 1 c
To adulterate boron element.
After above-mentioned operation, it may also need to carry out the deposition such as ONOP (oxide/nitride/oxide/polysilicon), etching
Process, these subsequent process steps can generate a large amount of heat and form pyroprocess, and the atomic number of the boron element due to doping
Number the, molecular weight are small, are easy to generate diffusion in these subsequent pyroprocesses, to cross between silicon epitaxy layer and substrate
Interface, go in the middle of silicon substrate that (lower section white arrow is boron element diffusion in a-b referring to fig. 2, Fig. 2 a by silicon epitaxy layer
Direction), to influence the control of threshold voltage (Vt), and then finally influence the performance of 3D nand flash memory.
Therefore, the interface diffusion of ion implantation doping boron element how is reduced, effectively to improve silicon epitaxial layer
Threshold voltage characteristic is endeavoured always the direction of research by those skilled in the art.
Summary of the invention
The purpose of the present invention is to provide a kind of production method of 3D nand flash memory, it can be realized and reduce in silicon epitaxy layer
Boron ion implantation elements diffusion, to improve the performance of 3D nand flash memory.
To achieve the goals above, the invention proposes a kind of improvement growing epitaxial silicon intermediate ion injection boron element diffusions
Technique, it is characterised in that the following steps are included:
Channel etching, specifically, firstly, provide substrate, and substrate surface formed NO stacked structure (NO Stacks)；
Then, it performs etching to form channel, the channel passes to the substrate and forms the silicon slot of certain depth；
Etching post-processing (Post Etch Treatment) converts amorphous by monocrystalline silicon for it to destroy silicon rooved face
Silicon；
Growing epitaxial silicon, specifically, carrying out silicon at silicon slot is epitaxially-formed silicon epitaxy layer (SEG)；
Boron element is adulterated, ion implanting processing specially is carried out to adulterate boron element to the silicon epitaxy layer.
Further, the formation NO stacked structure (NO Stacks), specifically, forming multilayer in the substrate surface
The interlayer dielectric layer and sacrificial dielectric layer being staggeredly stacked, the sacrificial dielectric layer are formed between adjacent interlayer dielectric layer；Institute
Stating interlayer dielectric layer is oxide skin(coating), and the sacrificial dielectric layer is nitride layer, to form NO stacked structure (NO
Stacks)。
It further, further include being formed on NO stacked structure surface and being covered firmly before etching in the channel etching step
Mould oxide skin(coating) (Hard Mask Oxide).
Further, the etching, specifically, etching the NO vertically downward using anisotropic dry etch process
Stacked structure is to form the channel.
Further, the etching post-processing, is to carry out corona treatment using the gas containing F and/or Cl, to have
The monocrystalline silicon destruction at growing epitaxial silicon interface is converted amorphous silicon by effect.
Further, in the growing epitaxial silicon step, there is vacancy between obtained silicon epitaxy layer and substrate
(Void)。
Further, the height of the vacancy (Void) can guarantee, so that polysilicon passage and institute in subsequent technique
It states and forms current path between silicon epitaxy layer and substrate.
Further, the height of the vacancy (Void) is less than the depth of the silicon slot.
The present invention also provides a kind of 3D NAND flash memory structure, the silicon epitaxy layer in the flash memory structure is by above-mentioned
Process is prepared.
Compared with prior art, the beneficial effects are mainly reflected as follows:
First, after channel etching, carried out by using silicon slot interface of the gas containing F and/or Cl to growing epitaxial silicon
The monocrystalline silicon at growing epitaxial silicon interface can be destroyed effectively and be converted into amorphous silicon in turn by corona treatment, and amorphous silicon circle
The growing epitaxial silicon speed in face is slower than the growing epitaxial silicon speed of monocrystalline silicon interface, to advantageously form silicon epitaxy layer and lining
Vacancy (Void) between bottom；
Second, the vacancy (Void) of formation become boron element interface diffusion barrier (Barrier), effectively block from
The boron element of son injection doping diffuses to silicon substrate from silicon epitaxy layer, so that the threshold voltage (Vt) for improving silicon epitaxy layer is special
Property；
Third, technique of the invention can be effectively controlled vacancy (Void) height, to guarantee effectively to stop boron element diffusion
While, it also can guarantee the polysilicon passage in subsequent technique, silicon epitaxy layer, form circuit pathways between substrate.
Detailed description of the invention
By reading the following detailed description of the preferred embodiment, various other advantages and benefits are common for this field
Technical staff will become clear.The drawings are only for the purpose of illustrating a preferred embodiment, and is not considered as to the present invention
Limitation.And throughout the drawings, the same reference numbers will be used to refer to the same parts.In the accompanying drawings:
Fig. 1 a-c is the process flow chart of the growing epitaxial silicon of 3D NAND flash memory structure in the prior art；
Fig. 2 a-b shines for the schematic illustration and scanning electron microscope of boron element interface diffusion in growing epitaxial silicon in the prior art
Piece；
Fig. 3 a-d is the process flow chart of the growing epitaxial silicon of 3D NAND flash memory structure in the present invention；
Fig. 4 is that the polysilicon passage of 3D NAND flash memory structure in the present invention, silicon epitaxy layer, the electric current between silicon substrate are logical
Road schematic diagram.
Specific embodiment
The illustrative embodiments of the disclosure are more fully described below with reference to accompanying drawings.Although showing this public affairs in attached drawing
The illustrative embodiments opened, it being understood, however, that may be realized in various forms the disclosure without the reality that should be illustrated here
The mode of applying is limited.It is to be able to thoroughly understand the disclosure on the contrary, providing these embodiments, and can be by this public affairs
The range opened is fully disclosed to those skilled in the art.
For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail well known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to related system or related business
Limitation, changes into another embodiment by one embodiment.Additionally, it should think that this development may be complicated and expend
Time, but to those skilled in the art it is only routine work.
The present invention is more specifically described by way of example referring to attached drawing in the following passage.It is wanted according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very simplified form and using non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Referring to FIG. 3, in the present embodiment, a kind of improvement growing epitaxial silicon intermediate ion injection boron element diffusion is proposed
Technique, specifically includes the following steps:
S100: channel etching, specifically, firstly, provide substrate, and substrate surface formed NO stacked structure (NO
Stacks)；Then, it performs etching to form channel, the channel passes to the substrate and forms the silicon slot of certain depth；
S200: etching post-processing (Post Etch Treatment) is converted it by monocrystalline silicon with destroying silicon rooved face
For amorphous silicon；
S300: growing epitaxial silicon, specifically, carrying out silicon at silicon slot is epitaxially-formed silicon epitaxy layer (SEG)；
S400: doping boron element specially carries out ion implanting processing to the silicon epitaxy layer to adulterate boron element.
Specifically, please referring to Fig. 3 a, in the step s 100, progress step S110 first provides substrate 100, and in substrate
100 surfaces form the interlayer dielectric layer 110 and sacrificial dielectric layer 120 of multi-layer intercrossed stacking, and the sacrificial dielectric layer 120 is formed in
Between adjacent interlayer dielectric layer 110；The interlayer dielectric layer 110 is oxide skin(coating), such as silicon oxide layer, the sacrificial dielectric
Layer 120 is nitride layer, such as silicon nitride layer, to form NO stacked structure (NO Stacks)；Step S120 is then carried out,
Hard mask oxide skin(coating) (Hard Mask Oxide) is formed on NO stacked structure surface；Followed by step S130, adopt
The NO stacked structure is etched vertically downward with anisotropic dry etch process to form channel 130, and the channel 130 is logical
To the substrate 100 and form the silicon slot 140 of certain depth.
Fig. 3 b is please referred to, in step s 200, the etching of corona treatment is carried out using the gas containing F and/or Cl
(Post Etch Treatment) technique is post-processed, to destroy silicon rooved face, by the growing epitaxial silicon interface of silicon rooved face by list
Crystal silicon is converted into amorphous silicon.
Fig. 3 c is please referred to, in step S300, silicon is carried out at silicon slot 140 is epitaxially-formed silicon epitaxy layer 150
(SEG).Since the etching for carrying out S200 post-processes (Post Etch Treatment), so that growing epitaxial silicon interface is by list
Crystal silicon is converted into amorphous silicon, and the growing epitaxial silicon speed at amorphous silicon interface is than the growing epitaxial silicon speed of monocrystalline silicon interface
Slowly, to form the vacancy (Void) 160 between silicon epitaxy layer 150 and substrate 100 during growing epitaxial silicon.
Fig. 3 d is please referred to, in step S400, ion implanting processing is carried out to adulterate boron member to the silicon epitaxy layer 150
Element.
The silicon epitaxy layer that present invention process is prepared, need to carry out the height of vacancy (Void) 160 effectively to adjust and
Control, to guarantee to form effective electric current between the polysilicon passage 170 of subsequent preparation, silicon epitaxy layer 150 and silicon substrate 100
Access, therefore the height of vacancy (Void) 160 should be less than the depth H of silicon slot (referring to FIG. 4, graphical dots dash-dot curve is electricity
Logical circulation road signal).
To sum up, it after channel etching, is carried out by using silicon slot interface of the gas containing F and/or Cl to growing epitaxial silicon
The monocrystalline silicon at growing epitaxial silicon interface can be destroyed effectively and be converted into amorphous silicon in turn by corona treatment, and amorphous silicon circle
The growing epitaxial silicon speed in face is slower than the growing epitaxial silicon speed of monocrystalline silicon interface, to advantageously form silicon epitaxy layer and lining
Vacancy (Void) between bottom；The vacancy (Void) of formation becomes the barrier (Barrier) of boron element interface diffusion, effectively hinders
The boron element for having kept off ion implantation doping diffuses to silicon substrate from silicon epitaxy layer, to improve the threshold voltage of silicon epitaxy layer
(Vt) characteristic；Meanwhile technique of the invention can be effectively controlled vacancy (Void) height, to guarantee effectively to stop boron element diffusion
While, it also can guarantee the polysilicon passage in subsequent technique, silicon epitaxy layer, form circuit pathways between substrate.
The foregoing is only a preferred embodiment of the present invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of the claim
Subject to enclosing.
Claims (8)
1. a kind of technique for improving the injection boron element diffusion of growing epitaxial silicon intermediate ion, which comprises the following steps:
Channel etching, specifically, firstly, provide substrate, and substrate surface formed NO stacked structure (NO Stacks)；Then,
It performs etching to form channel, the channel passes to the substrate and forms the silicon slot of certain depth；
Etching post-processing (Post Etch Treatment) converts amorphous silicon by monocrystalline silicon for it to destroy silicon rooved face；
Growing epitaxial silicon, specifically, carrying out silicon at silicon slot is epitaxially-formed silicon epitaxy layer (SEG), obtained silicon epitaxy
There is vacancy (Void) between layer and substrate；
Boron element is adulterated, ion implanting processing specially is carried out to adulterate boron element to the silicon epitaxy layer.
2. technique according to claim 1, it is characterised in that:
The formation NO stacked structure (NO Stacks), specifically, forming the interlayer of multi-layer intercrossed stacking in the substrate surface
Dielectric layer and sacrificial dielectric layer, the sacrificial dielectric layer are formed between adjacent interlayer dielectric layer；The interlayer dielectric layer is
Oxide skin(coating), the sacrificial dielectric layer is nitride layer, to form NO stacked structure (NO Stacks).
3. technique according to claim 1, it is characterised in that:
It further include forming hard mask oxide skin(coating) on NO stacked structure surface before etching in the channel etching step
(Hard Mask Oxide)。
4. technique according to claim 1, it is characterised in that:
The etching, specifically, anisotropic dry etch process is used to etch the NO stacked structure vertically downward with shape
At the channel.
5. technique according to claim 1, it is characterised in that:
The etching post-processing, is to carry out corona treatment using the gas containing F and/or Cl, effectively by silicon epitaxy life
The monocrystalline silicon destruction at long interface is converted into amorphous silicon.
6. technique according to claim 1, it is characterised in that:
The height of the vacancy (Void) can guarantee, so that the polysilicon passage in subsequent technique and the silicon epitaxy layer and lining
Current path is formed between bottom.
7. technique according to claim 6, it is characterised in that:
The height of the vacancy (Void) is less than the depth of the silicon slot.
8. a kind of 3D NAND flash memory structure, it is characterised in that: the silicon epitaxy layer of the flash memory structure is any by claim 1-7
Technique described in one is prepared.
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| KR102675751B1 (en) | 2019-01-08 | 2024-06-14 | 양쯔 메모리 테크놀로지스 씨오., 엘티디. | Three-dimensional memory device and method of manufacturing the same |
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| CN104201176A (en) * | 2014-09-23 | 2014-12-10 | 武汉新芯集成电路制造有限公司 | 3D NAND flash structure and production method thereof |
| CN105470260A (en) * | 2015-12-03 | 2016-04-06 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and method for manufacturing the same |
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| US6812523B1 (en) * | 2001-09-21 | 2004-11-02 | Wei-Kan Chu | Semiconductor wafer with ultra thin doping level formed by defect engineering |
| TW579569B (en) * | 2003-02-11 | 2004-03-11 | Au Optronics Corp | Multi-level diffusion barrier layer structure of TFT LCD and manufacturing method thereof |
| KR101087797B1 (en) * | 2010-06-15 | 2011-11-30 | 주식회사 하이닉스반도체 | Wafer processing method |
| CN103855018B (en) * | 2012-12-04 | 2017-03-29 | 上海华虹宏力半导体制造有限公司 | Channel bottom carries out ion implanting and adjusts BV and the method for improving conducting resistance |
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| CN104201176A (en) * | 2014-09-23 | 2014-12-10 | 武汉新芯集成电路制造有限公司 | 3D NAND flash structure and production method thereof |
| CN105470260A (en) * | 2015-12-03 | 2016-04-06 | 中国科学院微电子研究所 | Three-dimensional semiconductor device and method for manufacturing the same |
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