CN107967905A - Verify device, method and the display panel and equipment of display panel clock signal - Google Patents
Verify device, method and the display panel and equipment of display panel clock signal Download PDFInfo
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- CN107967905A CN107967905A CN201810003135.1A CN201810003135A CN107967905A CN 107967905 A CN107967905 A CN 107967905A CN 201810003135 A CN201810003135 A CN 201810003135A CN 107967905 A CN107967905 A CN 107967905A
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- display panel
- drive signal
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3648—Control of matrices with row and column drivers using an active matrix
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- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Tests Of Electronic Circuits (AREA)
- Controls And Circuits For Display Device (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a kind of device for verifying display panel clock signal, including：Receiver, for receiving the array base palte drive signal to be verified from host computer；Waveform generator, for producing and the corresponding array base palte benchmark drive signal of array base palte drive signal to be verified；Comparator, for the array base palte drive signal to be verified received and the array base palte benchmark drive signal to be compared, if the two signal is consistent, the gate drive signal to be verified is then sent to the drive circuit of the array base palte, otherwise exports the drive circuit that invalid signals are sent to the array base palte.The embodiment provides a kind of device, method and display panel and equipment for verifying display panel clock signal, it is able to verify that whether the setting of test condition in debugging process is correct, so as to improve debugging efficiency.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of device for verifying display panel clock signal, method
And display panel and equipment.
Background technology
The normal display of the display panel of TFT-LCD is closely related with the setting of correct sequential, therefore is designed for exploitation
For personnel, correct sequential sets it is particularly important that design is debugged in the early stage.
Many developers often do not pay attention to the parameter for setting sequential to debug in debugging process, when causing in debugging process
There is mistake in sequence premise, so as to lose time, influence development progress.
The content of the invention
At least one to solve the above-mentioned problems, first aspect present invention provides a kind of verification display panel clock signal
Device, including
Receiver, for receiving the drive signal to be verified from host computer；
Waveform generator, for producing and the corresponding benchmark drive signal of drive signal to be verified；
Comparator, for the drive signal to be verified received and the benchmark drive signal to be compared, if
The two signal is consistent, then the drive signal to be verified is sent to the drive circuit of the display panel, it is invalid otherwise to export
Signal is sent to the drive circuit of the display panel.
Further, the drive signal to be verified is data drive signal or scanning drive signal.
Further, the display panel is provided with test interface, and the waveform generator is coupled in the display panel
On test interface, for producing the benchmark drive signal.
Further, the comparator is logic gates.
Further, the logic gates includes thin film transistor (TFT).
Second aspect of the present invention provides a kind of method for verifying display panel clock signal, including
S101：Receiver receives the drive signal to be verified from host computer；
S103：Waveform generator produces and the corresponding benchmark drive signal of drive signal to be verified；
S105：The drive signal to be verified received and the benchmark drive signal are compared by comparator, if
The two signal is consistent, then jumps to S107, otherwise jump to S109；
S107：The drive signal to be verified is sent to the drive circuit of the display panel；
S109：Output invalid signals are sent to the drive circuit of the display panel.
Third aspect present invention provides a kind of display panel, including the device described in first aspect.
Fourth aspect present invention provides a kind of display device, including the display panel described in the third aspect.
Beneficial effects of the present invention are as follows：
In the verification device of the present invention, by verifying the setting of time sequence parameter in display panel debugging process, so that really
The premise for protecting debugging is correct, avoids mistake occur in debugging, so as to improve debugging efficiency.
Brief description of the drawings
The embodiment of the present invention is described in further detail below in conjunction with the accompanying drawings.
Fig. 1 shows the flow chart of the verification display panel clock signal method of one embodiment of the present of invention；
Fig. 2 shows the structure diagram of the verification display panel clock signal device of one embodiment of the present of invention.
Embodiment
In order to illustrate more clearly of the present invention, the present invention is done further with reference to preferred embodiments and drawings
It is bright.Similar component is indicated with identical reference numeral in attached drawing.It will be appreciated by those skilled in the art that institute is specific below
The content of description is illustrative and be not restrictive, and should not be limited the scope of the invention with this.
One embodiment of the present of invention provides a kind of method for verifying display panel clock signal, as shown in Figure 1, specific bag
Include：S101：Receiver receives the drive signal to be verified from host computer；S103：Waveform generator produce with it is described to be verified
The corresponding benchmark drive signal of drive signal；S105：Comparator is by the drive signal to be verified received and the base
Quasi- drive signal is compared, if the two signal is consistent, is jumped to S107, is otherwise jumped to S109；S107：Will be described to be tested
Card drive signal is sent to the drive circuit of the display panel；S109：Output invalid signals are sent to the display panel
Drive circuit.
Design and debugging stage are developed, it is necessary to largely debug the function to detect display panel and refer in display panel
Mark, the time sequence parameter setting from host computer is the basis of debugging efforts in debugging process, once error can cause a large amount of nothings
Effect test, and it is possible to damage display panel, therefore it is particularly important that verification to the parameter.
It is related to data drive signal and turntable driving to display panel transmission timing signal using host computer in the present embodiment
Signal.Receiver on the display panel receives the clock signal from host computer, i.e., drive signal to be verified, and this is believed
Number it is transmitted in comparator.The waveform generator of coupling at the same time on said display panel is it is anticipated that debugging target produces benchmark
Drive signal, is to be transmitted in comparator by the signal.
The comparator can realize that comparator described in the present embodiment uses logic gates using operational amplifier,
Further, the logic gates includes thin film transistor (TFT), which can utilize the existing display panel
The preparation process of middle array base palte is made.
In the present embodiment, the comparator is judged according to the waveform of above two signal, judges the height of waveform
Whether consistent with width, if the consistent clock signal shown from host computer is set correctly, this is proved to be successful, will be described to be tested
Card drive signal is sent to the drive circuit of the display panel, and the display panel can be tested.If inconsistent
Show that the clock signal from host computer sets mistake, comparator output invalid signals (such as low level) are sent to the display
The drive circuit of panel, this verification terminate.
It is corresponding, as shown in Fig. 2, one embodiment of the present of invention provides a kind of dress for verifying display panel clock signal
Put, including receiver, for receiving the drive signal to be verified from host computer；Waveform generator, is treated for producing with described
Verify the corresponding benchmark drive signal of drive signal；Comparator, for by the drive signal to be verified received and institute
State benchmark drive signal to be compared, if the two signal is consistent, the drive signal to be verified is sent to the display surface
The drive circuit of plate, otherwise exports the drive circuit that invalid signals are sent to the display panel.
In a specific example, the frame initial pulse STV for scan drive circuit is verified, first, on
Position machine sets test parameter：Horizontal total pixel number (Htotal) and frequency (f), STV=Htotal*f, then sends STV signals
To display panel, the display panel receives the clock signal, and by the signal transmission to comparator.The display is used at the same time
The waveform generator of panel produces a simulation STV signal according to expected test target, i.e. benchmark drive signal, and by the signal
It is transmitted to comparator.Comparator is compared the waveform of two kinds of signals, the high level width of STV signal waveforms is contrasted, if ripple
Shape unanimously then illustrate host computer set horizontal total pixel number (Htotal) and frequency (f) correctly, by the STV signal transmissions to institute
State the drive circuit of array base palte in display panel, through level shifter conversion display on a display panel, and can continue into
Follow-up test of the row to display panel.Illustrate the test parameter mistake that host computer is set, comparator output if waveform is inconsistent
Low level changes host computer test parameter, originally to remind to develop to the drive circuit of the display panel with debugging efforts personnel
Secondary verification terminates.
It should be noted that it will be appreciated by those skilled in the art that in actual debugging efforts, those skilled in the art can
With according to actual conditions to such as line scanning clock signal VCK, data drive circuit start of line pulse signal STH it is other when
Sequential signal is verified that details are not described herein.
An alternative embodiment of the invention provides a kind of display panel, including the verification described in above-described embodiment is shown
The device of panel clock signal.
An alternative embodiment of the invention provides a kind of display device, including the display surface provided in above-described embodiment
Plate.The display device can be that mobile phone, tablet computer, television set, display, laptop, Digital Frame, navigator etc. are appointed
What has the product or component of display function.
Obviously, the above embodiment of the present invention is only intended to clearly illustrate example of the present invention, and is not pair
The restriction of embodiments of the present invention, for those of ordinary skill in the field, may be used also on the basis of the above description
To make other variations or changes in different ways, all embodiments can not be exhaustive here, it is every to belong to this hair
Row of the obvious changes or variations that bright technical solution is extended out still in protection scope of the present invention.
Claims (8)
- A kind of 1. device for verifying display panel clock signal, it is characterised in that includingReceiver, for receiving the drive signal to be verified from host computer；Waveform generator, for producing and the corresponding benchmark drive signal of drive signal to be verified；Comparator, for the drive signal to be verified received and the benchmark drive signal to be compared, if the two Signal is consistent, then the drive signal to be verified is sent to the drive circuit of the display panel, otherwise exports invalid signals It is sent to the drive circuit of the display panel.
- 2. device according to claim 1, it is characterised in that the drive signal to be verified is data drive signal or sweeps Retouch drive signal.
- 3. device according to claim 1, it is characterised in that the display panel is provided with test interface, the waveform The test interface of generator coupling on said display panel, for producing the benchmark drive signal.
- 4. device according to claim 1, it is characterised in that the comparator is logic gates.
- 5. device according to claim 4, it is characterised in that the logic gates includes thin film transistor (TFT).
- A kind of 6. method for verifying display panel clock signal, it is characterised in that includingS101：Receiver receives the drive signal to be verified from host computer；S103：Waveform generator produces and the corresponding benchmark drive signal of drive signal to be verified；S105：The drive signal to be verified received and the benchmark drive signal are compared by comparator, if the two Signal is consistent, then jumps to S107, otherwise jump to S109；S107：The drive signal to be verified is sent to the drive circuit of the display panel；S109：Output invalid signals are sent to the drive circuit of the display panel.
- 7. a kind of display panel, it is characterised in that including the device any one of claim 1-5.
- 8. a kind of display device, it is characterised in that including the display panel described in claim 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810003135.1A CN107967905A (en) | 2018-01-02 | 2018-01-02 | Verify device, method and the display panel and equipment of display panel clock signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810003135.1A CN107967905A (en) | 2018-01-02 | 2018-01-02 | Verify device, method and the display panel and equipment of display panel clock signal |
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| Publication Number | Publication Date |
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| CN107967905A true CN107967905A (en) | 2018-04-27 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201810003135.1A Pending CN107967905A (en) | 2018-01-02 | 2018-01-02 | Verify device, method and the display panel and equipment of display panel clock signal |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021114354A1 (en) * | 2019-12-10 | 2021-06-17 | 深圳市华星光电半导体显示技术有限公司 | Detection method and detection circuit for liquid crystal display panel |
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| US11348496B2 (en) | 2019-10-12 | 2022-05-31 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Detecting method and detecting circuit of LCD panel |
| WO2021114354A1 (en) * | 2019-12-10 | 2021-06-17 | 深圳市华星光电半导体显示技术有限公司 | Detection method and detection circuit for liquid crystal display panel |
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Application publication date: 20180427 |
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