CN107947791B

CN107947791B - A fast frequency switching microsystem based on integrated phase-locked loop chip

Info

Publication number: CN107947791B
Application number: CN201711392874.6A
Authority: CN
Inventors: 刘晓东; 聂利鹏; 刘志哲; 曹玉雄; 陈磊; 杜景超
Original assignee: Beijing Institute of Remote Sensing Equipment
Current assignee: Beijing Institute of Remote Sensing Equipment
Priority date: 2017-12-21
Filing date: 2017-12-21
Publication date: 2021-04-09
Anticipated expiration: 2037-12-21
Also published as: CN107947791A

Abstract

The invention discloses a fast frequency switching micro-system based on an integrated phase-locked loop chip, comprising: a Flash chip and an integrated phase-locked loop frequency synthesizer chip with a built-in VCO; wherein, the integrated phase-locked loop frequency synthesizer chip with a built-in VCO comprises: Frequency multipliers/dividers, frequency and phase detectors, charge pumps, loop filters, summing circuits, broadband voltage-controlled oscillators, digital-to-analog converters, and multi-mode frequency dividers. The integrated phase-locked loop chip and the Flash chip together form a fast frequency switching micro-system based on the integrated phase-locked loop chip through the SiP method. The micro-system provides high-performance RF frequency source signal from the integrated phase-locked loop frequency synthesizer chip with built-in VCO, and realizes the fast switching of the output frequency of the phase-locked loop by reading the control signal stored in the Flash chip. The system of the invention has a high degree of integration, and can greatly reduce the locking time while realizing the output of the wideband radio frequency frequency source signal without affecting the loop bandwidth.

Description

Rapid frequency switching micro system based on integrated phase-locked loop chip

Technical Field

The invention relates to a microsystem, in particular to a rapid frequency switching microsystem based on an integrated phase-locked loop chip.

Background

The conventional frequency source system is limited by a reference frequency, a loop bandwidth, switching among a plurality of sub-bands, and the like, and therefore, the frequency switching time is generally over 5 us. For fast frequency switching system applications, the frequency switching time may be as low as 1us or less, and for this requirement, a common solution is to use a plurality of phase-locked loop loops and perform frequency selection between the loops. This solution allows to achieve a frequency switching time of the order of hundreds ns, since the switching time is mainly determined by the switching speed, but its drawbacks are also very significant: firstly, the complexity of system design is greatly increased; secondly, the frequency point and the sequence of frequency switching need to be known in advance, and the working frequency of a certain phase-locked loop is locked at the frequency in advance before the system enters the next working frequency point, so that the application occasions of the fast-hopping source are greatly limited; and thirdly, because the phase-locked loop with at least two different locking frequencies works, certain interference signals exist in the system, and the design difficulty of the system is increased. In terms of reducing the locking time, there is a fast locking scheme, which can reduce the time to 1us magnitude, and it uses an on-chip non-volatile memory (NVM) to store the oscillation frequency of some kind of hybrid voltage-controlled oscillator, which is actually to add a preset module in front of the voltage-controlled oscillator, and implement the presetting of the control voltage of the oscillator through digital control. However, this solution also has certain drawbacks: one is that the devices used by the non-volatile memory are not devices provided in a standard process library; secondly, the nonvolatile memory occupies a very large chip area, and if the data storage capacity is large, the chip design difficulty is greatly increased; thirdly, the working voltage adopted by the nonvolatile memory during data writing is usually higher than that of the CMOS, so that the data writing mode is very complex and is not easy to be applied in practice.

Disclosure of Invention

The invention aims to provide a rapid frequency switching micro-system based on an integrated phase-locked loop chip, which solves the problems that the traditional phase-locked loop frequency source system is long in switching time, a fast-hopping frequency source system for rapid frequency switching is complex, limited in application occasions and high in design difficulty, and a frequency preset phase-locked loop data writing mode based on an NVM is complex and is not easy to actually apply.

A fast frequency switching microsystem based on an integrated phase locked loop chip, comprising: the Flash chip also comprises: the integrated phase-locked loop frequency synthesizer chip internally provided with the VCO is internally integrated with a frequency multiplier/divider, a phase frequency detector, a charge pump, a loop filter, a summing circuit, a broadband voltage-controlled oscillator, a digital-to-analog converter, a multi-mode frequency divider and a digital processor. The frequency multiplier/divider receives the input of a crystal oscillator/signal source signal REF _ IN from outside the system and is controlled by a frequency multiplier/divider ratio control signal from the digital processor, and the output end of the frequency multiplier/divider is connected with one input end of the phase frequency detector. The other input end of the phase frequency detector is connected with the output end of the multi-mode frequency divider, and the output end of the phase frequency detector is connected with the input end of the charge pump. The charge pump is controlled by a charge/discharge current control signal from the digital processor, and the output of the charge pump is connected to the loop filter. The loop filter is controlled by a parameter configuration signal from the digital processor, and an output of the loop filter is connected to one input of the summing circuit. The other input of the summing circuit is connected to the output of the digital-to-analog converter, and the output of the summing circuit is connected to the input of the voltage-controlled oscillator. The voltage-controlled oscillator is controlled by a VCO frequency control signal from the digital processor, and the output end of the voltage-controlled oscillator is connected with the input end of the multi-mode frequency divider, the input end of the output buffer and the input end of the counter. The input end of the digital-to-analog converter is connected with the digital processor and is controlled by the digital-to-analog conversion output control signal. The output terminal of the multi-modulus frequency divider is connected with one input terminal of the digital processor. The input end of the digital processor receives four digital signals of an accompanying clock signal SCLK, a chip selection signal SS, a DATA transmission signal TXD and a reset signal RST _ N from outside the system, the other input end of the digital processor is also connected with the output end of the counter, meanwhile, a DATA port of the digital processor is bidirectionally connected with Flash, the output end of the digital processor is connected with the counter, and meanwhile, three output ports of READ, WRITE and ADDRESS of the digital processor are connected with Flash.

The Flash chip is controlled by an integrated phase-locked loop frequency synthesizer chip with a built-in VCO (voltage controlled oscillator), and stores or outputs data to the integrated phase-locked loop chip in an asynchronous parallel mode; an integrated phase-locked loop frequency synthesizer chip with a built-IN VCO is controlled by digital signals SCLK, SS, DATA and RST _ N from outside a system, and generates a high-performance frequency source signal FOUT after frequency multiplication is carried out on a crystal oscillator signal or a signal source signal REF _ IN; the frequency multiplier/divider is used for carrying out frequency multiplication or frequency division on the off-chip crystal oscillator signal or the signal source signal REF _ IN; the phase frequency detector is used for comparing the frequency and the phase of the output signal from the frequency multiplier/divider and the output signal from the multi-mode divider so as to control the charging and discharging processes of the charge pump; the charge pump is used for charging and discharging the loop filter; a loop filter for converting the charge/discharge current of the charge pump into a control voltage V_A(ii) a A summing circuit for controlling the voltage V to the output from the loop filter_AAnd the output voltage V of the D/A converter_DSumming to generate final voltage-controlled oscillator control voltage V_C(ii) a Wideband voltage controlled oscillator, controlled frequency word and control voltage V_CControlling to generate continuously adjustable broadband radio frequency output; a D/A converter for converting the D/A signal from the digital processor into an analog voltage signal V_DAnd is combined with V_ASumming is carried out; the multi-mode frequency divider is used for dividing the frequency of the output signal of the voltage-controlled oscillator and feeding the frequency-divided output signal back to the input end of the phase frequency detector; the digital processor is internally provided with an SPI module, a Sigma-Delta modulator module, a table look-up algorithm module and a Flash control module; the SPI module receives digital input from outside of the system and generates internal control signals, including control signals for a frequency multiplier/divider, a charge pump, a loop filter, a broadband voltage-controlled oscillator, a digital-to-analog converter and a multi-mode divider; the Sigma-Delta modulator module is used for realizing fractional frequency division; the table look-up algorithm module is used for searching the target frequency control word; the Flash control module is used for writing and reading data of the Flash chip. And the output buffer is used for buffering and amplifying the output signal of the phase-locked loop and outputting the signal to the outside of the chip, and the output power of the output buffer is configured through the digital processor. The counter counts the frequency of the signal from the voltage-controlled oscillator within a set time to obtain the current oscillation frequency of the voltage-controlled oscillator.

The application method of the micro system based on the fast frequency switching of the integrated phase-locked loop chip comprises the following three working modes:

and (3) correction mode:

the summing circuit is open V_AInput to the port, receiving only from V_DInput to the port, control voltage V of the voltage-controlled oscillator at this time_CSize and V_DAre equal. The digital processor performs a two-dimensional scan of the VCO frequency control word P and the A/D converted output control word D to obtain 2 for each of the VCO frequency sub-bands⁶64 frequency points, a total of 2⁸The x 64 is 16384 frequency points, and the frequency size corresponding to the frequency points is obtained by counting through a counter. The frequency of these frequency points, together with the corresponding VCO frequency control word P and D/A conversion output control word D, will be written when the WRITE signal of the digital processor is activePutting the data into Flash. During writing, the ADDRESS is composed of a VCO frequency control word P and an analog-to-digital conversion output control word D, and DATA corresponds to the frequency.

Preparation mode:

the system first enters a ready mode when powered up. The digital processor READ signal is effective, and the internal register READs all the frequency sizes stored in the Flash, the corresponding VCO frequency control word P and the analog-to-digital conversion output control word D in sequence into the internal memory of the digital processor.

Fast frequency switching mode of operation:

after the ready mode, the system enters a fast frequency switching mode of operation. The summing circuit receives the signals from V simultaneously_APort and V_DInput to the port, control voltage V of the voltage-controlled oscillator at this time_CIs a V_AAnd V_DThe sum of (1). The counter is closed. The digital processors READ and WRITE are both inactive. The digital processor receives four digital signals of SCLK, SS, TXD and RST _ N from outside the system, obtains the value of each on-chip circuit control word through an internal SPI module, and calculates a VCO frequency control word P and a D/A conversion output control word D of the frequency to be switched through an internal table look-up algorithm module, wherein the values comprise a frequency multiplication/division ratio A, a multi-mode frequency divider frequency division ratio control word M, a charge/discharge current control word C, a loop filter parameter configuration K and an output power control word E. Because the VCO frequency control word P is 8 bits and the digital-to-analog conversion output control word D is 6 bits, after the frequency to be switched is obtained by operating REF _ IN, a, M, the table lookup algorithm will find a set of P and D values that can obtain the closest frequency to the table lookup algorithm IN at most 14 clock cycles. The digital processor configures the obtained P and D values directly to the corresponding modules, and the oscillation frequency of the VCO will be close to the target frequency. Then the loop is adjusted quickly to form a lock.

Preferably, in the fast frequency switching operation mode, the loop is locked after fast adjustment, and the duration of the adjustment process is controlled within 800 ns.

Preferably, in the fast frequency switching operation mode, the entire frequency switching process is controlled within 1 us.

The system is simple and easy, the integration level is high, and the fast switching of the working frequency of the broadband frequency source is realized based on the integrated phase-locked loop chip and the Flash chip. Compared with the traditional design mode, the integrated phase-locked loop chip and the Flash chip are integrated and packaged by using an SiP mode, namely a System in Package, the fast frequency switching function same as that of a fast jump source is realized in a single chip, the complexity and the working mode of the System are simplified, and the size is greatly reduced. Because a plurality of configurable modules are adopted in the broadband phase-locked loop, a flexible architecture mode is formed, and working frequency points, loop bandwidths and the like are easy to configure; in addition, because the data writing and reading of the Flash chip are in a parallel mode, the voltage-controlled oscillator is configured to be close to the working frequency in a very short time, and the loop is locked in a very short time.

Drawings

FIG. 1 is a block diagram of a fast frequency switching microsystem based on an integrated PLL chip.

1, a Flash chip 2, an integrated phase-locked loop frequency synthesizer chip 3 with a built-in VCO, a frequency multiplier/frequency divider 4, a phase frequency detector 5, a charge pump 6, a loop filter 7, a summing circuit 8, a broadband voltage-controlled oscillator 9, a digital-to-analog converter 10, a multi-mode frequency divider 11, a digital processor 12, an output buffer 13, a counter

Detailed description of the preferred embodiment 1

A block diagram of a fast frequency switching microsystem based on an integrated phase-locked loop chip comprises: the integrated phase-locked loop frequency synthesizer chip 2 of built-in VCO comprises frequency multiplier/divider 3, phase frequency detector 4, charge pump 5, loop filter 6, summation circuit 7, broadband voltage controlled oscillator 8, digital-to-analog converter 9, multi-mode frequency divider 10, digital processor 11, output buffer 12, counter 13, still includes: a Flash chip 1. And the integrated phase-locked loop frequency synthesizer chip 2 with the built-in VCO and the Flash chip 1 are packaged and integrated by using SiP.

The frequency multiplier/divider 3 receives the input of the crystal oscillator/signal source signal REF _ IN from outside the system and is controlled by the frequency multiplier/divider ratio control signal from the digital processor 11, and the output end thereof is connected with the phase frequency detector 4. The input end of the phase frequency detector 4 is connected with the output ends of the frequency multiplier/divider 3 and the multi-mode divider 10, and the output end is connected with the input end of the charge pump 5. The input end of the charge pump 5 is connected with the output end of the phase frequency detector 4 and is controlled by a charging/discharging current control signal from the digital processor 11, and the output end is connected with the loop filter 6. The loop filter 6 is connected at an input to the charge pump 5 and controlled by a parameter configuration signal from the digital processor 11 and at an output to the summing circuit 7. The input of the summing circuit 7 is connected to the loop filter 6 and to the output of the digital-to-analog converter 7, and the output is connected to the input of the voltage-controlled oscillator 8. An input of the voltage controlled oscillator 8 is connected to an output of the summing circuit 7 and is controlled by a VCO frequency control signal from a digital processor 11, and an output is connected to an input of the multi-modulus divider 10, an input of an output buffer 12, and an input of a counter 13. The input end of the digital-to-analog converter 9 is connected with the digital processor and is controlled by the digital-to-analog conversion output control signal, and the output end of the digital-to-analog converter is connected with the input end of the summing circuit 7. The input end of the multi-mode frequency divider 10 is connected with the output end of the voltage-controlled oscillator 8, and the output end is connected with the input end of the phase frequency detector 4 and the input end of the digital processor 11. The input end of the digital processor 11 receives four digital signals of SCLK, SS, TXD, RST _ N, etc. from outside the system, the input end is also connected with the output end of the multi-modulus frequency divider 10 and the output end of the counter 13, meanwhile, the DATA port is bidirectionally connected with Flash1, the output end is connected with the counter 13, and simultaneously, three output ports of READ, WRITE, ADDRESS, etc. are connected with Flash.

Detailed description of the preferred embodiment 2

A method for applying a micro system based on fast frequency switching of an integrated phase-locked loop chip comprises the following three working modes:

(1) calibration mode

The summing circuit 7 switches off V_AInput to the port, receiving only from V_DInput to the port, control voltage V of the voltage-controlled oscillator at this time_CSize and V_DAre equal. The digital processor 11 performs a two-dimensional scan of the VCO frequency control word P and the digital-to-analog conversion output control word D to obtain 2 for each of the voltage-controlled oscillator sub-bands⁶64 frequency points, a total of 2⁸×6416384 frequency points, and the frequency magnitudes corresponding to the frequency points are counted by the counter 13. The frequency magnitudes of these frequency points, together with the corresponding VCO frequency control word P and the digital-to-analog conversion output control word D, will be written into Flash when the WRITE signal of the digital processor 11 is active. During writing, the ADDRESS is composed of a VCO frequency control word P and an analog-to-digital conversion output control word D, and DATA corresponds to the frequency.

(2) Preparation mode

The system first enters a ready mode when powered up. The digital processor 11 is asserted, and its internal registers sequentially READ all the frequency values stored in Flash1, and the corresponding VCO frequency control word P and a digital-to-analog conversion output control word D into the internal memory of the digital processor 11.

(3) Fast frequency switching mode of operation

After the ready mode, the system enters a fast frequency switching mode of operation. The summing circuit 7 receives the signals from V simultaneously_APort and V_DInput to the port, control voltage V of the voltage-controlled oscillator at this time_CIs a V_AAnd V_DThe sum of (1). The counter 13 is turned off. The digital processor 11READ and WRITE are both inactive. The digital processor 11 receives four digital signals, such as SCLK, SS, TXD, RST _ N, from outside the system, and obtains values of on-chip circuit control words, including a frequency doubling/dividing ratio a, a multi-modulus divider frequency dividing ratio control word M, a charge/discharge current control word C, a loop filter parameter configuration K, an output power control word E, and the like, through an internal table lookup algorithm module, calculates a VCO frequency control word P and a digital-to-analog conversion output control word D of frequencies to be switched. Because the VCO frequency control word P is 8 bits and the digital-to-analog conversion output control word D is 6 bits, after the frequency to be switched is obtained by operating REF _ IN, a, M, the table lookup algorithm will find a set of P and D values that can obtain the closest frequency to the table lookup algorithm IN at most 14 clock cycles. If the clock frequency is 100MHz, the time required for the table look-up process is within 200 ns. The digital processor 11 configures the resulting P and D values directly to the respective modules, and the oscillation frequency of the VCO will be very close to the target frequency. Then the loop is adjusted for a very short timeAnd then locking is formed. The entire frequency switching process will be controlled to within 1 us.

Claims

1. a fast frequency switching micro-system based on integrated phase-locked loop chip, comprising: Flash chip (1), it is characterized in that also comprising: the integrated phase-locked loop frequency synthesizer chip (2) of built-in VCO, this chip integrates inside Frequency multiplier/divider (3), frequency discriminator (4), charge pump (5), loop filter (6), summation circuit (7), broadband voltage-controlled oscillator (8), digital The analog converter (9), the multi-mode frequency divider (10), the digital processor (11); the frequency multiplier/frequency divider (3) receives the crystal oscillator/signal source signal REF_IN input from outside the system, and receives the input from the digital processing The frequency multiplier/frequency division ratio control signal of the device (11) is controlled, and its output end is connected with one input end of the frequency discriminator (4); the other input end of the frequency discriminator (4) is connected to the multi-mode divider The output end of the frequency discriminator (10) is connected, and the output end of the frequency discriminator (4) is connected with the input end of the charge pump (5); the charge pump (5) receives the charge/discharge current from the digital processor (11) Controlled by a control signal, the output end of the charge pump (5) is connected to a loop filter (6); the loop filter (6) is controlled by a parameter configuration signal from a digital processor (11), and the loop filter (6) The output end of the summation circuit (7) is connected to one input end of the summation circuit (7); the other input end of the summation circuit (7) is connected to the output end of the digital-to-analog converter (9), and the output end of the summation circuit (7) is connected to the output end of the digital-to-analog converter (9). The input end of the voltage-controlled oscillator is connected; the voltage-controlled oscillator is controlled by the VCO frequency control signal from the digital processor (11), and the output end of the voltage-controlled oscillator is connected with the input end and output buffer of the multi-mode frequency divider (10). The input end of the counter (12) is connected with the input end of the counter (13); the input end of the digital-to-analog converter (9) is connected with the digital processor (11), and is controlled by the output control signal of the digital-to-analog conversion; multi-mode frequency division The output end of the device (10) is connected with an input end of the digital processor (11); the input end of the digital processor (11) receives the accompanying clock signal SCLK, chip selection signal SS, data transmission signal TXD, reset from outside the system The signal RST_N has four digital signals, and its other input end is also connected to the output end of the counter (13), and its DATA port is bidirectionally connected to the Flash, its output end is connected to the counter (13), and its READ, WRITE, ADDRESS Three output ports are connected to Flash;

The Flash chip (1) is controlled by the integrated phase-locked loop frequency synthesizer chip (2) with built-in VCO, and stores or outputs data to the integrated phase-locked loop chip in an asynchronous parallel manner; the integrated phase-locked loop frequency synthesizer chip with built-in VCO ( 2) Under the control of digital signals SCLK, SS, DATA, and RST_N from outside the system, the crystal oscillator signal or the signal source signal REF_IN is multiplied to generate a high-performance frequency source signal FOUT; the frequency multiplier/divider (3), with For frequency multiplication or frequency division processing of off-chip crystal oscillator signal or signal source signal REF_IN; frequency discriminator (4), used for output signal from frequency multiplier/frequency divider (3) and from multi-mode frequency division The output signal of the device (10) is compared in frequency and phase to control the charging and discharging process of the charge pump (5); the charge pump (5) is used to charge and discharge the loop filter (6); the loop A filter (6) converts the charging and discharging current of the charge pump (5) into a control voltage VA; _a summation circuit (7) converts the output control voltage VA from the loop filter (6) and digital-to _- analog conversion The output voltage V _D of the device (9) is summed to generate the final voltage-controlled oscillator control voltage V _C ; the broadband voltage-controlled oscillator (8) is controlled by the frequency control word and the control voltage V _C to generate a continuously adjustable Broadband RF frequency output; digital-to-analog converter (9), converting the digital-to-analog signal from the digital processor (11) into an analog voltage signal V _D , and summing with VA; _a multi-mode frequency divider (10), The output signal of the voltage-controlled oscillator is divided into frequency and fed back to the input end of the frequency and phase detector (4); the digital processor (11) includes an SPI module, a Sigma-Delta modulator module, a table look-up algorithm module, Flash control module; SPI module receives digital input from outside the system and generates internal control signals, including frequency multiplier/divider (3), charge pump (5), loop filter (6), broadband voltage-controlled oscillation The control signal of the device (8), the digital-to-analog converter (9), and the multi-mode frequency divider (10); the Sigma-Delta modulator module is used to realize the fractional frequency division; the look-up table algorithm module is used to find the target frequency control word; The Flash control module is used for writing and reading data of the Flash chip (1); the output buffer (12) buffers and amplifies the output signal of the phase-locked loop, and outputs it to the off-chip, and its output power passes through the digital processor ( 11) Perform configuration; the counter (13) counts the frequency of the signal from the voltage-controlled oscillator within a set time, so as to obtain the current size of the oscillation frequency of the voltage-controlled oscillator.

2. a fast frequency switching micro-system application method based on an integrated phase-locked loop chip, is characterized in that, there are following three operating modes:

Correction Mode:

The summation circuit (7) disconnects the input of the V _A port and only receives the input from the V _D port. At this time, the control voltage V _C of the VCO is equal to V _D ; the digital processor (11) controls the VCO frequency. The word P and the digital-to-analog conversion output control word D are scanned two-dimensionally, so that 2 ⁶ =64 frequency points are obtained for each sub-band of the voltage-controlled oscillator, and 2 ⁸ ×64 = 16384 frequency points are obtained in total. The frequency size corresponding to the frequency point is obtained by counting the counter (13); the frequency size of these frequency points, together with the corresponding VCO frequency control word P and the digital-to-analog conversion output control word D, are valid in the WRITE signal of the digital processor (11). It will be written into the Flash; during the writing process, the address ADDRESS consists of the VCO frequency control word P and the digital-to-analog conversion output control word D, and DATA corresponds to the frequency;

Ready Mode:

When the system is powered on, it first enters the preparation mode; the digital processor (11) READ signal is valid, and its internal register reads all the frequencies stored in the Flash and the corresponding VCO frequency control word P and digital-to-analog conversion output control word D in turn into the memory inside the digital processor (11);

Fast frequency switching working mode:

After the preparation mode, the system enters the fast frequency switching operation mode; the summation circuit (7) receives the input from the VA port and the V _D port at the same time, and the control voltage V _C of the voltage controlled oscillator at this time is the sum of V _A and _V _D ; The counter (13) is closed; the digital processor (11) READ and WRITE are invalid; the digital processor (11) receives the four digital signals SCLK, SS, TXD, RST_N from outside the system, and obtains each digital signal through the internal SPI module The value of the on-chip circuit control word, including frequency multiplication/division ratio A, multi-mode frequency divider (10) frequency division ratio control word M, charge/discharge current control word C, loop filter (6) parameter configuration K , output power control word E, and through the internal look-up table algorithm module, calculate the VCO frequency control word P and digital-to-analog conversion output control word D of the frequency to be switched; because the VCO frequency control word P is 8 bits, the digital-to-analog conversion output The control word D is 6 bits. After the frequency to be switched is obtained through the operation of REF_IN, A, and M, the table lookup algorithm will find a set of P and D values that can obtain the closest frequency within a maximum of 14 clock cycles; The digital processor (11) directly configures the obtained P and D values to the corresponding modules, and the oscillation frequency of the VCO will be close to the target frequency; then the loop is quickly adjusted to form a lock.

3. the fast frequency switching micro-system application method based on integrated phase-locked loop chip according to claim 2, is characterized in that, in the fast frequency switching working mode, the loop is quickly adjusted to form locking, and the continuation of this adjustment process The process will be controlled within 800ns.

4 . The method for applying a fast frequency switching microsystem based on an integrated phase-locked loop chip according to claim 2 , wherein in the fast frequency switching working mode, the entire frequency switching process will be controlled within 1us. 5 .