CN113225074B - Universal frequency modulator and frequency modulation method and device - Google Patents

Abstract

The embodiment of the disclosure provides a universal frequency modulator, a frequency modulation method and a device. Wherein the universal frequency modulator comprises: a configurable all-digital phase-locked loop, the all-digital phase-locked loop comprising two loops: loop a and loop b; the loop A comprises: binary phase detector, digital loop filter, digital controlled oscillator, dual-mode frequency divider, differential integral modulator, digital time converter and integer frequency divider; the loop B comprises other parts except a numerical control oscillator in the loop A; the output end of the digital loop filter in the loop A is connected with the input end of the numerical control oscillator; the output signals of the numerical control oscillator are respectively input into a dual-mode frequency divider in a loop A and a loop B; the output end of the digital loop filter in the loop B is connected with the input end of the differential integral modulator in the loop A.

Description

A general frequency modulator, frequency modulation method and device

technical field

The present disclosure relates to, but is not limited to, the field of radio frequency integrated circuits, and particularly relates to a general frequency modulator based on a reconfigurable all-digital phase-locked loop and a frequency modulation method and device.

Background technique

At present, no matter in wireless communication or wired communication applications, phase-locked loops have been widely used due to their simple structure and superior performance, from clock data recovery and spread spectrum in wired communication systems to wireless communication applications frequency synthesis etc. Among them, the digital phase-locked loop is not troubled by serious matching accuracy or leakage current problems like the analog phase-locked loop, which makes its transplantation and expansion in the process easier and better in process compatibility. At the same time, the realization of digitalization makes low power supply voltage possible, and can realize high integration and low power consumption, which provides a good foundation for the application of digital phase-locked loop in the field of radio frequency communication.

With the development of CMOS (Complementary Metal-Oxide-Semiconductor, Complementary Metal Oxide Semiconductor) technology, the all-digital phase-locked loop can provide low-cost and stable frequency generation and modulation through digital calibration, and the binary all-digital phase-locked loop with phase detection function Further reduce the complexity of the design. But in the case of fractional mode, binary all-digital phase-locked loops often require high-resolution digital-to-time converters to avoid significant reduction of in-band noise. Although frequency modulator architectures based on binary all-digital phase-locked loops without high-resolution digital-to-time converters have been recently proposed for wired and wireless systems, most of them are difficult to simultaneously realize wideband and narrowband frequency modulation in the same modulator.

Contents of the invention

The following is an overview of the topics described in detail in this article. This summary is not intended to limit the scope of the claims.

An embodiment of the present disclosure provides a general frequency modulator, and proposes a general frequency modulator architecture based on a reconfigurable all-digital phase-locked loop, so as to respectively perform wideband and narrowband frequency modulation in the same modulator. The embodiment of the present disclosure also provides a method for outputting a modulated signal on demand based on the frequency modulator.

An embodiment of the present disclosure provides a general frequency modulator, including:

A configurable all-digital phase-locked loop, the all-digital phase-locked loop includes two loops: loop A and loop B;

The loop A includes: a first binary phase detector, a first digital loop filter, a numerically controlled oscillator, a first dual-mode frequency divider, a first differential integral modulator, a first digital time converter, The first integer frequency divider; the loop B includes: a second binary phase detector, a second digital loop filter, a second dual-mode frequency divider, a second differential integral modulator, a second digital time converter, second integer frequency divider;

The output end of the first digital loop filter of the loop A is connected to the input end of the numerically controlled oscillator; the output signal of the numerically controlled oscillator is respectively input into the first dual-mode frequency divider and the second Two dual-mode frequency dividers;

The output end of the second digital loop filter of the loop B is connected to the input end of the first differential-sigma modulator of the loop A.

An embodiment of the present disclosure also provides a frequency modulation method, including:

According to the requirement of bandwidth modulation, control the working state of loop A and loop B in the general frequency modulator as described above, so as to realize different configurations of the topological structure of the all-digital phase-locked loop, output from the numerically controlled oscillator The corresponding frequency modulation signal;

Wherein, the bandwidth modulation requirement includes: broadband modulation and narrowband modulation.

An embodiment of the present disclosure also provides an electronic device, including a memory and a processor, where a computer program for performing frequency modulation is stored in the memory, and the processor is configured to read and run the computer program for performing frequency modulation. A computer program to implement the frequency modulation method as described above.

Embodiments of the present disclosure provide that the proposed universal frequency modulator does not require complex and high-power background digital calibration modules to overcome the nonlinearity of key modules in the circuit, but only requires initial calibration and pre-calibration for process deviations and frequency requirements of different channels. Tuning greatly simplifies the design of the circuit and reduces the power consumption of the circuit.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Other aspects will be apparent to others upon reading and understanding the drawings and detailed description.

Description of drawings

FIG. 1 is a schematic structural diagram of a general frequency modulator in an embodiment of the present disclosure;

FIG. 2 is a topological structure of the general frequency modulator under narrowband signal modulation in an embodiment of the present disclosure;

FIG. 3 is a topological structure of the general frequency modulator under broadband signal modulation in an embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

Embodiment one

An embodiment of the present disclosure provides a general frequency modulator, including:

A configurable all-digital phase-locked loop, the all-digital phase-locked loop includes two loops: loop A and loop B;

The loop A includes: a first binary phase detector, a first digital loop filter, a numerically controlled oscillator, a first dual-mode frequency divider, a first differential integral modulator, a first digital time converter, The first integer frequency divider; the loop B includes: a second binary phase detector, a second digital loop filter, a second dual-mode frequency divider, a second differential integral modulator, a second digital time converter, second integer frequency divider;

The output end of the first digital loop filter of the loop A is connected to the input end of the numerically controlled oscillator; the output signal of the numerically controlled oscillator is respectively input into the first dual-mode frequency divider and the second Two dual-mode frequency dividers;

The output end of the second digital loop filter of the loop B is connected to the input end of the first differential-sigma modulator of the loop A.

In some exemplary embodiments, the first binary phase detector is used to compare the phase information of the reference clock signal and the feedback clock signal from the first integer frequency divider;

The first digital loop filter is configured to perform digital domain filtering on the signal output by the first binary phase detector to generate a first control signal;

The numerically controlled oscillator is used to generate an output modulation signal according to the first control signal output by the first digital loop filter;

The first dual-mode frequency divider is used to generate two frequency division modes according to the second control signal from the first differential-sigma modulator to realize fractional frequency division;

The first differential-sigma modulator is used to generate a second control signal to control the first dual-mode frequency divider to achieve fractional frequency division;

The first digital-to-time converter is configured to delay the clock signal output by the first dual-mode frequency divider;

The first integer frequency divider is used for integer frequency division of the clock signal output by the first digital-to-time converter;

The second binary phase detector is used to compare the phase information of the reference clock signal and the feedback clock signal from the second integer frequency divider;

The second digital loop filter is configured to perform digital domain filtering on the signal output by the second binary phase detector to generate a third control signal;

The second dual-mode frequency divider is used to generate two frequency division modes according to the fourth control signal from the second differential-sigma modulator to realize fractional frequency division;

The second differential-integral modulator is used to generate a fourth control signal to control the second dual-mode frequency divider to achieve fractional frequency division;

The second digital-to-time converter is configured to delay the clock signal output by the second dual-mode frequency divider;

The second integer frequency divider is used for integer frequency division of the clock signal output by the second digital-to-time converter.

In some exemplary embodiments, both the first binary phase detector and the second binary phase detector are phase detectors with 1-bit output, and the two input terminals input the external reference clock signal and the second The frequency-divided feedback clock signal output by an integer frequency divider or the second integer frequency divider, the output signal of the first/second binary phase detector represents the advance of the reference clock signal and the feedback clock signal /lag information.

In some exemplary embodiments, both the first digital loop filter and the second digital loop filter include a proportional path and an integral path; the proportional path implements phase tracking, and the integral path implements frequency tracking;

The first control signal output by the first digital loop filter in the loop A is connected to the numerically controlled oscillator for frequency tuning;

The third control signal output by the second digital loop filter in the loop B is connected to the first differential-sigma modulator of the loop A to adjust the fractional frequency division coefficient of the loop A.

In some exemplary embodiments, the numerically controlled oscillator is designed based on a ring oscillation structure, and the first control signal from the first digital loop filter controls the magnitude of the current injected into the numerically controlled oscillator by the PMOS array to achieve the numerically controlled oscillation Frequency tuning of the device;

The numerically controlled oscillator also includes a finite impulse response filter.

In some exemplary embodiments, when the frequency modulator outputs a narrowband modulation signal, the finite impulse response filter is turned on, so as to reduce quantization noise.

In some exemplary embodiments, both the first dual-mode frequency divider and the second dual-mode frequency divider are divided by 4/5 frequency dividers designed based on current mode frequency dividers, and can be controlled by the second control signal Or, under the selection of the fourth control signal, the frequency division operation of dividing by 4 or 5 is performed on the input high-frequency clock signal, so as to realize fractional frequency division. In some exemplary embodiments, the comprehensive stability and noise performance of the overall circuit are better by adopting the divider by 4/5 frequency divider. In some exemplary embodiments, those skilled in the art can also adjust frequency dividers using other parameters.

In some exemplary embodiments, the first differential-sigma modulator has a third-order single-loop structure, and is configured to generate the second control signal according to the input fractional frequency division control word to control the first dual-mode frequency divider Realize fractional frequency division; the second control signal is a random output sequence.

The second differential-integral modulator has a third-order single-loop structure, and is configured to generate the fourth control signal according to the input fractional frequency division control word to control the second dual-mode frequency divider to achieve fractional frequency division; the The fourth control signal is a random output sequence.

Wherein, the fractional frequency division control word input to the first differential-sigma modulator in the loop A is jointly determined by the third control signal output by the second digital loop filter of the loop B and the external input; The fractional frequency division control word input to the second differential integral modulator in the loop B is determined by an external input.

The external input includes: a narrow-band low-pass modulation signal, a wide-band high-pass modulation signal or a wide-band low-pass modulation signal among the modulation signals to be output.

In some exemplary embodiments, both the first differential-integral modulator and the second differential-integral modulator operate at a high frequency below 1 GHz, and the quantization noise generated by it can be further pushed to a higher frequency to be effectively filtering out to achieve an improvement in the overall noise performance of the modulator. In some exemplary embodiments, the first differential-sigma modulator and the second differential-sigma modulator work in a frequency range of 500MHz-650MHz or 500MHz-700MHz.

In some exemplary embodiments, both the first digital-to-time converter and the second digital-to-time converter are composed of 16 delay units, and the delay time of each delay unit is the period of the digitally controlled oscillator output clock signal one-eighth of

The first digital-to-time converter is configured to, according to the input fractional frequency division control word (fifth control signal) of the first differential-sigma modulator and the second control signal output by the first differential-sigma modulator, control The delay of the output signal of the first digital-to-time converter is used to reduce deterministic jitter generated by the two frequency division modes of the first dual-mode frequency divider and improve performance. That is, the fractional frequency division control word (fifth control signal) input to the first differential-sigma modulator and the second control signal output by the first differential-sigma modulator are both input into the first digital-to-time converter, and the first digital The digital part in the time converter generates the control word to control the delay chain (delay chain composed of delay units).

The second digital-to-time converter is configured to, according to the input fractional frequency division control word (sixth control signal) of the second differential-sigma modulator and the fourth control signal output by the second differential-sigma modulator, control The delay of the output signal of the second digital-to-time converter is used to reduce the deterministic jitter generated by the two frequency division modes of the second dual-mode frequency divider and improve the performance. That is, the fractional frequency division control word (sixth control signal) input to the second differential-sigma modulator and the fourth control signal output by the second differential-sigma modulator are all input into the second digital-to-time converter, and the second digital The digital part in the time converter generates the control word to control the delay chain (delay chain composed of delay units).

In some exemplary embodiments, the first integer frequency divider is an all-digital circuit designed based on a digital gate circuit, and is controlled by a seventh control signal to achieve corresponding frequency division of the input clock signal. In some exemplary embodiments, the seventh control signal is a 5-bit control signal.

In some exemplary embodiments, the second integer frequency divider is an all-digital circuit designed based on a digital gate circuit, and is controlled by an eighth control signal to achieve corresponding frequency division of the input clock signal. In some exemplary embodiments, the eighth control signal is a 5-bit control signal.

In some exemplary embodiments, loop B in the general frequency modulator is opened when wideband modulation is performed; said loop A is also opened when wideband modulation is performed; the numerically controlled oscillator of said loop A outputs a wideband modulation signal . That is, when performing broadband modulation, loop B in the described universal frequency modulator is turned on; the loop A is turned on; the numerically controlled oscillator of the loop A outputs a broadband modulation signal;

or,

Loop B in the general-purpose frequency modulator is closed when narrowband modulation is performed; the loop A is opened when narrowband modulation is performed; the numerically controlled oscillator of the loop A outputs a narrowband modulation signal; the required narrowband modulation signal The high-pass modulation section inputs the digitally controlled oscillator while performing narrowband modulation. That is, when performing narrowband modulation, the loop B in the general frequency modulator is closed; the loop A is opened; the narrowband high-pass modulation signal in the signal to be modulated is input to the numerically controlled oscillator, and the loop A of the The digitally controlled oscillator outputs a narrowband modulation signal.

In some exemplary embodiments, loop B in the general-purpose frequency modulator is closed when narrowband modulation is performed; loop A is opened when narrowband modulation is performed, and the numerically controlled oscillator also inputs a narrowband high-pass modulation signal, so The finite impulse response filter in the numerically controlled oscillator is turned on; the high-pass modulation part of the required narrowband modulation signal is input to the numerically controlled oscillator when performing narrowband modulation; the numerically controlled oscillator of the loop A outputs a narrowband modulated signal. That is, when performing narrowband modulation, the loop B in the general frequency modulator is closed; the loop A is opened; the finite impulse response filter in the numerically controlled oscillator is opened; the narrowband high-pass modulation in the signal to be modulated The signal is input to the numerically controlled oscillator; the numerically controlled oscillator of the loop A outputs a narrowband modulation signal.

The universal frequency modulator based on the reconfigurable all-digital phase-locked loop in the embodiment of the present disclosure has the ability to perform wideband and narrowband frequency modulation respectively in the same modulator. The universal modulator is based on an all-digital binary phase-locked loop design, and the circuit is simpler and easier to implement. At the same time, the reconfigurable structure can achieve good modulation linearity according to requirements, without the need for complex and high-power background digital calibration modules to overcome the nonlinearity of key modules in the circuit, which further simplifies the design of general modulators and reduces power consumption. consumption.

Embodiment two

An embodiment of the present disclosure also provides a general frequency modulator, which is a general frequency modulator based on a reconfigurable all-digital phase-locked loop, as shown in FIG. 1 . According to whether the output modulation signal is a narrowband modulation signal or a broadband modulation signal, the internal all-digital phase-locked loop is reconfigured to form two topological structures corresponding to the modulation signal, and finally the two-point modulation technology is used to complete the frequency modulation of the signal. The configurable all-digital phase-locked loop used consists of two loops: loop A and loop B. When outputting a narrowband modulation signal, only loop A works, and the finite impulse response filter of the numerically controlled oscillator in loop A is turned on; when outputting a wideband modulation signal, loop B is also turned on at the same time, recombined with loop A A new frequency modulator (topology) is used to accommodate wideband modulation, but the finite impulse response filter in loop A is now turned off.

As shown in Figure 1, loop B of the configurable all-digital phase-locked loop includes other components in loop A except for the numerically controlled oscillator; that is, except for the numerically controlled oscillator, loop A and loop Road B contains the same components. As shown in Figure 1, loop A includes: binary phase detector, digital loop filter, numerically controlled oscillator, dual-mode frequency divider, differential integral modulator, digital time converter, integer frequency divider; loop B Includes: binary phase detector, digital loop filter, dual-mode frequency divider, differential-sigma modulator, digital-to-time converter, integer frequency divider.

In some exemplary embodiments, the binary phase detector provides a 1-bit output signal according to the lead/lag information of the phase between the externally given reference clock signal and the frequency-divided feedback clock signal; the digital loop filter includes a proportional The path and the integration path are respectively used to realize phase tracking and frequency tracking, and a corresponding digital control signal is generated according to the output phase signal of the corresponding binary phase detector, which is recorded as the first control signal. In loop A, the first control signal output by the digital loop filter is used to control the digitally controlled oscillator, and in loop B, the third control signal output by the digital loop filter is used to control the differential integral of loop A Modulator. The numerically controlled oscillator is designed based on a ring oscillation structure, including a finite impulse response filter to reduce quantization noise during narrowband modulation; the PMOS (P-channel Metal-Oxide-Semiconductor, P-channel) is controlled by a digital control signal (first control signal) metal-oxide-semiconductor) array to inject the current size of the oscillator to realize the frequency tuning of the oscillator; The control signal (second control signal) output by the differential integral modulator in A is selected to divide the input high-frequency clock signal by 4 or 5 to achieve fractional frequency division; in loop A, the differential integral modulator is The third-order single-loop structure generates a random output sequence according to the given fractional frequency division control word (referred to as the fifth control signal) to control the dual-mode frequency divider to realize fractional frequency division, and the random output sequence is the obtained the second control signal. In the loop B, the dual-mode frequency divider is a 4/5 frequency divider designed based on the current mode frequency divider. In the loop B, the control signal (the fourth control signal) output by the differential integral modulator selects the input The high-frequency clock signal is divided by 4 or 5 to achieve fractional frequency division; in loop B, the differential integral modulator is a third-order single-loop structure, and according to the given fractional frequency division control word (denoted as the sixth control signal) to generate a random output sequence to control the dual-mode frequency divider to achieve fractional frequency division, and the random output sequence is the fourth control signal.

In loop A, the fractional frequency division control word (fifth control signal) is jointly determined by the third control signal output by the digital loop filter of loop B and the external input, and in loop B, the fractional frequency division control word (Sixth control signal) is determined by external input. In loop A, the frequency division control word (fifth control signal) is determined by adding the third control signal and the wideband high-pass modulation signal or the narrowband low-pass modulation signal in the externally input signal to be modulated. In the loop B, the frequency division control word (sixth control signal) is determined by the wideband low-pass modulation signal and the fractional frequency division coefficient in the externally input signal to be modulated.

In loop A and loop B, the digital-to-time converter consists of a preset number (for example, 16) of delay units to reduce the deterministic jitter generated by the two frequency division modes of the dual-mode frequency divider. Those skilled in the art can adjust the number of delay units as required, and are not limited to the 16 delay units defined in this embodiment.

In loop A and loop B, the integer frequency divider is an all-digital circuit based on digital gate circuit design, controlled by a control signal (recorded as the seventh control signal in loop A, and recorded as the eighth control signal in loop B) , not shown in the current drawing) realize corresponding frequency division for the input clock signal. For example, in some exemplary embodiments, both the seventh control signal and the eighth control signal are 5-bit control signals.

In some exemplary embodiments, the topological structures of the general frequency modulator in the case of narrowband modulation and wideband modulation are shown in FIGS. 2 and 3 respectively, which are denoted as the first topology and the second topology. Fig. 2 has shown the topological structure (the first topological structure) when described modulator works under the narrow-band frequency modulation situation of modulation index less than 1, and the low-frequency part and the high-frequency part of the signal to be modulated are respectively connected to the differential integral modulator of loop A and digitally controlled oscillators. In the circuit, only loop A is working, and loop B is closed. At this time, the fractional frequency division control word (fifth control signal) of the differential integral modulator in loop A is given by the low frequency part of the signal to be modulated. At the same time, in order to suppress the quantization noise of the high-pass branch, the finite impulse response filter of the digitally controlled oscillator in the loop A is turned on.

As shown in Figure 2, loop B is closed, and the binary phase detector in loop A inputs the reference frequency signal and the feedback clock signal fed back by the integer frequency divider, and the output represents the phase between the reference clock signal and the feedback clock signal after frequency division The 1-bit output signal of the lead/lag information; the digital loop filter inputs the 1-bit signal output by the binary phase detector, and outputs the first control signal; the numerical control oscillator inputs the first control signal and the narrow-band high-pass modulation signal, and outputs the narrow-band modulation Signal; the dual-mode frequency divider inputs the narrow-band modulation signal from the numerically controlled oscillator and the second control signal from the differential integral modulator, and outputs the signal after fractional frequency division; the differential integral modulator inputs the fractional frequency division signal from the dual-mode frequency divider After the signal and the fractional frequency division control word (fifth control signal), output the second control signal; the digital time converter inputs the fractional frequency division signal from the dual-mode frequency divider, and outputs the delayed signal to the integer frequency divider.

It can be seen that in Figure 2, loop B is closed (the gray part is closed and does not work), and the fractional frequency division control word (fifth control signal) input to the differential integral modulator of loop A is determined by the narrow-band low-pass modulation signal.

Wherein, the narrow-band high-pass modulation signal is the high-pass modulation part of the required narrow-band modulation signal, that is, the high-pass modulation part in the signal to be modulated; the narrow-band low-pass modulation signal is the low-pass modulation part of the required narrow-band modulation signal, that is, the signal to be modulated The low-pass modulation section in .

Figure 3 shows the topology (second topology) of the modulator when the modulation index is much greater than 1 in the case of broadband frequency modulation, the low-frequency part and high-frequency part of the signal to be modulated are respectively connected to the differential integral modulation of loop B device and a differential-sigma modulator for loop A. Since the linearity of the oscillator is the key factor of the circuit performance in the case of wideband modulation, loop A and loop B are turned on at the same time, and loop A works as a nested numerically controlled oscillator of loop B, providing loop B with Digitally controlled oscillator with good linearity.

As shown in Figure 3, both loop B and loop A are open. The binary phase detector in loop A inputs the reference frequency signal and the feedback clock signal fed back by the integer frequency divider, and outputs a 1-bit output signal representing the lead/lag information of the phase between the reference clock signal and the frequency-divided feedback clock signal; The digital loop filter inputs the 1-bit signal output by the binary phase detector, and outputs the first control signal; the numerically controlled oscillator inputs the first control signal, and outputs a broadband modulation signal; the dual-mode frequency divider inputs the broadband modulation signal from the numerically controlled oscillator And the second control signal from the differential integral modulator, the signal after the fractional frequency division is output; the differential integral modulator inputs the signal after the fractional frequency division and the fractional frequency division control word (the fifth control signal) from the dual-mode frequency divider, and outputs The second control signal: the digital-time converter inputs the fractional frequency-divided signal from the dual-mode frequency divider, and outputs the delayed signal to the integer frequency divider.

The binary phase detector in loop B inputs the reference frequency signal and the feedback clock signal fed back by the integer frequency divider, and outputs a 1-bit output signal representing the lead/lag information of the phase between the reference clock signal and the frequency-divided feedback clock signal; The digital loop filter inputs the 1-bit signal output by the binary phase detector, and outputs the third control signal; the third control signal output by the digital loop filter enters the differential integral modulator of loop A; the input of the dual-mode frequency divider comes from The broadband modulation signal of the digitally controlled oscillator of loop A and the fourth control signal from its own differential integral modulator output the signal after fractional frequency division; the differential integral modulator inputs the signal after fractional frequency division and fractional frequency division from the dual-mode frequency divider The frequency division control word (sixth control signal) outputs the fourth control signal; the digital-time converter inputs the fractional frequency-divided signal from the dual-mode frequency divider, and outputs the delayed signal to the integer frequency divider.

It can be seen that the second loop is opened in Fig. 3; the fractional frequency division control word (the fifth control signal) of the differential integral modulator input to the loop first is set by the broadband high-pass modulation signal and the third control signal from the second loop; The fractional frequency division control word (sixth control signal) input to the differential integral modulator of loop B is determined by the wideband low-pass modulation signal and the fractional frequency division coefficient.

Wherein, the broadband high-pass modulation signal is the high-pass modulation part of the required broadband modulation signal, that is, the high-pass modulation part in the signal to be modulated; the broadband low-pass modulation signal is the low-pass modulation part of the required broadband modulation signal, that is, the signal to be modulated The low-pass modulation section in .

It can be seen that the use of digital time converters in loop A and loop B can deal with the noise aliasing problem caused by cascading dual-mode frequency dividers and integer frequency dividers; the use of dual-mode frequency dividers + digital time converters +Integer frequency divider cascade can significantly optimize the noise of the overall circuit.

The input and output of each module/component shown in Figure 1-Figure 3 is a schematic representation of the relevant data flow, and does not represent all the input/output of each module/component. Those skilled in the art can combine the basic functions and characteristics of each module/component. know other aspects.

The universal frequency modulator of the embodiment of the present disclosure reconfigures the structure of the internal all-digital phase-locked loop according to the required output modulation signal, and realizes good modulation performance while avoiding complicated background nonlinear calibration circuits. The universal frequency modulator is based on a reconfigurable fractional all-digital phase-locked loop design, and uses two-point modulation to realize signal frequency modulation. The general-purpose frequency modulator is reconfigured for the two loops included in the all-digital phase-locked loop under the different requirements of outputting broadband modulation signals or narrow-band modulation signals, so there is no need for complex and high-power real-time linearity calibration circuits It can adapt to different signal modulation and linearity requirements, has a simple structure and is easy to integrate, and has lower power consumption.

Embodiment three

An embodiment of the present disclosure also provides a frequency modulation method, including:

According to the bandwidth modulation requirements, control the working states of loop A and loop B in the general frequency modulator as described above, so as to realize different configurations of the topological structure of the all-digital phase-locked loop, from the numerically controlled oscillator The corresponding frequency modulation signal is obtained at the output terminal;

Wherein, the bandwidth modulation requirement includes: broadband modulation and narrowband modulation.

In some exemplary embodiments, according to bandwidth modulation requirements, the working states of loop A and loop B in the general-purpose frequency modulator are controlled, so as to realize different configurations of the topology of the all-digital phase-locked loop, including:

When the bandwidth modulation requirement is narrowband modulation, control the loop B to close, the loop A to open, and configure the all-digital phase-locked loop as the first topology;

When the modulation requirement is broadband modulation, the loop B is controlled to be turned on, the loop A is turned on, and the all-digital phase-locked loop is configured as a second topology.

In some exemplary embodiments, the numerically controlled oscillator further includes a finite impulse response filter;

According to bandwidth modulation requirements, control loop A and loop B working states in the general-purpose frequency modulator, so as to realize different configurations of the topological structure of the all-digital phase-locked loop, including:

When the bandwidth modulation requirement is narrowband modulation, control the loop B to close, the loop A to open, and the finite impulse response filter in the numerically controlled oscillator to open; control the input of the narrowband high-pass modulation signal in the signal to be modulated The numerically controlled oscillator; control the narrowband low-pass modulation signal in the signal to be modulated to input the first differential integral modulator to determine the first topology of the all-digital phase-locked loop; when the general-purpose frequency modulator When configured to work under the first topology, the numerically controlled oscillator outputs a narrowband modulation signal.

When the modulation requirement is broadband modulation, control the loop B to open, and the loop A to open; control the broadband high-pass modulation signal in the signal to be modulated to input the first differential integral modulator; control the broadband in the signal to be modulated A low-pass modulation signal is input to the second differential-sigma modulator to determine the second topology of the all-digital phase-locked loop; when the general-purpose frequency modulator is configured to work under the second topology, the The digitally controlled oscillator outputs a broadband modulation signal.

Embodiment four

Embodiments of the present disclosure also provide a frequency modulation method, which uses the general frequency modulator described in the above embodiments to perform frequency modulation, including:

Obtain the bandwidth modulation requirement, when the bandwidth adjustment requirement is narrowband modulation, close loop B in the general frequency modulator, open loop A; obtain the narrowband modulation signal output by the numerical control oscillator of the loop A;

When the bandwidth adjustment requirement is broadband modulation, open loop B and loop A in the general frequency modulator; obtain the broadband modulation signal output by the numerically controlled oscillator of loop A.

An embodiment of the present disclosure also provides an electronic device, including a memory and a processor, where a computer program for performing frequency modulation is stored in the memory, and the processor is configured to read and run the computer program for performing frequency modulation. A computer program to execute the method described in any one of the above embodiments.

An embodiment of the present disclosure also provides an electronic device, including a memory, a processor, and any of the above general frequency modulators, the memory stores a computer program for frequency modulation, and the processor is configured to read And run the computer program for frequency modulation to execute the method described in any one of the above embodiments to control the general frequency modulator to obtain a corresponding frequency modulation signal.

It can be seen that the frequency modulator solution provided by the embodiments of the present disclosure has the following technical characteristics and beneficial effects:

1. Narrowband modulation and broadband modulation can be realized in the same frequency modulator at the same time, which is suitable for both wired communication and wireless communication.

2. The universal frequency modulator is designed based on an all-digital phase-locked loop, and the digital implementation enables the universal frequency modulator to have good process portability and compatibility. At the same time, the digital implementation has a compact structure and a better chip area.

3. The all-digital phase-locked loop structure is reconfigurable, and can be configured into the most suitable topology under narrowband modulation and wideband modulation to meet the requirements for circuit linearity under two different modulation modes. There is no need for complex and high-power background digital calibration modules to overcome the nonlinearity of key modules in the circuit, but only initial calibration and pre-tuning for process deviations and frequency requirements of different channels, which greatly simplifies circuit design and reduces circuit power. consumption.

In describing the embodiments of the present disclosure, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front" , "Back", "Left", "Right", "Vertical", "Horizontal", "Top", "Bottom", "Inner", "Outer", "Clockwise", "Counterclockwise", "Axial ", "radial", "circumferential" and other indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying the referred device Or that an element must have a particular orientation, be constructed and operate in a particular orientation, and thus should not be construed as limiting the invention.

In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless specifically defined otherwise.

In the present invention, unless otherwise clearly specified and limited, terms such as "installation", "connection", "connection" and "fixation" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection , or integrated; it may be mechanically connected or electrically connected; it may be directly connected or indirectly connected through an intermediary, and it may be the internal communication of two components or the interaction relationship between two components, unless otherwise specified limit. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention according to specific situations.

In the embodiments of the present disclosure, unless otherwise specified and limited, the first feature may be in direct contact with the first feature or the first feature and the second feature pass through the middle of the second feature. Media indirect contact. Moreover, "above", "above" and "above" the first feature on the second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. "Below", "beneath" and "beneath" the first feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is less horizontally than the second feature.

In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structure, material or feature is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the described specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples and features of different embodiments or examples described in this specification without conflicting with each other.

Those of ordinary skill in the art can understand that all or some of the steps in the methods disclosed above, the functional modules/units in the system, and the device can be implemented as software, firmware, hardware, and an appropriate combination thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be composed of several physical components. Components cooperate to execute. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). As known to those of ordinary skill in the art, the term computer storage media includes both volatile and nonvolatile media implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data. permanent, removable and non-removable media. Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cartridges, tape, magnetic disk storage or other magnetic storage devices, or can Any other medium used to store desired information and which can be accessed by a computer. In addition, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media .

Claims (8)

1. A universal frequency modulator, comprising:

a configurable all-digital phase-locked loop, the all-digital phase-locked loop comprising two loops: loop a and loop b;

the loop A comprises: a first binary phase detector, a first digital loop filter, a digital controlled oscillator, a first dual-mode frequency divider, a first differential integral modulator, a first digital time converter, a first integer frequency divider; the loop B comprises: a second binary phase detector, a second digital loop filter, a second double-mode frequency divider, a second differential integral modulator, a second digital time converter, a second integer frequency divider;

the output end of the first digital loop filter of the loop A is connected with the input end of the numerical control oscillator; the output signals of the numerical control oscillator are respectively input into the first double-mode frequency divider and the second double-mode frequency divider;

the output end of the second digital loop filter of the loop B is connected with the input end of the first differential integral modulator of the loop A;

the first binary phase discriminator is used for comparing the phase information of the reference clock signal and the feedback clock signal from the first integer frequency divider;

The first digital loop filter is used for performing digital domain filtering on the signal output by the first binary phase discriminator to generate a first control signal;

the digital control oscillator is used for generating an output modulation signal according to a first control signal output by the first digital loop filter;

the first dual-mode frequency divider is used for generating two frequency dividing modes according to a second control signal from the first differential integral modulator so as to realize fractional frequency division;

the first differential integral modulator is used for generating a second control signal to control the first dual-mode frequency divider to realize fractional frequency division;

the first digital time converter is used for delaying the clock signal output by the first dual-mode frequency divider;

the first integer frequency divider is used for integer frequency division of the clock signal output by the first digital time converter;

the second binary phase detector is used for comparing the phase information of the reference clock signal and the feedback clock signal from the second integer frequency divider;

the second digital loop filter is used for performing digital domain filtering on the signal output by the second binary phase discriminator to generate a third control signal;

The second double-mode frequency divider is used for generating two frequency division modes according to a fourth control signal from the second differential integral modulator so as to realize fractional frequency division;

the second differential integral modulator is used for generating a fourth control signal to control the second double-mode frequency divider to realize fractional frequency division;

the second digital time converter is used for delaying the clock signal output by the second double-mode frequency divider;

the second integer frequency divider is used for performing integer frequency division on the clock signal output by the second digital time converter;

the first differential integral modulator is of a third-order single-loop structure and is arranged to generate the second control signal according to an input fractional frequency division control word so as to control the first dual-mode frequency divider to realize fractional frequency division;

the second differential integral modulator is of a third-order single-loop structure and is arranged to generate the fourth control signal according to an input fractional frequency division control word so as to control the second double-mode frequency divider to realize fractional frequency division;

the fractional frequency division control word input into the first differential integral modulator in the loop A is determined by a third control signal output by a second digital loop filter of the loop B and an external input; the fractional frequency division control word input into the second differential integral modulator in the loop B is determined by an external input;

The external inputs include: a narrowband low-pass modulation signal, a wideband high-pass modulation signal or a wideband low-pass modulation signal in the signal to be modulated.

2. The universal frequency modulator of claim 1, wherein,

the first digital loop filter and the second digital loop filter each include a proportional path and an integral path; the proportional path realizes phase tracking, and the integral path realizes frequency tracking;

a first control signal output by a first digital loop filter in the loop A is connected with the numerical control oscillator to perform frequency tuning;

and a third control signal output by the second digital loop filter in the loop B is connected with the first differential integral modulator of the loop A to adjust the fractional frequency division coefficient of the loop A.

3. The universal frequency modulator of claim 1, wherein,

the numerical control oscillator is based on a ring oscillation structure design, and a first control signal from a first digital loop filter controls the current of the PMOS array injected into the numerical control oscillator so as to realize frequency tuning of the numerical control oscillator;

the digitally controlled oscillator further includes a finite impulse response filter.

4. A universal frequency modulator according to any of claims 1-3, characterized in that,

when broadband modulation is carried out, a loop B in the universal frequency modulator is started, a loop A is started, and a digital control oscillator of the loop A outputs a broadband modulation signal;

or,

and when narrowband modulation is carried out, a loop B in the universal frequency modulator is closed, a loop A is opened, a narrowband high-pass modulation signal in a signal to be modulated is input into the numerical control oscillator, and the numerical control oscillator of the loop A outputs a narrowband modulation signal.

5. A universal frequency modulator according to claim 3, characterized in that,

when narrowband modulation is carried out, a loop B in the universal frequency modulator is closed, a loop A is opened, a finite impulse response filter in the numerical control oscillator is opened, a narrowband high-pass modulation signal in a signal to be modulated is input into the numerical control oscillator, and the numerical control oscillator of the loop A outputs a narrowband modulation signal.

6. A method of frequency modulation, comprising:

according to bandwidth modulation requirements, controlling the working states of a loop A and a loop B in the universal frequency modulator according to any one of claims 1-5 to realize different configurations of the topological structure of the all-digital phase-locked loop, and outputting corresponding frequency modulation signals from the numerical control oscillator;

Wherein the bandwidth modulation requirement comprises: broadband modulation and narrowband modulation.

7. The method of claim 6, wherein the step of providing the first layer comprises,

the numerically controlled oscillator further comprises a finite impulse response filter;

according to bandwidth modulation requirements, controlling working states of a loop A and a loop B in the universal frequency modulator to realize different configurations of topological structures of the all-digital phase-locked loop, wherein the method comprises the following steps:

when the bandwidth modulation requirement is narrow-band modulation, the loop B is controlled to be closed, the loop A is opened, and a finite impulse response filter in the numerical control oscillator is opened; controlling a narrow-band high-pass modulation signal in a signal to be modulated to be input into the numerical control oscillator; controlling a narrow-band low-pass modulation signal in a signal to be modulated to be input into the first differential integral modulator so as to determine a first topological structure of the all-digital phase-locked loop;

when the modulation requirement is broadband modulation, controlling the loop B to be opened, and controlling the loop A to be opened; controlling a broadband high-pass modulation signal in a signal to be modulated to be input into the first differential integral modulator; and controlling a broadband low-pass modulation signal in the signal to be modulated to be input into the second differential integral modulator so as to determine a second topological structure of the all-digital phase-locked loop.

8. An electronic device comprising a memory, a processor, characterized in that the memory has stored therein a computer program for frequency modulation, the processor being arranged to read and run the computer program for frequency modulation to perform the method according to claim 6 or 7.

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