CN104079315B - Multi-standard performance reconfigurable type multiple I/Q quadrature carrier generators - Google Patents

Abstract

The invention discloses a reconfigurable I/Q quadrature carrier generator with multi-standard performance. The generator can realize I/Q carrier output with continuous coverage of 0.1-5 GHz and 5-10 GHz, 1.5 ~3GHz continuous differential signal output; at the same time, by configuring the parameters of the programmable charge pump (102), the loop filter (103), the multi-channel voltage-controlled oscillator (104) and the corresponding first multi-channel selection device (105), five-stage division-by-two frequency link (109) and corresponding second multiplexer (110), third multiplexer (112), which can produce different loop bandwidths, different phase noises, Carrier signals at various frequencies with different power consumption levels and different locking times realize the generation of reconfigurable I/Q quadrature carriers with multi-standard performance.

Description

Multi-standard Performance Reconfigurable I/Q Quadrature Carrier Generator

technical field

The present invention relates to the technical field of radio frequency wireless transceivers in wireless communication applications, in particular to a reconfigurable I/Q quadrature carrier generator with multi-standard performance. The generator is based on a fractional frequency division structure and can generate 0.1-5GHz continuous Covered I/Q carrier output and differential signal output with continuous coverage of 5-10GHz and 1.5-3GHz.

Background technique

The frequency synthesizer is an important part of the wireless transceiver. It provides the local oscillator signal for the transceiver. Its performance directly determines the performance level of the transceiver system, and its power consumption often accounts for a large part of the overall power consumption of the transceiver. proportion. In recent years, with the continuous advancement of wireless communication technology, more and more transceivers are developing towards multi-mode and multi-standard, and many single-terminal transceiver chips with broadband and multi-band to meet multiple communication standards have emerged. As a key component of a transceiver, the frequency synthesizer in this type of transceiver system needs to provide a very wide frequency range of local oscillator signals, and different communication standards require different locking time and phase noise performance. If multiple frequencies are used to synthesize Implementing them separately will often complicate the system, and the cost will be difficult to control. In order to reduce cost and improve integration, it is hoped that a single frequency synthesizer can meet the requirements of local oscillator signals under various communication standards; at the same time, if the performance of the frequency synthesizer (including lock time, power consumption level, phase noise, etc.) can Refactoring will make its application more flexible.

Contents of the invention

In view of this, the main purpose of the present invention is to provide a reconfigurable I/Q quadrature carrier generator with multi-standard performance, so that it can meet the requirements of transceivers for local oscillators of various standards in frequency bands below 5 GHz. The multiple voltage-controlled oscillators in the multi-standard performance reconfigurable I/Q quadrature carrier generator need to cover at least 5-10 GHz, so that it is possible to generate 0.1-5 GHz quadrature I/Q Q signal output.

To achieve the above object, the present invention provides a multi-standard performance reconfigurable I/Q quadrature carrier generator, the I/Q quadrature carrier generator includes: a frequency and phase detector, used for input reference The signal is compared with the frequency and phase of the output signal of the programmable multi-mode frequency divider; the programmable charge pump, controlled by the output signal of the frequency and phase detector, generates charging and discharging current, and then charges and discharges the loop filter , to change its output voltage; the loop filter is used to convert the charging and discharging current of the programmable charge pump into an analog voltage for controlling the multi-channel controlled oscillator; the multi-channel voltage-controlled oscillator is controlled by the analog voltage to generate The required phase-locked loop locks the frequency range; the first multiplexer is used to channel select the output signals of multiple voltage-controlled oscillators to determine which voltage-controlled oscillator provides the oscillation frequency; The frequency divider is used to prescale the output signal from the first multiplexer by two to reduce the maximum operating frequency of the programmable multimode frequency divider; the programmable multimode frequency divider is used to control the phase lock The frequency division ratio of the main loop of the ring ultimately determines the locking frequency of the phase-locked loop; the output buffer of the main loop is used to output the main loop signal of the phase-locked loop; the five-stage divide-by-two link is used to generate The I/Q signal of 0.1～5GHz is divided into two channels and output to the receiver and the transmitter respectively; the second multiplexer and the third multiplexer are used for the output signal of the five-stage divide-by-two link Carry out channel selection; to the receiver output buffer and to the transmitter output buffer, for outputting the two signals to the receiver and the transmitter respectively; input buffer, for receiving an external input signal into five stages divided by two Frequency division link.

As can be seen from the above technical solution, the present invention has the following beneficial effects: 1) The multi-standard performance reconfigurable I/Q quadrature carrier generator provided by the present invention adopts a standard CMOS process and is realized by monolithic integration to meet practical applications Low cost requirements, the same chip provides I/Q local oscillation signals covering all frequency bands within 0.1-5GHz. At the same time, the present invention adopts modules such as multi-channel voltage-controlled oscillator, programmable charge pump, loop filter, first multiplexer, second multiplexer, third multiplexer, etc., so that the carrier generator The power consumption level, PLL lock time, loop bandwidth and phase noise performance can be reconfigured. 2) The reconfigurable I/Q quadrature carrier generator with multi-standard performance provided by the present invention adopts a programmable charge pump, and its charging and discharging current can be programmed and configured, so that the automatic adjustment of the loop bandwidth can be realized. 3) The multi-standard performance reconfigurable I/Q quadrature carrier generator provided by the present invention, since multiple voltage-controlled oscillators are used in the phase-locked loop, the overall tuning range of the voltage-controlled oscillator covers 5-10 GHz and 1.5-3GHz, and the characteristics of each independent voltage-controlled oscillator that make up the multi-channel voltage-controlled oscillator are different, and the characteristics of the difference will include: different frequency coverage, different power consumption levels, different phase noise performance , The composition structure is different. 4) The multi-standard performance reconfigurable I/Q quadrature carrier generator provided by the present invention, the first multiplexer adopted is a parallel combination of buffers designed for different operating frequency bands, so that not only targeted It greatly enhances the load capacity and reduces the power consumption level of the phase-locked loop when it is applied in different frequency bands. 5) The multi-standard performance reconfigurable I/Q quadrature carrier generator provided by the present invention adopts a programmable multi-mode frequency divider to complete the frequency division ratio control in a wide range, thereby realizing the phase-locked loop main loop in 5 ～10GHz and 1.5～3GHz frequency locking, and can also meet the requirements of different reference frequency configurations (10～50MHz). 6) The multi-standard performance reconfigurable I/Q quadrature carrier generator provided by the present invention utilizes the main loop output buffer to output the local oscillator of the main loop of the phase-locked loop. It should be noted that the output signal of the main loop Only differential signals, not I/Q signals. The local oscillator signal output by the main loop is 5-10GHz and 1.5-3GHz, which can provide signal source output for other chips. 7) The multi-standard performance reconfigurable I/Q quadrature carrier generator provided by the present invention adopts a five-stage divide-by-two frequency division link to generate an I/Q signal of 0.1 to 5 GHz, and finally outputs it to the receiver and transmitter machine. Dividing the frequency by two can ensure that the output I/Q signal has a good match, and the cascading of the five-stage frequency divider can make the output frequency reach below 0.1GHz. 8) The multi-standard performance reconfigurable I/Q quadrature carrier generator provided by the present invention utilizes the second multiplexer and the third multiplexer to realize the output signal path of the five-stage divide-by-two link Finally, the output signals are provided to the receiver output buffer and the transmitter output buffer respectively.

Description of drawings

Fig. 1 is a system block diagram of a kind of multi-standard performance reconfigurable I/Q quadrature carrier generator system provided by the present invention;

Fig. 2 is an example circuit block diagram of a programmable charge pump in the multi-standard performance reconfigurable I/Q quadrature carrier generator system provided by the present invention;

Fig. 3 is an example circuit diagram of the loop filter in the multi-standard performance reconfigurable type I/Q quadrature carrier generator system provided by the present invention;

4 is an example circuit diagram of a voltage-controlled oscillator in the multi-channel voltage-controlled oscillator in the multi-standard performance reconfigurable I/Q quadrature carrier generator system provided by the present invention;

Figure 5 is a multi-standard performance reconfigurable I/Q quadrature carrier generator system provided by the present invention. Among the multi-channel voltage-controlled oscillators, the frequency preset function can be realized to realize the mixed-signal voltage-controlled oscillator for fast loop locking. An example circuit diagram of ;

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

The invention proposes a multi-standard performance reconfigurable I/Q quadrature carrier generator, which is a frequency synthesizer. Because in the frequency range below 5GHz, a lot of wireless communication standards are concentrated, such as wireless wide area network 2G ~ 3G, wireless wide area network 4G, metropolitan area network, wireless local area network, wireless body area network, medical communication, digital broadcasting and digital TV, etc. , so the present invention designs the frequency output range of the orthogonal carrier generator below 5 GHz. At the same time, the main loop provides an output port, which can provide a differential signal output of 5 to 10 GHz; and the frequency division output part provides a port for external signal input to the frequency division link, providing a platform for implementing MIMO between chips .

Fig. 1 is the system block diagram of multi-standard performance reconfigurable type I/Q quadrature carrier generator provided by the present invention, and this carrier generator includes: frequency and phase detector 101, programmable charge pump 102, loop filter 103 , multi-channel voltage controlled oscillator 104, first multiplexer 105, divide by two prescaler 106, programmable multimode frequency divider 107, main loop output buffer 108, five-stage divide by two frequency link 109, the second multiplexer 110, to the receiver output buffer 111, the third multiplexer 112, to the transmitter output buffer 113, the input buffer 114, the non-volatile memory 115, the digital processor 116 .

The frequency and phase detector 101 is used to compare the frequency and phase of the input reference signal and the output signal of the programmable multi-mode frequency divider 107 . The frequency and phase detector 101 generates corresponding pulse voltage signals according to the frequency difference and phase difference of the two signals, so as to drive the charge pump to charge and discharge the loop filter. One input end of the frequency and phase detector 101 is connected with the external reference signal F _ref , the other input end is connected with the output signal F _div of the programmable multimode frequency divider 107 , and the output end is connected with the input end of the programmable charge pump 102 . The output voltage pulse of the frequency and phase detector 101 controls the charging and discharging of the programmable charge pump 102 .

The programmable charge pump 102 is controlled by the output signal of the frequency and phase detector 101 to generate charging and discharging current, thereby changing the control voltage output by the loop filter. The input end of the programmable charge pump 102 is connected with the output end of the frequency and phase detector 101, and the output end is connected with the input end of the loop filter 103, and simultaneously, its operating state is controlled by the output C[3:0 of the digital processor 116 ]control. The programmable charge pump 102 is preferably a configurable charge pump for charging and discharging current. In the present invention, it is controlled by a 4-bit digital signal, and the current size can be adjusted from the unit current I to 15I, so that the digital processor 116 can be used to lock the phase The loop bandwidth of the loop is adjusted.

The loop filter 103 is realized by a low-pass filter, and is used to convert the charging and discharging current of the programmable charge pump 102 into an analog voltage for controlling the multi-channel voltage-controlled oscillator 104 . The input end of the loop filter 103 is connected to the output end of the programmable charge pump 102 , and the output end is connected to the input end of the multi-channel voltage-controlled oscillator 104 .

The multi-channel voltage-controlled oscillator 104 is used to generate the required oscillating signals of 5-10 GHz and 1.5-3 GHz, and its oscillating frequency is determined by the digital signals A[2:0], B[6:0], P[5:0] and the output voltage of the loop filter 103 are jointly determined. Among them, A[2:0] is used for the selection of the voltage-controlled oscillator. It has 3 control bits, and each bit controls the enable terminal of the corresponding voltage-controlled oscillator. When one of the voltage-controlled oscillators needs to be selected for When working, the corresponding control bit is configured as high level, and all other control bits are configured as low level; B[6:0] is used for sub-band selection, it has 7 control bits, and each bit controls The bit switch of the capacitor array in the voltage-controlled oscillator changes the overall capacitance value of the capacitor array by turning on and off the switch, thereby changing the oscillation frequency of the voltage-controlled oscillator; P[5:0] is used for the frequency preset module The preset signal setting of the mixed-signal voltage-controlled oscillator, when A[2:0] selects the mixed-signal voltage-controlled oscillator to work, the preset module is based on the configuration of P[5:0] and from the loop filter The output voltage of the control voltage is applied to the core of the voltage controlled oscillator to generate the required oscillation frequency. The input end of the multi-channel voltage-controlled oscillator 104 is connected with the output end of the loop filter 103, and the output end is connected with the input end of the first multiplexer 105. Meanwhile, its working state is affected by the output A[ 2:0], B[6:0], P[5:0] control. The multi-channel voltage-controlled oscillator 104 includes three mutually independent voltage-controlled oscillators, among which, the voltage-controlled oscillator controlled by A[2] covers a frequency range of 5-10 GHz and has very good phase noise performance; The voltage-controlled oscillator controlled by 1] covers the frequency range of 1.5-3GHz and has very low power consumption; the voltage-controlled oscillator controlled by A[0] has a frequency preset function, which can realize fast locking and greatly shorten the locking time. According to actual application requirements (such as power consumption requirements, frequency band requirements, lock-in time requirements, phase noise requirements, etc.), the digital processor 116 selects a certain voltage-controlled oscillator to work to form the main loop of the phase-locked loop. The frequency division link 109 can implement frequency configuration in a wide frequency band.

The first multiplexer 105 is used for channel selection of the output signals of the multiple voltage-controlled oscillators 104 to determine which voltage-controlled oscillator provides the oscillation frequency. The input end of this multiplexer 105 is connected with the output end of multi-channel voltage-controlled oscillator 104, and the output end is respectively connected with divide by two prescaler 106, five-stage divide by two frequency link 109 and main loop output buffer 108 connected to the output; meanwhile, its working state is controlled by the output MUX1 [2:0] of the digital processor 116 . The first multiplexer 105 is composed of parallel combinations of buffers designed for different operating frequency bands. Each buffer is controlled by MUX1[2:0] and can be turned on or off independently. After being turned off, the buffer does not consume power .

The divide-by-two prescaler 106 is used for dividing the output signal from the first multiplexer 105 into a divide-by-two prescaler, so as to reduce the maximum operating frequency of the programmable multimode frequency divider 107 and save power consumption. The input end of the divide-by-two prescaler 106 is connected to the output end of the multiplexer 105 , and the output end is connected to the output end of the programmable multi-mode frequency divider 107 .

The programmable multi-mode frequency divider 107 is used to control the frequency division ratio of the signal F _div fed back from the phase-locked loop to the frequency detector 101 , and ultimately determine the locking frequency of the phase-locked loop. Since the frequency of the reference signal F _ref is constant, the frequency of F _div will eventually be consistent with F _ref . Changing the configuration of the programmable multimode frequency divider 107 will change its frequency division ratio, thereby finally changing the frequency of the voltage-controlled oscillator. The oscillation frequency realizes the control of the locking frequency. The input end of this programmable multi-mode frequency divider 107 is connected with the output end of dividing by two prescaler 106, and the output end is connected with the input end of frequency discrimination phase detector 101, simultaneously, its operating state is controlled by digital processor 116 Control of output M[11:0]. In the present invention, the programmable multi-mode frequency divider 107 is controlled by a 12-bit digital signal. It is composed of 8-level 2/3 frequency division units and 4 frequency division ratio expansion logic units. The frequency division ratio range It is 16-511 to meet the working requirements of the broadband phase-locked loop.

The main loop output buffer 108 is used to output the phase locked loop main loop signal. The input end of the main loop output buffer 108 is connected to the output end of the multiplexer 105 , and the output end is provided off-chip for the local oscillator signal output of the phase locked loop main loop.

The five-stage divide-by-two frequency-division link 109 is used to generate I/Q signals of 0.1-5 GHz, and output them to the receiver and the transmitter respectively in two ways. The input end of this five-stage frequency division link 109 is connected with the output end of the first multiplexer 105 and the external signal input buffer 114, and the output end is connected with the second multiplexer 110 and the third multiplexer respectively. The output terminal of the device 112 is connected; at the same time, its working state is controlled by the output N[4:0] of the digital processor 116. The five-stage divide-by-two link 109 is formed by cascading five divide-by-two dividers, and each divide-by-two divider uses current-mode logic (CML) to generate an output signal in the form of I/Q. It uses a 5-bit digital signal to control the opening of the first N ₁ (1≤N ₁ ≤5) stage divider by 2, so as to realize the frequency division output of the lowest division by 2 and the highest division by 32.

The second multiplexer 110 and the third multiplexer 112 are used for channel selection of the output signal of the five-stage divide-by-two link 109 . The input end of the second multiplexer 110 is connected with the output end of the five-stage division-by-two link 109, and the output end is connected with the receiver output buffer 111. Meanwhile, its operating state is affected by the output MUX2[ of the digital processor 116 4:0] control. The input end of the third multiplexer 112 is connected with the output end of the five-stage division-by-two link 109, and the output end is connected with the transmitter output buffer 113. Simultaneously, its operating state is controlled by the output MUX3 of the digital processor 116. [4:0] control. The second multiplexer 110 and the third multiplexer 112 are all composed of 5 buffers designed for different operating frequency bands, and they are respectively connected to the five-stage divide-by-two link 109 and each stage divides the divide-by-two frequency The output terminals of the buffers are each controlled by a 5-bit digital signal to open and close one of the buffers. When the first N ₁ (1≤N ₁ ≤5) stage divider by two of the five-stage divider by two link 109 is turned on, it means that the frequency synthesizer needs to select the frequency division result of the _N1th stage divider by two output, thus the second multiplexer 110 or the third multiplexer 112 in the second multiplexer 110 or third multiplexer 112, the buffer connected to the stage divider by two will be turned on, while the other buffers will be all turned off, thus achieving the desired frequency select.

To-receiver output buffer 111 and to-transmitter output buffer 113 are used to output the two signals to the receiver and the transmitter respectively. The input terminal to the receiver output buffer 111 is connected to the output terminal of the multiplexer 2 110, and the output terminal provides a local oscillator signal for an off-chip receiver. The input terminal to the transmitter output buffer 113 is connected to the output terminal of the multiplexer three 112, and the output terminal provides a local oscillator signal for the off-chip transmitter.

The input buffer 114 is used to receive an external input signal into the five-stage divide-by-two link 109 . The input end of the input buffer 114 is connected to the external signal input, and the output end is connected to the input end of the five-stage divide-by-two link 109 .

The main loop output buffer 108, to the receiver output buffer 110, and to the transmitter output buffer 112 can buffer the output signal, enhance its load capacity, and isolate the on-chip signal from the off-chip.

The input terminal of the nonvolatile memory 115 is connected to the output of the digital processor 116 , and the output terminal is connected to the input of the digital processor 116 . READ and WRITE respectively control the reading and writing process of the nonvolatile memory 115 .

The digital processor 116, its input end receives the programming configuration data of external input and the data read from the non-volatile memory 115, and the output end is connected with the programmable charge pump 102, the multi-channel voltage-controlled oscillator 104, the first multi-channel selector 105, programmable multimode divider 107, N stage divide-by-two link 109, second multiplexer 110, to receiver output buffer 111, third multiplexer 112, to transmitter The output buffer 113 and the input buffer 114 are connected. The digital processor 116 controls the digital configuration of the entire multi-standard performance reconfigurable I/Q quadrature carrier generator, and it also includes a ΣΔ modulator module, a frequency sampling module, a frequency comparison module, and a linear interpolation calculation module.

Based on the system block diagram of the multi-standard performance reconfigurable I/Q quadrature carrier generator shown in FIG. 1 , FIG. 2 shows an example circuit block diagram of the programmable charge pump 102 provided by the present invention. The charge pump is a fully differential charge pump with programmable current, and is composed of a programmable reference current module 201 and a charge pump core module 202 . The input signals UP and DN are provided by the frequency and phase detector 101 , and the output signals OUTP and OUTN are provided to the loop filter 103 . The programmable reference current module 201 is controlled by a 4-bit digital signal C[3:0] to realize the adjustment of the output reference current from the unit current I to 15I. The charge pump core module 202 is controlled by the input signals UP and DN. When UP is high, the output signals OUTP and OUTN charge the loop filter 103 to increase its output voltage; when DN is high, the output signals OUTP and OUTN OUTN discharges the loop filter 103 to lower its output voltage. The magnitude of the charging and discharging current is equal to the magnitude of the reference current provided by the programmable reference current 201 , and the loop bandwidth of the PLL can be adjusted by adjusting the magnitude of the charging and discharging current. The charges at the source terminals are respectively released through the tubes, which eliminates the charge sharing effect and effectively reduces the off-time of the current source. The respective switches in the current replication branch and their corresponding switches

Based on the system block diagram of the multi-standard performance reconfigurable I/Q quadrature carrier generator shown in FIG. 1 , FIG. 3 shows an example circuit diagram of the loop filter 103 provided by the present invention. The loop filter is a third-order low-pass filter with differential input and differential output, and loop characteristics such as loop bandwidth can be adjusted by adjusting device parameters. The input terminals CPOUT_P and CPOUT_N are respectively provided by the outputs OUTP and OUTN of the programmable charge pump 102 , while the output terminals VC_P and VC_N are provided to the multi-channel voltage controlled oscillator 104 as a control voltage. The loop filter 103 is composed of resistors R _P2 , R _P3 , R _N2 , R _N3 and capacitors C _P1 , C _P2 , C _P3 , C _N1 , C _N2 , C _N3 . Among them, one end of C _P1 , C _P2 and R _P3 is connected to CPOUT_P, and the other end of C _P1 is connected to GND (ground), the other end of C _P2 is connected to one end of R _P2 , and the other end of R _P3 is connected to VC_P Connect; one end of R _P2 is connected with _CP2 , and the other end is connected with GND; one end of CP3 is connected with VC_P, and the other end is connected with GND. One end of C _N1 , C _N2 , R _N3 is connected to CPOUT_N, the other end of C _N1 is connected to GND, the other end of C _N2 is connected to one end of R _N2 , the other end of R _N3 is connected to VC_N; the other end of R _N2 One end is connected to CN2, and the other end is connected to GND; one end of _CN3 is connected to _{VC_N} , and the other end is connected to GND. Based on the system block diagram of the multi-standard performance reconfigurable I/Q quadrature carrier generator described in Figure 1, Figure 4 provides an example circuit diagram of a voltage-controlled oscillator in the multi-channel voltage-controlled oscillator 104 provided by the present invention . The voltage controlled oscillator adopts NMOS, PMOS upper and lower complementary cross-coupling structures. It is composed of PMOS cross-coupled transistors M _p1 , M _p2 , NMOS cross-coupled transistors M _n1 , M _n2 , switch K, inductor L, 7-bit capacitor array 401 , and radio frequency MOS varactor module 402. Wherein, the sources of M _p1 and M _p2 are connected together and connected with one end of the switch K, and the other end of K is connected with the power supply voltage VDD. K is controlled by the output A[2] from the digital processor 116, when it is high, K is closed; when it is low, K is open, and the VCO will not work. The drain of _Mp1 is connected to the drain of _Mn1 , the gate of _Mn2 , and the gate of _Mp2 , and the gate is connected to the drain of _Mp2 , the drain of _Mn2 , and the gate of _Mn1 . The sources of _Mn1 and _Mn2 are connected together and connected to GND (ground). One end of the inductor L is connected to the drain of _Mp1 , and the other end is connected to the drain of _Mp2 . The output terminal OUT_P of the oscillating signal is connected to the drain of M _p1 , and OUT_N is connected to the drain of M _p2 , and both are connected to the input terminal of the first multiplexer 105 . One end of the 7-bit capacitor array 401 is connected to the drain of _Mp1 and the other end is connected to the drain of _Mp2 , which is controlled by the output B[6:0] from the digital processor 116, each of B[6:0] One bit respectively controls the on and off of a capacitor in the 7-bit capacitor array 401 . When a bit in B[6:0] changes from low to high, the corresponding capacitor is turned on, the overall capacitance value of the capacitor array increases, and the oscillation frequency of the voltage-controlled oscillator decreases; when B[6:0] When a certain bit changes from high to low, the corresponding capacitor is turned off, the overall capacitance value of the capacitor array decreases, and the oscillation frequency of the voltage-controlled oscillator increases, thus forming a coarse tuning of the oscillation frequency of the voltage-controlled oscillator. One end of the radio frequency MOS varactor module 402 is connected to the drain of Mp1, and the other end is connected to the drain of Mp2, and its capacitance value is controlled by the outputs _{VC_P} and _{VC_N} from the loop filter 103, VC_P and VC_N The change of MOS changes the capacitance value of the MOS varactor module 402, thereby adjusting the oscillation frequency of the voltage-controlled oscillator, forming a fine tuning of the oscillation frequency of the voltage-controlled oscillator. Since the tail current source tube and the bias circuit that provides bias to it are a large noise source, the 1/f noise of their tube will deteriorate the phase noise of the voltage controlled oscillator in the form of frequency mixing, so choose no tail current form; at the same time, this also increases the oscillation amplitude of the signal, which is beneficial to optimize the phase noise performance. The voltage-controlled oscillator uses a 7-bit capacitor array to divide the entire frequency band into 128 sub-bands, which reduces the gain of the voltage-controlled oscillator and expands the tuning range of the voltage-controlled oscillator; in addition, the varactor adopts an accumulative MOS varactor , the control voltage is input in a differential form, thereby extending the frequency coverage of each sub-band. The oscillation frequency range of the voltage-controlled oscillator covers 5-10GHz, and is characterized by high oscillation frequency, large tuning range and good phase noise performance.

Based on the system block diagram of the multi-standard performance reconfigurable I/Q quadrature carrier generator described in Figure 1, Figure 5 shows the frequency preset function that can be realized in the multi-channel voltage-controlled oscillator 104 provided by the present invention so as to realize An example circuit diagram of a mixed-signal voltage-controlled oscillator with fast loop lock. The mixed-signal voltage-controlled oscillator is composed of a preset module 501 and a voltage-controlled oscillator core 502 . The input end of the preset module 501 is connected with the output ends VC_P and VC_N of the loop filter 103, and the output end is connected with the input end of the strictly controlled oscillator core 502; at the same time, it receives the output signal P[ from the digital processor 116 5:0] control. The input end of voltage controlled oscillator core 502 is connected with the output end of preset module 501, and output end OUT_P and OUT_N are then connected with the input end of first multiplexer 105; Simultaneously, it receives the output signal from digital processor 116 Control of A[0] and B[6:0]. The structure of the voltage-controlled oscillator core 502 is the same as that of the voltage-controlled oscillator shown in FIG. 4. When A[0] is high, the voltage-controlled oscillator core starts to work; The controlled oscillator core stops working. B[6:0] controls the working state of the 7-bit capacitor array in the core of the voltage-controlled oscillator. The control signals P[5:0] and B[6:0] from the digital processor 116 jointly determine the output frequency of the VCO. When the multi-standard performance reconfigurable I/Q quadrature carrier generator selects the mixed-signal voltage-controlled oscillator in the multi-channel voltage-controlled oscillator 104 to work, there are two operating modes in the system, which are the operating modes 1 and working mode 2. In working mode 1, the preset module disconnects the control voltage input from the loop filter 103, and biases the input of the preset module to an internally generated fixed level, by adjusting the output P[ 5:0] and B[6:0], record the output frequency in turn, and write it into the non-volatile memory 115 . In this way, corresponding to each digital combination of P[5:0] and B[6:0], the voltage-controlled oscillator has a fixed frequency output. This is a frequency sampling process. In fact, we have obtained the mapping relationship between P[5:0], B[6:0] and the output frequency, and the mapping relationship is stored in the non-volatile memory 115 to avoid repeated calibration Increased workload and power loss. In operating mode 2, the input of the preset module is connected to the control voltage output from the loop filter 103 . The digital processor 116 extracts the mapping relationship stored in the non-volatile memory, and obtains the digital configuration P[5:0] and B[6:0] of the required frequency through the frequency comparison module and the linear interpolation calculation module, and is set P[5:0] and B[6:0] preset the output frequency of the mixed-signal voltage-controlled oscillator to a place very close to the required frequency, and then rely on the loop adjustment to achieve the final lock. When the frequency of the main loop needs to jump, the digital processor 116 adjusts P[5:0], B[6:0] and the control signal M[11:0] of the programmable multimode frequency divider 107, so that The output frequency of the mixed-signal voltage-controlled oscillator is preset to another frequency point in a short period of time, and the loop will be re-locked in a very short period of time because the control voltage changes very little. The characteristic of the mixed-signal voltage-controlled oscillator is that the loop lock time can be greatly reduced, but due to the existence of the preset module, the power consumption will increase and the phase noise performance will also decrease.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention, and are not intended to limit the present invention. Within the spirit and principles of the present invention, any modifications, equivalent replacements, improvements, etc., shall be included in the protection scope of the present invention.

Claims (6)

1. A multi-standard performance reconfigurable I/Q quadrature carrier generator, which adopts standard CMOS technology and is realized by monolithic integration, which includes: A frequency and phase detector (101) is used to compare the frequency and phase of the input reference signal and the output signal of the programmable multimode frequency divider (107); The programmable charge pump (102), controlled by the output signal of the frequency and phase detector (101), generates charging and discharging currents, and then charges and discharges the loop filter to change its output voltage; The loop filter (103) is used to convert the charging and discharging current of the programmable charge pump (102) into an analog voltage for controlling the multi-channel voltage-controlled oscillator (104); A multi-channel voltage-controlled oscillator (104), which is controlled by the analog voltage to generate the required phase-locked loop locking frequency range; The first multiplexer (105) is used to channel select the output signals of the multiple voltage-controlled oscillators (104), to determine which voltage-controlled oscillator provides the oscillation frequency; Divide by two prescaler (106), be used to divide the output signal from the first multiplexer (105) by two prescaler, to reduce the maximum operating frequency of programmable multimode frequency divider (107); A programmable multimode frequency divider (107), used to control the frequency division ratio of the main loop of the phase-locked loop, finally determines the locking frequency of the phase-locked loop; The main loop output buffer (108), used for outputting the phase locked loop main loop signal; The five-stage division-by-two link (109) is used to generate I/Q signals of 0.1 to 5 GHz, and output them to the receiver and the transmitter in two ways; The second multiplexer (110) and the third multiplexer (112), are used for carrying out the channel selection to the output signal of the five-stage divide-by-two frequency division link (109); To the receiver output buffer (111) and to the transmitter output buffer (113), for outputting the two-way signals to the receiver and the transmitter respectively; The input buffer (114) is used to receive the external input signal and enter the five-stage divide-by-two frequency link (109); Wherein, the programmable charge pump (102) is a charge pump that can be configured for charging and discharging current, its input end is connected with the output end of the frequency and phase detector (101), and the output end is connected with the input end of the loop filter (103) , its working state is controlled by the first output of the digital processor (116), thereby the loop bandwidth of the phase-locked loop can be adjusted by the digital processor (116); The multi-channel voltage-controlled oscillator (104) generates the required oscillating signals of 5-10 GHz and 1.5-3 GHz, and its oscillating frequency is jointly determined by the digital signals A, B, P and the output voltage of the loop filter (103). For the selection of the voltage-controlled oscillator, B is used for the selection of sub-bands, and P is used for the setting of the preset signal of the mixed-signal voltage-controlled oscillator including the frequency preset module. When A selects the mixed-signal voltage-controlled oscillator to work When , the preset module generates the control voltage according to the configuration of P and the output voltage from the loop filter to act on the core of the voltage-controlled oscillator, thereby generating the required oscillation frequency, where A, B and P are digital processors respectively the second, third and fourth outputs of (116); The multi-channel voltage-controlled oscillator (104) includes three mutually independent voltage-controlled oscillators, wherein the first voltage-controlled oscillator covers a frequency range of 5-10 GHz, the second voltage-controlled oscillator covers a frequency range of 1.5-3 GHz, and the third one covers a frequency range of 1.5-3 GHz. The voltage-controlled oscillator has a frequency preset function, which can realize fast locking and shorten the locking time, and a certain voltage-controlled oscillator is selected by the digital processor (116) to work to form the main loop of the phase-locked loop; The input end of the first multiplexer (105) is connected with the output end of the multi-channel voltage controlled oscillator (104), and the output end is respectively connected with the division by two prescaler (106), the five-stage division by two frequency link ( 109) and the input end of the main loop output buffer (108), its working state is controlled by the fifth output of the digital processor (116), and the first multiplexer (105) is designed for different operating frequency bands The buffers are combined in parallel, and each buffer is controlled by the fifth output of the digital processor (116), and can be opened or closed independently, and the buffer does not consume power consumption after being closed. 2. multi-standard performance reconfigurable type I/Q quadrature carrier generator according to claim 1, is characterized in that, an input end of frequency discrimination phase detector (101) is connected with external reference signal F _ref , in addition An input terminal is connected with the output signal F _div of the programmable multimode frequency divider (107), and the frequency and phase detector (101) produces corresponding pulse voltage signals according to the frequency difference and the phase difference of the two input signals, so as to Drive the charge pump to charge and discharge the loop filter (103). 3. multi-standard performance reconfigurable type I/Q quadrature carrier generator according to claim 1, is characterized in that, the input terminal of programmable multi-mode frequency divider (107) is divided with two prescaler (106 ), the output is connected to the input of the frequency and phase detector (101), and the operating state of the programmable multimode frequency divider (107) is controlled by the sixth output of the digital processor (116). 4. multi-standard performance reconfigurable type I/Q quadrature carrier generator according to claim 3, is characterized in that, five stages divide frequency division link (109) by two and are used to produce the I/Q of 0.1～5GHz signal, and output to the receiver and the transmitter respectively in two ways, the input end of the five-stage frequency division link (109) and the first multiplexer (105), the external signal input buffer (114) The output end is connected, and the output end is connected with the output end of the second multiplexer (110) and the third multiplexer (112) respectively, and the working state of the five-stage divide-by-two frequency division link (109) is controlled by the digital processor (116) Control of the seventh output. 5. multi-standard performance reconfigurable type I/Q quadrature carrier generator according to claim 4, is characterized in that, five stages divide frequency division link (109) by 5 divide frequency divider cascading by 2 Composition, the divider by two of each stage adopts current mode logic, which can generate an output signal in the form of I/Q, and the first N ₁ (1≤N ₁ ≤5) stage divides by two is controlled by a 5-bit digital signal The opener is turned on to realize the frequency division output of the lowest division by 2 and the highest division by 32. 6. multi-standard performance reconfigurable type I/Q quadrature carrier generator according to claim 5, is characterized in that, the second multiplexer (110) and the 3rd multiplexer (112) are all made of 5 buffers designed for different operating frequency bands constitute, these 5 buffers are respectively connected to the output end of each stage of the frequency divider of the five-stage divide-by-two link (109), each of which is composed of a 5-digit number The signal controls the opening and closing of one of the buffers. When the first N ₁ (1≤N ₁ ≤5) stage divide-by-two frequency divider of the five-stage divide-by-two link (109) is turned on, it means that the frequency synthesis The divider needs to select the frequency division result of the N _1st stage divider by two to output, so the second multiplexer (110) or the third multiplexer (112) is connected with this stage divider by two The buffer will be on, while the other buffers will all be off, enabling the selection of the desired frequency.