CN117254805B - SUB-1G full-frequency coverage frequency integrated circuit - Google Patents
SUB-1G full-frequency coverage frequency integrated circuit Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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Abstract
The invention belongs to the technical field of radio frequency communication chips, and particularly relates to a SUB-1G full-frequency coverage frequency integrated circuit which comprises a decimal phase-locked loop, a prescaler circuit, a digital logic module, a power amplifier and a quadrature mixer. The method has the advantages that when the chip is electrified, the maximum frequency and the minimum frequency of the phase-locked loop are measured and the corresponding algorithm is adopted, so that the influence of frequency range change caused by the deviation of inductance and capacitance values of the voltage-controlled oscillator is avoided, the seamless coverage of 120-960 MHz frequency range is realized under the condition of the frequency range of the minimum phase-locked loop voltage-controlled oscillator, the phase noise of the phase-locked loop is greatly improved due to the fact that the frequency range of the phase-locked loop is reduced through a self-adaptive frequency configuration mode and a flexible prescaled circuit, the anti-interference capability of the chip is greatly improved, and the seamless coverage of SUB-1G full frequency range is achieved by utilizing the matching of the frequency division ratio of the phase-locked loop and the prescaled circuit under the condition that excessive extra frequency allowance is not needed.
Description
Technical Field
The invention belongs to the technical field of radio frequency communication chips, and particularly relates to a SUB-1G full-frequency coverage frequency integrated circuit.
Background
According to the regulations of wireless communication in various countries, a plurality of SUB-bands are divided into a frequency band (SUB-1G) lower than 1GHz for various applications, and some are authorized bands for telecommunication, broadcasting, television, etc. Some are open bands such as: 315MHZ band, 433MHZ band, 868MHZ band, 915MHZ band, etc. Some are dedicated frequency bands such as 470-510 MHz for wireless meter reading, 840.5-845 MHz for unmanned aerial vehicle frequency bands, 174-216M, 230M, 407-425M, 608-630M for medical treatment, and the like. Since the SUB-1G coverage frequency is very large, the current technology generally designs chips for certain application frequency bands.
Such as the chip design shown in fig. 1. The high-frequency signal is generated through the decimal phase-locked loop, then the quadrature signal is obtained through the frequency division of the voltage-controlled oscillator through the prescaler circuit (comprising the IQ frequency divider 1, the IQ frequency divider 2, the frequency divider 2 and the MUX (multiplexer)), the I-path output signal ip/in and the Q-path output signal Qp/Qn are connected to the quadrature downmixing circuit IQ-MIXER, and the IQ frequency divider 1 realizes the frequency division of the voltage-controlled oscillator by 2. IQ divider 2 achieves a division by 2 of the output signal of IQ divider 1. And then through the selection of a multiplexer MUX, the quadrature frequency division by 2 times of the phase-locked loop signal is realized, and the frequency division by 4 times of the frequency division by 2 times is realized. The transmit signal of the PA is single-phase, so that divider 2 achieves a single-phase division by 2 or division by 4 of the phase-locked loop.
In the prior art, full coverage of the SUB-1G frequency band (120-960 MHz) is difficult, and only specific frequency bands can be covered.
In addition, the phase-locked loop is a main circuit of the frequency synthesis module, and as the frequency range of the phase-locked loop increases, the phase noise of the phase-locked loop will be greatly deteriorated. Since the inductance and capacitance of the voltage-controlled oscillator determine the frequency range, and the inductance and capacitance will vary by up to ±20% during mass production, a relatively large margin is required for the designed frequency range to stably cover the desired frequency band. And an excessive frequency range will have a great influence on the phase noise of the frequency-integrated phase-locked loop, and eventually worsens the anti-interference performance of the receiving chip.
Disclosure of Invention
The invention aims to provide a SUB-1G full-frequency coverage frequency integrated circuit, which achieves SUB-1G full-frequency band seamless coverage and maintains good phase noise performance by utilizing the matching of the phase-locked loop frequency and the frequency division ratio of a prescaler circuit under the condition of not needing excessive extra frequency allowance so as to solve the problems in the background technology.
In order to achieve the above purpose, the invention adopts the following technical scheme: the utility model provides a SUB-1G full frequency covers frequency integrated circuit, includes decimal phase-locked loop, prescaler circuit, digital logic module, power amplifier and quadrature mixer, wherein: the output signals vco_n and vco_p of the voltage-controlled oscillator of the decimal phase-locked loop are connected with a prescaler circuit; the TX signal output by the prescaler circuit is sent to a power amplifier, the Ip, in, qp and Qn signals output by the prescaler circuit are sent to a quadrature mixer, and the Cnt <23:0> output signal is connected with a digital logic module; the output signals Divn <2:0>, cnt_time and TRX_EN of the digital logic module are connected with a prescaler circuit; signals Ccap <7:0> and N.K output by the digital logic module are connected with a decimal phase-locked loop;
The prescaler circuit comprises a frequency divider 1, a frequency divider 2, an IQ frequency divider 1, an IQ frequency divider 2, a MUX and a counter, wherein: the output signals vco_n and vco_p of the voltage-controlled oscillator are connected with the frequency divider 1 and the IQ frequency divider 2, the vco_n is also connected to a counter circuit, and the counter is also provided with an input signal cnt_time and an output signal Cnt <23:0>; the input signal of the frequency divider 1 is connected with the output signal Divn <2:0> of the digital logic module and is used for setting the frequency dividing ratio of the frequency divider 1, the output signals Dp and Dn of the frequency divider 1 are connected with the IQ frequency divider 1, and the Dp signal is also connected with the frequency divider 2; the other two input signals of the frequency divider 2 are connected with output signals Divn <2:0> and TRX_EN of the digital logic module, and the output signals are Tx; the input signal TRX_EN of the IQ frequency divider 1 is used for closing the output signal of the IQ frequency divider 1, and the output signals I4n, I4p, Q4n and Q4p are connected with the MUX; the input signal TRX_EN of the IQ frequency divider 2 is used for closing the output of the IQ frequency divider 2, and the output is I6n, I6p, Q6n and Q6p which are connected with a MUX circuit; the input signals of the MUX select I4n, I4p, Q4n, Q4p or I6n, I6p, Q6n and Q6p to output according to the output signals Divn <2:0> of the digital logic module;
The output signal of the digital logic module comprises: the TRX_EN signal, divn <2:0> signals, and the Cnt_time signal, wherein: the TRX_EN signal is used for determining that the pre-frequency division is in a frequency division state of transmitting or receiving; the Divn <2:0> signals are used for setting the frequency division value of the pre-frequency division circuit to the voltage-controlled oscillator; the Cnt_time signal is a pulse signal with a fixed period, and is used for a counter circuit for pre-dividing frequency to count the Vco_n signal output by the voltage-controlled oscillator so as to obtain the maximum frequency and the minimum frequency of Vco;
the output signal of the digital logic module further comprises: ccap <7:0> signals and N.K signals, wherein: the Ccap <7:0> signal is used to coarse tune the VCO frequency; the N.K signal is used for setting the frequency division value of the decimal phase-locked loop; the Cnt <23:0> signals output by the counter are stored in a register and are used for calculating the setting of the frequency division value of the pre-frequency division and the setting of N.K of the phase-locked loop;
The Ccap <7:0> signal is a switch capacitance control bit of a voltage-controlled oscillator of the decimal phase-locked loop, the frequency of the voltage-controlled oscillator can be adjusted by setting the value of the Ccap <7:0> signal, the prescaler circuit is used for dividing the signal of the decimal phase-locked loop to a required radio frequency and is used for receiving a local oscillator mixing signal or transmitting a required radio frequency signal by the power amplifier PA, and the input of the prescaler circuit is the output signals vco_n and vco_p of the voltage-controlled oscillator and the output signal Divn <2:0> of the digital logic module; the output signals are differential signals Qp, qn for receiving the quadrature mixed I-path differential signals Ip, in and Q-path differential signals Qp, qn, and a single-ended signal TX for the power amplifier PA transmission.
Preferably, the frequency divider 1 is configured to divide 1-7 of the voltage-controlled oscillator output signals vco_n and vco_p.
The invention has the technical effects and advantages that: compared with the prior art, the SUB-1G full-frequency coverage frequency integrated circuit provided by the invention has the following advantages:
The invention avoids the influence of frequency range change caused by the deviation of inductance and capacitance values of the voltage-controlled oscillator by measuring the maximum frequency and the minimum frequency of the phase-locked loop and a corresponding algorithm when the chip is electrified, realizes seamless coverage of 120-960 MHz frequency band under the condition of the frequency range of the minimum voltage-controlled oscillator of the phase-locked loop, greatly improves the phase noise due to the reduction of the frequency range of the phase-locked loop by a self-adaptive frequency configuration mode and a flexible prescaler circuit, greatly improves the anti-interference capability of the chip, and achieves the seamless coverage of SUB-1G full frequency band by utilizing the matching of the frequency of the phase-locked loop and the prescaler circuit without excessive extra frequency allowance and maintains better phase noise performance.
Drawings
FIG. 1 is a diagram of a conventional RF chip frequency synthesis architecture;
FIG. 2 is a diagram of a full frequency coverage frequency synthesis circuit of the SUB-1G of the present invention;
FIG. 3 is a pre-frequency division circuit diagram of the present invention;
FIG. 4 is a flow chart of the operation of the fractional phase locked loop of the present invention;
FIG. 5 is a flow chart of a frequency configuration of the present invention;
Fig. 6 is a circuit diagram of a fractional phase locked loop.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. The specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention provides a SUB-1G full-frequency coverage frequency synthesis circuit as shown in fig. 2, which comprises a decimal phase-locked loop, a prescaler circuit, a digital logic module, a power amplifier and a quadrature mixer, wherein: the output signals vco_n and vco_p of the voltage-controlled oscillator of the decimal phase-locked loop are connected with a prescaler circuit; the TX signal output by the prescaler circuit is sent to a power amplifier, the Ip, in, qp and Qn signals output by the prescaler circuit are sent to a quadrature mixer, and the Cnt <23:0> output signal is connected with a digital logic module; the output signals Divn <2:0>, cnt_time and TRX_EN of the digital logic module are connected with a prescaler circuit; signals Ccap <7:0> and N.K output by the digital logic module are connected with a decimal phase-locked loop.
The prior art can know that the fractional phase-locked loop mainly comprises a frequency discrimination phase discrimination circuit, a charge pump, a filter circuit, a voltage-controlled oscillator, a feedback frequency divider and a fractional sigma delta modulator, and the fractional phase-locked loop has a lot of literature, and the conventional fractional phase-locked loop circuit is shown in fig. 6 and is not described herein.
In addition, the input of the decimal phase-locked loop is a reference frequency clock, the frequency division ratio (N.K), the switch capacitance control bit (Ccap <7:0 >) of the voltage-controlled oscillator of the phase-locked loop, and the output is the high-frequency signal output of the voltage-controlled oscillator of the phase-locked loop.
Since the frequency of the voltage controlled oscillator is determined by the inductance and capacitance in the circuit, the frequency of the voltage controlled oscillator can be adjusted by setting Ccap <7:0> values. In this embodiment Ccap <7:0> is the highest frequency when the minimum is 0. Ccap <7:0> is maximum, 255, and the frequency is lowest.
The prescaler circuit functions to divide the signal of the phase locked loop to the desired radio frequency for the received local oscillator mixing signal, or the PA to transmit the desired radio frequency signal. In order to achieve seamless coverage of SUB-1G full band (120 m-960 mhz), in this embodiment, the frequency of the pll is designed to be about 2.8-4.2 ghz, and the prescaler may be configured to divide by 4, 6, 8, 12, 16, 20, 24, and 28.
Any required radio frequency of 120M-1020MHZ can be obtained through the frequency configured by the phase-locked loop and different prescaler ratios. The input of the prescaler circuit is the high frequency signal output vco_n, vco_p of the voltage controlled oscillator, the output signal Divn <2:0> of the digital logic module, the transmit and receive control signal trx_en (1: transmit, 0: receive) due to the fixed time period signal cnt_time signal measuring the phase locked loop frequency. The output signals are differential signals Ip, in.q-path differential signals Qp, qn. for receiving the I-path of quadrature mixing and a single-ended signal TX for the transmission of the power amplifier PA. The prescaler also has a counter circuit which outputs a count Cnt <15:0> of the phase-locked loop signal for a given clock cycle.
The full coverage of the SUB-1G frequency band is realized, and the maximum frequency and the minimum frequency of the phase-locked loop and the corresponding algorithm are measured when the chip is electrified, so that the influence of frequency range change caused by the deviation of inductance and capacitance values of the voltage-controlled oscillator is avoided, and the 120-960 MHz frequency band is seamlessly covered under the condition of the frequency range of the minimum phase-locked loop voltage-controlled oscillator.
As shown in Table 1, the design obtains frequency ranges at different frequency divisions, and seamless coverage from 120M to 960MHz can be obtained from the table. That is, continuous coverage can be achieved by dividing the maximum frequency of the phase-locked loop by the minimum frequency of the phase-locked loop by more than 1.5, and the influence of process deviation in chip manufacturing is overcome.
TABLE 1
In table 1, the frequency range of the pll 2800-4200 MHZ can be obtained at different frequency dividing ratios, and the column of the frequency range I/Q.I/Q frequency (L) of the prescaled output signal represents the lowest frequency output by the prescaled circuit at the lowest frequency 2800MHZ at different frequency dividing ratios.
The I/Q frequency (H) column represents the highest frequency output by the prescaler circuit at the highest frequency 4200MHZ at the phase locked loop frequency at different division ratios.
The first column Divn <2:0> of table 1 is a register configuration value output by the logic control circuit, which corresponds to the frequency division ratio of the prescaler circuit, that is, when the frequency division value of the vco_p signal is configured to be 0 for the fractional pll output signal vco_n of fig. 2, for example, DIVN <2:0>, divx=4, and the frequency range of the signal that the pll can output through the prescaler circuit is 700 to 1050mhz. The continuous coverage of the sub-1g frequency band can be obtained through the configuration of different frequency division ratios and the configuration of different phase-locked loop frequencies.
Illustratively, the prescaler circuit, as shown in FIG. 3, comprises:
The frequency divider 1 is implemented to divide 1-7 of the voltage-controlled oscillator output signal vco_n, vco_p. The divide ratio is set by Divn <2:0> control bits according to table 1. The outputs of which are fed to frequency divider 2 and IQ frequency divider 1, respectively.
Divider 2, which achieves a division by 4 or a division by 6 of the divider output signal Dp when trx_en=1. The setting of the division ratio is set by Divn <2:0> control bits according to table 1. The output signal TX of the frequency divider 2 is fed to the power amplifier PA.
IQ divider 1, when trx_en=0 and divn <2:0> is not 1 (i.e., the division value is not 6) according to table 1, implements quadrature IQ4 division of the divider output signal Dp, dn (I-way and Q-way phase difference is 90 degrees). The output signals I4n, I4p, Q4n, Q4p of the IQ divider 1 are supplied to a multiplexing circuit (MUX). Wherein I4n and I4p are differential signals to each other, and Q4n and Q4p are differential signals to each other.
IQ divider 2, when trx_en=0 and at DIVN <2:0> =1 (i.e. division value 6), implements quadrature IQ6 division of voltage controlled oscillator output signal vco_n, vco_p (I-path and Q-path phase difference 90 degrees). The output signals I6n, I6p, Q6n, Q6p of the IQ divider 2 are supplied to a multiplexing circuit (MUX). Wherein I6n and I6p are differential signals to each other, and Q6n and Q6p are differential signals to each other.
A multiplexing circuit (MUX) selects the desired frequency dividing branch according to table 1.
When Divn <2:0> =1: ip=i6p, in=i6n, qp=q6p, qn=q6n. When Divn <2:0> is not 1: p=i4p, in=i4n, qp=q4p, qn=q4n.
The input of the counter is an output signal vco_n of a voltage-controlled oscillator of the phase-locked loop, when cnt_time is high, the counter starts to count a clock signal vco_n, when cnt_time is low, the counter stops counting, and the counting result is latched and output to Cnt <23:0>, and then the counter is cleared to count the next time. Cnt <23:0> is connected to the input of the digital control logic. Since the period of the count is known, the result of the count reflects the frequency value of the pll vco at different configuration capacitances.
As shown in fig. 3, the input signals vco_n, vco_p are connected to the frequency divider 1 and the frequency divider 2, and vco_n is further connected to a counter circuit, which further has an input signal cnt_time and an output signal Cnt <23:0>. The other input signal Divn <2:0> of divider 1 is used to set the division ratio of divider 1. The output signal Dp, dn of the frequency divider 1 is connected to the IQ frequency divider 1, and the Dp signal is also connected to the frequency divider 2. The other two input signals of divider 2 are Divn <2:0> and TRX_EN, the output signals of which are Tx. The input signal trx_en of the IQ divider 1 is used for turning off the output signal of the IQ divider, and the output signals I4n, I4p, Q4n, Q4p are connected to the MUX. The input signal TRX_EN of the IQ divider 2 is used to turn off the output of the divider 2, the outputs are I6n, I6p, Q6n, Q6p connected to the MUX circuit, the multiplexing circuit MUX selects I4n, I4p, Q4n, Q4p or I6n, I6p, Q6n, Q6p outputs according to the input signal Divn <2:0 >.
The digital logic block of fig. 2 outputs a trx_en signal for determining whether the prescaler is operating in a transmit or receive frequency division state, divn <2:0> for setting the frequency division value of the prescaler circuit to the VCO, a cnt_time signal for outputting a pulse signal of a fixed period, and a counter circuit for prescaler for counting the vco_n signal output from the VCO to obtain the maximum frequency and the minimum frequency of the VCO. The output Cnt <23:0> of the counter will be stored in a register for use in calculating the setting of the divide value of the prescaler and the setting of N.K of the phase locked loop. Ccap <7:0> of the digital logic block is used to coarse tune the VCO frequency and N.K is used to set the fractional pll divider value.
The working principle of digital logic is as follows: the maximum and minimum frequencies of the phase locked loop are measured at power up. The workflow is shown in fig. 4.
Firstly, the chip is electrified and initialized, and the phase-locked loop enters a working state.
The phase locked loop is disconnected, i.e. the voltage of the control VCO output by the loop filter of the phase locked loop is forced to an intermediate value of the regulation voltage, in this embodiment 0.7V.
Then Ccap <7:0> is set to 0, causing the phase-locked loop to output the highest frequency. Cnt_time of the digital logic module outputs a pulse of 1 uS. The counter counts during a pulse time of 1 us. After the pulse jumps down, the digital logic module stores the Cnt <23:0> latch into the register reg0, and the counter is reset.
Then, ccap <7:0> is set to 255, so that the phase-locked loop outputs the lowest frequency. Cnt_time of the digital logic module outputs a pulse of 1 uS. The counter counts during a pulse time of 1 us. After the pulse down edge, the digital logic module stores Cnt <23:0> latches into register reg 1.
The frequency configuration method includes the configuration of pre-dividing frequency, and the configuration of the frequency dividing ratio N.K of the fractional phase-locked loop, as shown in fig. 5.
The user configures the desired radio frequency RF and the logic control unit calculates the divide ratio of the prescaled frequency based on this frequency, as shown in fig. 5.
The logic control module reads out the maximum and minimum frequencies TMH and TML of the phase-locked loop measured when the chip is powered on from reg0 and reg 1.
The maximum and minimum frequencies of the phase-locked loop tested by each chip and flexible frequency division ratio setting can be adaptively searched by each chip to be suitable for the frequency division ratio of the chip and the corresponding phase-locked loop frequency. The frequency division ratio DIVX is calculated according to the following formula, and the value divn <2:0> is determined by table 1.
IF:TML<RF*4<TMHDIVX=4
ELSEIF:TML<RF*6<TMHDIVX=6
ELSEIF:TML<RF*8<TMHDIVX=8
ELSEIF:TML<RF*12<TMHDIVX=12
ELSEIF:TML<RF*16<TMHDIVX=16
ELSEIF:TML<RF*20<TMHDIVX=20
ELSEIF:TML<RF*24<TMHDIVX=24
ELSEIF:TML<RF*28<TMHDIVX=28；
The fractional pll divide ratio N.K value is calculated by the following formula. INT is a rounding function. RF is the desired radio frequency, ref is the phase locked reference frequency, typically the frequency of the chip crystal oscillator circuit. The calculated results N and K are the frequency division ratios of the fractional phase locked loop circuit. N is the integer part of the division ratio and K is the fractional part.
N=INT((RF*DIVX）/ref)
K=((RF*DIVX）/ref)-N)
The phase locked loop can be enabled to output the desired rf signal based on the setting divn <2:0>, n k, trx_en, etc.
By the self-adaptive frequency configuration mode and the flexible prescaler circuit, the minimum phase-locked loop frequency coverage range is achieved, and the seamless coverage of the SUB-1G frequency band is realized. The maximum ratio of the adjacent prescaled two frequency dividing ratios is 1.5, and continuous coverage can be realized as long as the maximum frequency of the phase-locked loop divided by the minimum frequency of the phase-locked loop is greater than 1.5 by matching with the self-adaptive frequency configuration mode of the application. The phase noise of the phase-locked loop is greatly improved due to the reduction of the frequency range of the phase-locked loop, and the anti-interference capability of the chip is greatly improved.
Finally, it should be noted that: the foregoing description is only illustrative of the preferred embodiments of the present invention, and although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described, or equivalents may be substituted for elements thereof, and any modifications, equivalents, improvements or changes may be made without departing from the spirit and principles of the present invention.
Claims (2)
1. The utility model provides a SUB-1G full frequency covers frequency integrated circuit which characterized in that includes decimal phase-locked loop, prescaler circuit, digital logic module, power amplifier and quadrature mixer, wherein: the output signals vco_n and vco_p of the voltage-controlled oscillator of the decimal phase-locked loop are connected with a prescaler circuit; the TX signal output by the prescaler circuit is sent to a power amplifier, the Ip, in, qp and Qn signals output by the prescaler circuit are sent to a quadrature mixer, and the Cnt <23:0> output signal is connected with a digital logic module; the output signals Divn <2:0>, cnt_time and TRX_EN of the digital logic module are connected with a prescaler circuit; signals Ccap <7:0> and N.K output by the digital logic module are connected with a decimal phase-locked loop;
The prescaler circuit comprises a frequency divider 1, a frequency divider 2, an IQ frequency divider 1, an IQ frequency divider 2, a MUX and a counter, wherein: the output signals vco_n and vco_p of the voltage-controlled oscillator are connected with the frequency divider 1 and the IQ frequency divider 2, the vco_n is also connected to a counter circuit, and the counter is also provided with an input signal cnt_time and an output signal Cnt <23:0>; the input signal of the frequency divider 1 is connected with the output signal Divn <2:0> of the digital logic module and is used for setting the frequency dividing ratio of the frequency divider 1, the output signals Dp and Dn of the frequency divider 1 are connected with the IQ frequency divider 1, and the Dp signal is also connected with the frequency divider 2; the other two input signals of the frequency divider 2 are connected with output signals Divn <2:0> and TRX_EN of the digital logic module, and the output signals are Tx; the input signal TRX_EN of the IQ frequency divider 1 is used for closing the output signal of the IQ frequency divider 1, and the output signals I4n, I4p, Q4n and Q4p are connected with the MUX; the input signal TRX_EN of the IQ frequency divider 2 is used for closing the output of the IQ frequency divider 2, and the output is I6n, I6p, Q6n and Q6p which are connected with a MUX circuit; the input signals of the MUX select I4n, I4p, Q4n, Q4p or I6n, I6p, Q6n and Q6p to output according to the output signals Divn <2:0> of the digital logic module;
The output signal of the digital logic module comprises: the TRX_EN signal, divn <2:0> signals, and the Cnt_time signal, wherein: the TRX_EN signal is used for determining that the pre-frequency division is in a frequency division state of transmitting or receiving; the Divn <2:0> signals are used for setting the frequency division value of the pre-frequency division circuit to the voltage-controlled oscillator; the Cnt_time signal is a pulse signal with a fixed period, and is used for a counter circuit for pre-dividing frequency to count the Vco_n signal output by the voltage-controlled oscillator so as to obtain the maximum frequency and the minimum frequency of Vco;
the output signal of the digital logic module further comprises: ccap <7:0> signals and N.K signals, wherein: the Ccap <7:0> signal is used to coarse tune the VCO frequency; the N.K signal is used for setting the frequency division value of the decimal phase-locked loop; the Cnt <23:0> signals output by the counter are stored in a register and are used for calculating the setting of the frequency division value of the pre-frequency division and the setting of N.K of the phase-locked loop;
The Ccap <7:0> signal is a switch capacitance control bit of a voltage-controlled oscillator of the decimal phase-locked loop, the frequency of the voltage-controlled oscillator can be adjusted by setting the value of the Ccap <7:0> signal, the prescaler circuit is used for dividing the signal of the decimal phase-locked loop to a required radio frequency and is used for receiving a local oscillator mixing signal or transmitting a required radio frequency signal by the power amplifier PA, and the input of the prescaler circuit is the output signals vco_n and vco_p of the voltage-controlled oscillator and the output signal Divn <2:0> of the digital logic module; the output signals are differential signals Qp, qn for receiving the quadrature mixed I-path differential signals Ip, in and Q-path differential signals Qp, qn, and a single-ended signal TX for the power amplifier PA transmission.
2. The SUB-1G full frequency coverage frequency synthesis circuit according to claim 1, wherein the frequency divider 1 is configured to divide 1-7 of the Vco output signals vco_n and vco_p.
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