CN107590100B - A method for inter-core data interaction of multi-core processor - Google Patents

Abstract

The invention discloses an inter-core data interaction method of a multi-core processor, which comprises the following steps: the multiple cores are connected in sequence to form a ring communication structure, wherein each core is connected with the shared data area; one core starts inter-core communication interruption and sends the inter-core communication interruption to the next core, the next core responds to the inter-core communication interruption, reading and/or writing operation is carried out on the shared data area during the interruption response period, and the inter-core communication interruption is sent to the next core along the annular communication structure after the interruption response period is finished; the above processes are circularly carried out along the annular communication structure, and in the circulating process, the data interaction among the cores is completed through the shared data area. The invention provides an internuclear data interaction method with high-speed and high-reliability data transmission function, which can ensure that the read-write operation of a shared data area is only one core at any time, thereby effectively breaking through the bottleneck that the internuclear data is easy to transmit errors, and being applicable to both the presence and absence of an operating system.

Description

A method for inter-core data interaction of multi-core processor

technical field

The present invention relates to the technical field of multi-core processors, and more particularly, the present invention relates to a method for data interaction between cores of a multi-core processor.

Background technique

At present, in various electrical appliances and various control systems, the use of multi-core processors has become very common. However, when the inter-core data exchange method is not appropriate, problems such as data transmission error and data processing speed reduction will be caused. The existing solution is to develop a mature operating system, such as Android, iOS, Windowsphone, etc. However, a mature operating system will occupy a lot of system resources, and will generate high research and development costs in the process of developing and optimizing the operating system.

Therefore, on the premise of not relying on a mature operating system, providing a method for inter-core data interaction with high reliability and high transmission rate has become a technical problem to be solved urgently by those skilled in the art and a focus of constant research.

SUMMARY OF THE INVENTION

In order to solve the problems of easy data transmission errors between cores of multi-core processors, low data processing speed, and system resources and cost constraints due to mature operating systems, the present invention innovatively proposes a high-speed, high-reliability data The inter-core data interaction method of the transfer function can effectively break through the bottleneck of easy data transmission errors between the cores. This method is applicable and easy to implement with or without an operating system.

In order to achieve the above technical purpose, the present invention discloses a method for inter-core data interaction of a multi-core processor, the method comprising the following steps:

Ring communication structure setting: a plurality of cores are connected in sequence and the tail core is connected with the head core to form a ring communication structure, and each core in the ring communication structure is connected to the shared data area respectively;

Start inter-core communication interruption: one core in the ring communication structure initiates the inter-core communication interruption, and sends the inter-core communication interruption to the next core in the ring communication structure;

Responding to the inter-core communication interrupt: the next core responds to the inter-core communication interrupt, and reads and/or writes the shared data area through the buffer in the core during the interrupt response period;

Circular inter-core communication interruption: After the read and/or write operation is finished, the inter-core communication interruption is sent to the next core along the ring communication structure; During the cycle, each core completes the inter-core data interaction through the shared data area.

The present invention innovatively designs an inter-core data interaction method based on a ring communication structure, which effectively completes the inter-core data interaction of a multi-core processor by cyclically performing interrupt sending, interrupt response, and data reading and writing processes. , thereby effectively avoiding the dependence of the existing technology on the mature operating system, breaking through the bottleneck of easy data transmission errors between cores, and achieving the technical purpose of high-speed and high-reliability transmission of data between cores.

Further, each core is provided with at least one of a type I buffer, a type II buffer, and a type III buffer;

The role of the type I buffer is to periodically write the low-priority interrupt or data that needs to be sent to other cores in the main process into the shared data area through the type I buffer; the core with the type I buffer receives the low priority. When the level interrupt or the data instruction sent by the main process, the cycle write operation is performed to the type I buffer, and the data used for the write operation comes from the low-priority interrupt or the main process; the core with the type I buffer When receiving a timing interrupt that initiates an inter-core communication interrupt or a high-priority interrupt that responds to an inter-core communication interrupt, perform a cyclic read operation on the type I buffer, and write the read data into the shared data area;

The role of the type II buffer is to randomly and aperiodically write the low-priority interrupt or the data that needs to be sent to other cores in the main process into the shared data area through the type II buffer; the core with the type II buffer When receiving a low-priority interrupt or a data command sent by the main process, a random write operation is performed on the type II buffer, and the data used for the write operation comes from the low-priority interrupt or the main process; it has the type II buffer When the core of the processor receives a timing interrupt that initiates an inter-core communication interrupt or a high-priority interrupt that responds to an inter-core communication interrupt, it performs a periodic cyclic read operation on the Type II buffer, and writes the read data to the shared data Area;

The role of the type III buffer is to interrupt the low priority or the main process receives data transmitted by other cores through the buffer; the core with the type III buffer receives the timing interrupt that initiates the inter-core communication interrupt or responds to the inter-core communication interrupt. When the high-priority interrupt occurs, the data transmitted by other cores in the shared data area is written into the buffer, and the data used for the write operation comes from the shared data area; the core with the type III buffer is responding to the low-priority interrupt. Or in the main process, perform random or periodic cyclic read operations on the buffer to read data transmitted by other cores.

Based on the above improved technical solution, the present invention innovatively designs various buffers for each core, thereby effectively improving the reliability and stability of the data reading and writing process, and avoiding possible read and write confusion.

Further, a type I write data identification, a type I data register unit and a type I data register backup unit are set in the type I buffer;

When performing a periodic cyclic write operation to the type I buffer, the type I write data flag is set, and then the data to be written is written into the type I data register unit, the type I write data flag is cleared, and then the data to be written is written. The data is written into the type I data register backup unit;

When performing a cyclic read operation on the type I buffer, judge the state of the type I write data flag: if the type I write data flag is cleared, read the data in the type I data register unit; if the type I write data flag state is set. bit, then read the data in the backup unit of type I data register.

Further, a type II write data identification, a type II data register unit and a new data identification are set in the type II buffer;

When a random write operation is performed on the type II buffer, the type II write data flag is set and the new data flag is set, the data to be written is written into the type II data register unit, and the type II write data flag is cleared;

When performing a periodic cyclic read operation on the type II buffer, determine the type II write data identification status and the new data identification status, and read the type II data if the conditions for the type II write data identification to be cleared and the new data identification to be set are met. The data in the register unit, the new data flag is cleared.

Further, set a rewrite flag and a type III data register unit in the type III buffer;

When the periodic cyclic write operation is performed on the type III buffer, the rewrite flag is set, and the data to be written is written into the type III data register unit;

When random or periodic cyclic read operation is performed on the type III buffer, the rewriting flag is cleared, and data is read from the type III data register unit.

Based on the above improved technical solution, the present invention realizes fast and efficient data interaction among multiple processors for various priority workflows. By setting up a special buffer, the smooth progress of read and write operations can be ensured and the problem of read and write confusion can be avoided.

Further, in the step of starting the communication interruption between the cores, one of the cores in the ring communication structure periodically starts the communication interruption between the cores; the timing interruption of starting the communication interruption between the cores in each core and the interruption of responding to the communication between the cores are both for each core. The highest priority interrupt other than the reset interrupt.

Further, the duration of the inter-core communication interruption timing is 1 ms.

Further, the number of cores of the multi-core processor is four cores.

Further, the processor is a DSP processor.

Further, the inter-core communication interruption is an IPC interruption.

The beneficial effects of the present invention are as follows: the present invention innovatively proposes an inter-core data exchange method with a high-speed and high-reliability data transfer function, which can ensure that the read and write operations on the shared data area at any time will only be performed by one core. , so that the present invention effectively breaks through the bottleneck of easy data transmission errors between cores, and the method is applicable with or without an operating system, and is easy to implement.

Description of drawings

FIG. 1 is a schematic flowchart of a method for data interaction between cores of a multi-core processor.

FIG. 2 is a schematic diagram of a state of data interaction between cores of a quad-core processor.

Detailed ways

The data interaction method between the cores of the multi-core processor of the present invention will be explained and described in detail below with reference to the accompanying drawings.

As shown in Figures 1 and 2, the present invention specifically discloses a method for data interaction between cores of a multi-core processor, which can effectively improve the rate and reliability of data transmission, and is suitable for data interaction between multi-core processors. The method specifically includes the following steps.

Ring communication structure setting: a plurality of cores are connected in sequence and the tail core is connected with the head core to form a ring communication structure, and each core in the ring communication structure is respectively connected with the shared data area. It should be understood that "tail core" and "head core" are used to distinguish different cores in order to describe the construction process of the ring communication structure clearly, rather than to limit a certain core in a multi-core processor. In the construction process of the specific implementation, The "head core" can be considered as the first core to be noticed, and the "tail core" is the last core to be noticed, and in the last step of construction, it is necessary to connect the "tail core" and the "first core" to satisfy the two The need for the user to be able to interrupt the communication.

Start the inter-core communication interruption: a core in the ring communication structure starts the inter-core communication interruption, in this embodiment, the inter-core communication interruption is an IPC interruption, and a core in the ring communication structure periodically starts the inter-core communication interruption, and the present invention In each core, the timing interrupt for initiating the inter-core communication interruption and for responding to the inter-core communication interruption are interrupts with the highest priority other than the reset interruption in each core. In this embodiment, the duration of the inter-core communication interruption timing may be 1ms. , of course, under the inspiration of the present invention, the specific timing duration can be reasonably set as required, and the inter-core communication interruption is sent to the next core in the ring communication structure. It should be understood that "a core in the ring communication structure" refers to any one of the multiple cores. During specific implementation, a core in the ring communication structure can be specified according to actual needs; "the next core" refers to The core next to the current core in the ring communication structure, as shown in Figure 2.

Responding to the Inter-Core Communication Interrupt: The next core responds to the inter-core communication interrupt and performs read and/or write operations to the shared data area through the buffer within the core during the interrupt response period. If there are multiple types of buffers in the core, the shared data area can be read and written by polling the various types of buffers. In this embodiment, three types of buffers are provided, and the specific description is as follows.

Specifically, in the process of performing a read operation and/or a write operation on the shared data area, that is, a write operation and/or a read operation on the core. In the present invention, each core is provided with at least one of a type I buffer, a type II buffer, and a type III buffer. The constraints are defined by the device.

The role of the type I buffer is to periodically write the low-priority interrupt or data that needs to be sent to other cores in the main process into the shared data area through the type I buffer; the core with the type I buffer receives the low priority. When the level interrupt or the data instruction sent by the main process, the cycle write operation is performed to the type I buffer, and the data used for the write operation comes from the low-priority interrupt or the main process; the core with the type I buffer When receiving a timing interrupt for initiating an inter-core communication interrupt or a high-priority interrupt for responding to an inter-core communication interrupt, a periodic read operation is performed on the type I buffer, and the read data is written into the shared data area.

More specifically, a type I write data flag, a type I data register unit and a type I data register backup unit are set in the type I buffer.

When the cyclic write operation is performed to the type I buffer, the type I write data flag is set, and then the data to be written is written into the type I data register unit, the type I write data flag is cleared, and then the data to be written is written. Write to the Type I data register backup unit.

When the type I buffer is read periodically, the state of the type I write data flag is judged: if the type I write data flag is cleared, the data in the type I data register unit is read; if the type I write data flag state is set, Then read the data in the backup unit of type I data register.

The role of the type II buffer is to randomly and aperiodically write the low-priority interrupt or the data that needs to be sent to other cores in the main process into the shared data area through the type II buffer; the core with the type II buffer When receiving a low-priority interrupt or a data command sent by the main process, a random write operation is performed on the type II buffer, and the data used for the write operation comes from the low-priority interrupt or the main process; it has the type II buffer When the core of the processor receives a timing interrupt that initiates an inter-core communication interrupt or a high-priority interrupt that responds to an inter-core communication interrupt, it performs a periodic cyclic read operation on the Type II buffer, and writes the read data to the shared data Area.

More specifically, a type II write data identifier, a type II data register unit and a new data identifier are set in the type II buffer.

When random write operation is performed to the type II buffer, the type II write data flag is set and the new data flag is set, the data to be written is written into the type II data register unit, and the type II write data flag is cleared.

When performing periodic cyclic read operation on the type II buffer, judge the state of the type II write data flag and the new data flag state. If the conditions for the type II write data flag to be cleared and the new data flag to be set are met, read the type II data register unit. If the above conditions are not met, the read operation will be canceled and the next step will be executed.

The role of the type III buffer is to interrupt the low priority or the main process receives data transmitted by other cores through the buffer; the core with the type III buffer receives the timing interrupt that initiates the inter-core communication interrupt or responds to the inter-core communication interrupt. When the high-priority interrupt occurs, the data transmitted by other cores in the shared data area is written into the buffer, and the data used for the write operation comes from the shared data area; the core with the type III buffer is responding to the low-priority interrupt. Or in the main process, perform random or periodic cyclic read operations on the buffer to read data transmitted by other cores.

More specifically, set the rewrite flag and the type III data register unit in the type III buffer;

When the periodic cyclic write operation is performed to the type III buffer, the rewrite flag is set, and the data to be written is written into the type III data register unit.

When random or cycle read operation is performed on the type III buffer, the rewrite flag is cleared and the data is read from the type III data register unit.

Circular inter-core communication interruption: After the read and/or write operation is finished, the inter-core communication interruption is sent to the next core along the ring communication structure; During the cycle, each core completes the inter-core data interaction through the shared data area. In this embodiment, as shown in FIG. 2 , the number of cores of the multi-core processor is four cores, and the processor is a DSP processor.

The invention has been verified for the first time in the laser strapdown inertial group equipment using the TI multi-core DSP chip TMS320C6674 as the controller. As shown in Figure 2, TMS320C6674 has four DSP processors (Core0~Core3), and each processor has an independent The bus and data storage space can run independently, and the four DSP processing can jointly access a shared data area and common peripherals. The specific implementation process of this embodiment is as follows:

(1) Core1 uses a 1ms timer to regularly read and write the shared data area through the necessary buffer, and at the same time starts the Core1->Core2IPC interrupt;

(2) Core2 responds to the IPC interrupt, reads and writes the IPC shared data area through the necessary buffer, and starts the Core2—>Core3 IPC interrupt;

(3) Core3 responds to the IPC interrupt, reads and writes the IPC shared data area through the necessary buffer, and starts the Core3—>Core0 IPC interrupt;

(4) Core0 responds to the IPC interrupt, reads and writes the IPC shared data area through the necessary buffer, and starts the Core0—>Core1 IPC interrupt;

(5) Core1 responds to the IPC interrupt, and marks the necessary event record for the inter-core communication.

This inter-core communication method effectively solves a series of problems encountered in the research and development of laser strapdown inertial group equipment, such as abnormal inter-core interaction data, too slow fast data processing, and excessive memory resource consumption. Experiments have verified that this communication method is reliable. and high speed.

In addition, the terms "Class I" and "Class II" are used for descriptive purposes only, and should not be understood as indicating or implying relative importance or implying the number of technical features indicated. Thus, a feature defined as "Class I", "Class II" may expressly or implicitly include at least one of that feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise expressly and specifically defined.

In the present invention, unless otherwise expressly specified and limited, the terms "installed", "connected", "connected", "fixed" and other terms should be understood in a broad sense, for example, it may be a fixed connection or a detachable connection , or integrated; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between the two elements, unless otherwise specified limit. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

In the description of this specification, reference to the terms "this embodiment", "one embodiment", "some embodiments", "example", "specific example", or "some examples" or the like is meant to be combined with the description of the embodiment A particular feature, structure, material or characteristic described or exemplified is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, those skilled in the art may combine and combine the different embodiments or examples described in this specification, as well as the features of the different embodiments or examples, without conflicting each other.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements and simple improvements made in the essence of the present invention should be included in the protection scope of the present invention. Inside.

Claims (9)

1. A method for data interaction between cores of a multi-core processor, characterized in that: the method comprises the steps: Ring communication structure setting: a plurality of cores are connected in sequence and the tail core is connected with the head core to form a ring communication structure, and each core in the ring communication structure is connected to the shared data area respectively; Start inter-core communication interruption: one core in the ring communication structure initiates the inter-core communication interruption, and sends the inter-core communication interruption to the next core in the ring communication structure; Responding to the inter-core communication interrupt: the next core responds to the inter-core communication interrupt, and reads and/or writes the shared data area through the buffer in the core during the interrupt response period; Circular inter-core communication interruption: After the read and/or write operation is finished, the inter-core communication interruption is sent to the next core along the ring communication structure; During the cycle, each core completes the inter-core data interaction through the shared data area; Wherein, each core is provided with at least one of a type I buffer, a type II buffer, and a type III buffer; The role of the type I buffer is to periodically write the low-priority interrupt or data that needs to be sent to other cores in the main process into the shared data area through the type I buffer; the core with the type I buffer receives the low priority. When the level interrupt or the data instruction sent by the main process, the cycle write operation is performed to the type I buffer, and the data used for the write operation comes from the low-priority interrupt or the main process; the core with the type I buffer When receiving a timing interrupt that initiates an inter-core communication interrupt or a high-priority interrupt that responds to an inter-core communication interrupt, perform a cyclic read operation on the type I buffer, and write the read data into the shared data area; The role of the type II buffer is to randomly and aperiodically write the low-priority interrupt or the data that needs to be sent to other cores in the main process into the shared data area through the type II buffer; the core with the type II buffer When receiving a low-priority interrupt or a data command sent by the main process, a random write operation is performed on the type II buffer, and the data used for the write operation comes from the low-priority interrupt or the main process; it has the type II buffer When the core of the processor receives a timing interrupt that initiates an inter-core communication interrupt or a high-priority interrupt that responds to an inter-core communication interrupt, it performs a periodic cyclic read operation on the Type II buffer, and writes the read data to the shared data Area; The role of the type III buffer is to interrupt the low priority or the main process receives data transmitted by other cores through the buffer; the core with the type III buffer receives the timing interrupt that initiates the inter-core communication interrupt or responds to the inter-core communication interrupt. When the high-priority interrupt occurs, the data transmitted by other cores in the shared data area is written into the buffer, and the data used for the write operation comes from the shared data area; the core with the type III buffer is responding to the low-priority interrupt. Or in the main process, perform random or periodic cyclic read operations on the buffer to read data transmitted by other cores. 2. The method for data interaction between cores of a multi-core processor according to claim 1, wherein the type I write data identification, the type I data register unit and the type I data register backup unit are set in the type I buffer ; When performing a periodic cyclic write operation to the type I buffer, the type I write data flag is set, and then the data to be written is written into the type I data register unit, the type I write data flag is cleared, and then the data to be written is written. The data is written into the type I data register backup unit; When performing a cyclic read operation on the type I buffer, judge the state of the type I write data flag: if the type I write data flag is cleared, read the data in the type I data register unit; if the type I write data flag state is set. bit, then read the data in the backup unit of type I data register. 3. The method for data interaction between cores of a multi-core processor according to claim 2, characterized in that: a class II write data identification, a class II data register unit and a new data identification are set in the class II buffer; When a random write operation is performed on the type II buffer, the type II write data flag is set and the new data flag is set, the data to be written is written into the type II data register unit, and the type II write data flag is cleared; When performing a periodic cyclic read operation on the type II buffer, determine the type II write data identification status and the new data identification status, and read the type II data if the conditions for the type II write data identification to be cleared and the new data identification to be set are met. The data in the register unit, the new data flag is cleared. 4. The method for data interaction between cores of a multi-core processor according to claim 3, characterized in that: a rewrite flag and a type III data register unit are set in the type III buffer; When the periodic cyclic write operation is performed on the type III buffer, the rewrite flag is set, and the data to be written is written into the type III data register unit; When random or periodic cyclic read operation is performed on the type III buffer, the rewriting flag is cleared, and data is read from the type III data register unit. 5. The method for data interaction between cores of a multi-core processor according to any one of claims 1-4, wherein: In the step of initiating inter-core communication interruption, one of the cores in the ring communication structure periodically initiates inter-core communication interruption; In each core, the timing interrupt for initiating the inter-core communication interruption and for responding to the inter-core communication interruption are interrupts with the highest priority except the reset interrupt in each core. 6 . The method for inter-core data interaction of a multi-core processor according to claim 5 , wherein the duration of the inter-core communication interruption timing is 1 ms. 7 . 7 . The method for data interaction between cores of a multi-core processor according to claim 1 or 6 , wherein the number of cores of the multi-core processor is four cores. 8 . 8 . The method for inter-core data interaction of a multi-core processor according to claim 7 , wherein the processor is a DSP processor. 9 . 9 . The method for inter-core data interaction of a multi-core processor according to claim 1 or 8 , wherein the inter-core communication interruption is an IPC interruption. 10 .

Images