CN118606257B - Multi-core system, communication method thereof, control device and storage medium - Google Patents

Abstract

The embodiment of the invention discloses a multi-core system, a communication method, a control device and a storage medium thereof, wherein the multi-core system comprises: a plurality of processing units; the data interaction units are in one-to-one correspondence with the processing units, each data interaction unit comprises a sending unit and a receiving unit which are respectively connected with the corresponding processing units, the sending unit in each data interaction unit is connected with the receiving unit, and the sending unit in each data interaction unit is connected with the receiving unit in the adjacent data interaction unit, so that the plurality of data interaction units are connected in series to form a closed serial bus; the communication data generated by the initial processing unit are sequentially transmitted through the plurality of data interaction units until the communication data are transmitted to the target processing unit, and the initial processing unit and the target processing unit are any two of the plurality of processing units. The embodiment of the invention can realize low bus complexity, simple circuit structure, small hardware area, good expandability and low expansion cost.

Description

A multi-core system and its communication method, control device and storage medium

Technical Field

The present invention relates to the field of electronic related technologies, and in particular to a multi-core system and a communication method, a control device and a storage medium thereof.

Background Art

With the rapid development of new energy and robotics technology, the amount of information processed and the difficulty have also greatly increased, which has put forward higher requirements for computing power and product iteration. The computing power must meet the standards, and the speed of product release must also keep up. In existing technologies, multi-core processing is usually used to improve computing power. For multi-core systems, parallel port expansion is usually used, such as bus protocol (Advanced eXtensible Interface, AXI) or other parallel communications for inter-core exchange. Although the problem of communication speed is solved, as the number of cores increases, the complexity of the bus also increases exponentially, the hardware area is large, and the communication speed will begin to decrease. If the usual design scheme is adopted, the product iteration speed is slow and cannot meet the product iteration speed requirements.

Summary of the invention

The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a multi-core system with low bus complexity, simple circuit structure, small hardware area, good scalability and low expansion cost.

The present invention also provides a communication method, a control device and a computer-readable storage medium for a multi-core system.

A multi-core system according to a first aspect of the present invention includes:

Multiple processing units;

A plurality of data interaction units corresponding one to one with the plurality of processing units, each of the data interaction units comprising a sending unit and a receiving unit respectively connected to the corresponding processing units, the sending unit in each of the data interaction units being connected to the receiving unit, and the sending unit in each of the data interaction units being connected to the receiving unit in an adjacent data interaction unit, so that the plurality of data interaction units are connected in series to form a closed serial bus; the communication data generated by the initial processing unit is transmitted in sequence through the plurality of data interaction units according to the target frame marking information for identifying the target processing unit contained in the communication data, until it is transmitted to the target processing unit, the initial processing unit and the target processing unit being any two of the plurality of processing units.

The multi-core system according to the embodiment of the present invention has at least the following beneficial effects:

By connecting multiple data exchange units in series to form a closed serial bus, the communication data generated by the initial processing unit can be transmitted in sequence through the multiple data exchange units until it is transmitted to the target processing unit, and the communication data of the multiple processing units can only be transmitted unidirectionally in this serial bus. Compared with the traditional parallel port expansion method, the multi-core system of the embodiment of the present invention has only one closed serial bus no matter how many processing units are added, with low bus complexity, simple circuit structure, small hardware area, good scalability, low expansion cost, and unidirectional data flow, good data transmission stability and high reliability.

According to some embodiments of the present invention, each of the sending units includes:

A sending controller, comprising a first connection end, a second connection end and a third connection end, wherein the first connection end is used to receive the communication data sent by the corresponding processing unit;

a clock management unit, whose input end is connected to the second connection end, and the clock management unit is used to provide a clock signal;

A sending data buffer, comprising a first data interaction end and a first data output end, wherein the first data interaction end is connected to the third connection end, and the sending data buffer is used to store the communication data sent by the sending controller;

A protocol conversion unit, whose input end is connected to the first data output end, and the protocol state machine is used to convert the communication data sent by the sending data buffer into a preset frame format to obtain an initial data frame;

A serial conversion unit is connected to the output end of the clock management unit and the output end of the protocol conversion unit respectively, and is used to serialize the initial data frame to obtain a serial data frame, and send the serial data frame and the clock signal to the receiving unit in the next data exchange unit.

According to some embodiments of the present invention, each of the receiving units comprises:

A parallel conversion unit, configured to receive the serial data frame and the clock signal sent by the sending unit in the previous data exchange unit, and convert the serial data frame into a parallel data frame;

A protocol parsing unit, used for parsing the parallel data frames and restoring them to the communication data;

A receiving data buffer, used for storing the communication data sent by the protocol parsing unit; the communication data includes target frame marking information for identifying a target processing unit;

A receiving controller having a fourth connection end, a fifth connection end, a sixth connection end and a seventh connection end, wherein the fourth connection end is connected to the corresponding processing unit, the fifth connection end is connected to the receiving data buffer, and the sixth connection end is connected to the sending controller of the sending unit in the current data exchange unit; the receiving controller is used to send the communication data to the current processing unit for data processing when the target frame mark information is equal to the current frame mark information of the current processing unit, or send the communication data to the sending unit in the current data exchange unit when the target frame mark information is not equal to the current frame mark information, so as to send the communication data to the receiving unit in the next data exchange unit through the sending unit in the current data exchange unit until the communication data is transmitted to the target processing unit;

The watchdog unit is connected to the parallel conversion unit and the seventh connection end respectively.

The communication method of a multi-core system according to the second aspect of the present invention is applied to the multi-core system as described in the first aspect of the present invention, and the communication method of the multi-core system includes:

Acquire a target data frame sent by the sending unit in the previous data exchange unit and current frame marking information of the current processing unit, wherein the target data frame includes target frame marking information for identifying a target processing unit;

If the target frame mark information is equal to the current frame mark information, sending the target data frame to the current processing unit for data processing;

If the target frame marking information is not equal to the current frame marking information, the target data frame is sent to the sending unit in the current data interaction unit, so as to be sent to the receiving unit in the next data interaction unit through the sending unit in the current data interaction unit until the target data frame is transmitted to the target processing unit.

The communication method of the multi-core system according to the embodiment of the present invention has at least the following beneficial effects:

By connecting multiple data interaction units in series to form a closed serial bus, the communication data of multiple processing units can only be transmitted unidirectionally in this serial bus. The destination of the target data frame is determined by confirming whether the target frame marking information in the received target data frame is consistent with the current frame marking information of the current processing unit. If they are consistent, the target data frame is sent to the current processing unit for data processing. If they are inconsistent, the target data frame is sent to the next data interaction unit until the target data frame is transmitted to the target processing unit. This not only ensures low bus complexity, simple circuit structure, small hardware area, good scalability and low expansion cost, but also ensures that the data is correctly transmitted to the target processing unit for processing, and the data transmission stability and reliability are high.

According to some embodiments of the present invention, before acquiring the target data frame sent by the sending unit in the previous data exchange unit and the current frame marking information of the current processing unit, the communication method of the multi-core system further includes:

Acquire a target diagnosis frame sent by the sending unit in the previous data exchange unit, wherein the target diagnosis frame includes diagnosis identification information and is generated by a host, which is any one of the multiple processing units;

If the diagnostic identification information is equal to the preset diagnostic value, the target diagnostic frame is sent to the sending unit in the current data interaction unit, so as to be sent to the receiving unit in the next data interaction unit through the sending unit in the current data interaction unit, until the target diagnostic frame is transmitted to the receiving unit in the data interaction unit corresponding to the host.

According to some embodiments of the present invention, the communication method of the multi-core system further includes:

If the host receives the target diagnostic frame within a preset time period after sending the target diagnostic frame, the host sends the target data frame to the next data exchange unit;

If the host fails to receive the target diagnostic frame within a preset time period after sending the target diagnostic frame, a system error signal is generated.

According to some embodiments of the present invention, after sending the target data frame to the sending unit in the current data exchange unit, the communication method of the multi-core system further includes:

The sending unit in the current data exchange unit sends a clock signal to the receiving unit in the next data exchange unit to perform clock synchronization;

The sending unit in the current data exchange unit sends the target data frame to the receiving unit in the next data exchange unit.

According to some embodiments of the present invention, the sending unit in the current data exchange unit sends the target data frame to the receiving unit in the next data exchange unit, including:

The sending unit in the current data exchange unit splits the target data frame into a first data frame and a second data frame;

The first data frame is sent to the receiving unit in the next data exchange unit at the rising edge of the clock signal, and the second data frame is sent to the receiving unit in the next data exchange unit at the falling edge of the clock signal.

According to the third aspect of the present invention, the control device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the communication method of the multi-core system as described in the second aspect of the present invention when executing the computer program. Since the control device adopts all the technical solutions of the communication method of the multi-core system of the above embodiment, it has at least all the beneficial effects brought by the technical solutions of the above embodiment.

The computer-readable storage medium according to the fourth aspect of the present invention stores computer-executable instructions, and the computer-executable instructions are used to execute the communication method of the multi-core system as described in the second aspect of the present invention. Since the computer-readable storage medium adopts all the technical solutions of the communication method of the multi-core system of the above embodiment, it has at least all the beneficial effects brought by the technical solutions of the above embodiment.

Other features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and/or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

FIG1 is a system block diagram of a multi-core system according to an embodiment of the present invention;

FIG2 is a system block diagram of a sending unit according to an embodiment of the present invention;

FIG3 is a system block diagram of a receiving unit according to an embodiment of the present invention;

FIG4 is a schematic diagram of data transmission between two data exchange units according to an embodiment of the present invention;

5 is a waveform diagram of a target data frame and a clock signal according to an embodiment of the present invention;

FIG6 is a flow chart of a communication method for a multi-core system according to an embodiment of the present invention;

7 is a flow chart of a communication method for a multi-core system according to another embodiment of the present invention;

FIG8 is a flow chart of a communication method for a multi-core system according to another embodiment of the present invention;

9 is a flow chart of a communication method for a multi-core system according to another embodiment of the present invention;

FIG. 10 is a flow chart of a target data frame splitting and transmission process according to an embodiment of the present invention.

Reference numerals:

Processing unit 100;

The transmitting unit 200, the transmitting controller 210, the clock management unit 220, the transmitting data buffer 230, the protocol conversion unit 240, and the serial conversion unit 250;

The receiving unit 300 , the parallel conversion unit 310 , the protocol analysis unit 320 , the receiving data buffer 330 , the receiving controller 340 , and the watchdog unit 350 .

DETAILED DESCRIPTION

Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

In the description of the present invention, if there is a description of first, second, etc., it is only for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

In the description of the present invention, it should be understood that descriptions involving orientation, such as orientation or positional relationship indicated as up, down, etc., are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

In the description of the present invention, it should be noted that, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific content of the technical solution.

The multi-core system of an embodiment of the present invention will be clearly and completely described below in conjunction with Figures 1 to 10. Obviously, the embodiment described below is only a part of the embodiments of the present invention, not all of the embodiments.

According to the multi-core system of the first aspect of the present invention, the embodiment includes a plurality of processing units 100, and a plurality of data exchange units corresponding to the plurality of processing units 100. Each data exchange unit includes a sending unit 200 and a receiving unit 300 respectively connected to the corresponding processing unit 100, the sending unit 200 in each data exchange unit is connected to the receiving unit 300, and the sending unit 200 in each data exchange unit is connected to the receiving unit 300 in the adjacent data exchange unit, so that the plurality of data exchange units are connected in series to form a closed serial bus; the communication data generated by the initial processing unit 100 is transmitted in sequence through the plurality of data exchange units according to the target frame marking information for identifying the target processing unit 100 contained in the communication data, until it is transmitted to the target processing unit 100, and the initial processing unit 100 and the target processing unit 100 are any two of the plurality of processing units 100.

The communication data generated by the initial processing unit 100 includes target frame marking information for identifying the target processing unit 100. The communication data is sent in sequence to the sending unit 200 in the data interaction unit corresponding to the initial processing unit 100, and is sent to the receiving unit 300 in the next-level data interaction unit. The receiving unit 300 in the next-level data interaction unit determines whether the target frame marking information is equal to the current frame marking information of the processing unit 100 corresponding to the data interaction unit at this level. If the target frame marking information is equal to the current frame marking information, the communication data is sent to the processing unit 100 corresponding to the data interaction unit at this level for data processing; if the target frame marking information is not equal to the current frame marking information, the communication data is sent to the sending unit 200 in the data interaction unit at this level, so as to be sent to the receiving unit 300 in the next data interaction unit through the sending unit 200 in the data interaction unit at this level, until the communication data is transmitted to the target processing unit 100.

The communication data includes a target diagnostic frame and a target data frame. The serial bus of the multi-core system of the embodiment of the present invention is an expandable bus. After the processing unit 100 expanded on the original multi-core system is connected to the serial bus, it is necessary to confirm before data communication to prevent connection errors or timing deviations caused by changes in the external environment from affecting communication. Before data communication, the host sends a target diagnostic frame (diagnostic identification information is 0000) to the next level processing unit 100. After each level of processing unit 100 receives the target diagnostic frame and confirms that the diagnostic identification information is 0000, it is transmitted to the next level and then transmitted back to the host in sequence. When the host does not receive the target diagnostic frame (diagnostic identification information is 0000), it is judged that the connection is wrong, the system is wrong, and data communication cannot be performed. Otherwise, the normal communication process of the target data frame can be performed.

It should be noted that the diagnosis identification information needs to be distinguished from the target frame marking information. The specific diagnosis identification information and target frame marking information can be defined as needed and are not limited here.

In one embodiment, the A processing unit 100 generates a target diagnostic frame, the target diagnostic frame includes diagnostic identification information, the A processing unit 100 sends the target diagnostic frame to the B receiving unit 300 through the A sending unit 200, the B receiving unit 300 confirms that the diagnostic identification information is equal to the preset diagnostic value, and then sends the target diagnostic frame to the B sending unit 200, and then sends it to the C receiving unit 300 through the B sending unit 200, and the C receiving unit 300 confirms whether the diagnostic identification information is equal to the preset diagnostic value, and so on, until the N sending unit 200 sends the target diagnostic frame back to the A receiving unit 300. If the A processing unit 100 receives the target diagnostic frame within a preset time period after sending the target diagnostic frame, After receiving the target diagnostic frame, the target data frame is transmitted: the A processing unit 100 generates a target data frame, the target frame tag information contained in the target data frame indicates the ID number of the C processing unit 100, the A processing unit 100 sends the target data frame to the B receiving unit 300 through the A sending unit 200, the B receiving unit 300 confirms that the target frame tag information is not the ID number of the B processing unit 100, sends the target data frame to the B sending unit 200, and sends it to the C receiving unit 300 through the B sending unit 200, the C receiving unit 300 confirms that the target frame tag information is the ID number of the C processing unit 100, and sends the target data frame to the C processing unit 100 for processing. If the A processing unit 100 does not receive the target diagnostic frame within the preset time period after sending the target diagnostic frame, it means that the system has an error, and a system error signal is generated to remind the staff to perform maintenance.

The serial bus of the multi-core system of the embodiment of the present invention is integrated into the product, which not only has a simple interface, occupies fewer input and output interfaces, has good future scalability, and does not require logical expansion on the bus, thereby providing portability for chip design and reducing costs.

According to the multi-core system of the embodiment of the present invention, multiple data exchange units are connected in series to form a closed serial bus, so that the communication data generated by the initial processing unit 100 can be transmitted in sequence through multiple data exchange units until it is transmitted to the target processing unit 100, and the communication data of multiple processing units 100 can only be transmitted unidirectionally in this serial bus. Compared with the traditional parallel port expansion method, the multi-core system of the embodiment of the present invention has only one closed serial bus no matter how many processing units 100 are added, with low bus complexity, simple circuit structure, small hardware area, good scalability, low expansion cost, and unidirectional data flow, good data transmission stability and high reliability.

In some embodiments of the present invention, referring to FIG. 2 and FIG. 4 , each sending unit 200 includes a sending controller 210 , a clock management unit 220 , a sending data buffer 230 , a protocol conversion unit 240 and a serial conversion unit 250 .

The sending controller 210 has a first connection end, a second connection end and a third connection end, and the first connection end is used to receive the communication data sent by the corresponding processing unit 100;

A clock management unit 220, whose input end is connected to the second connection end, and the clock management unit 220 is used to provide a clock signal;

The sending data buffer 230 has a first data interaction end and a first data output end, the first data interaction end is connected to the third connection end, and the sending data buffer 230 is used to store the communication data sent by the sending controller 210;

A protocol conversion unit 240, whose input end is connected to the first data output end, and a protocol state machine is used to convert the communication data sent by the sending data buffer 230 into a preset frame format to obtain an initial data frame;

The serial conversion unit 250 is connected to the output end of the clock management unit 220 and the output end of the protocol conversion unit 240 respectively. The serial conversion unit 250 is used to serialize the initial data frame to obtain a serial data frame, and send the serial data frame and the clock signal to the receiving unit 300 in the next data exchange unit.

In an embodiment of the present invention, when the sending data buffer 230 is full, the sending controller 210 will provide interrupt feedback to prevent data overflow. The clock management unit 220 performs frequency division management on the system clock and provides clock signals to the serial conversion unit 250 and the protocol conversion unit 240. The protocol conversion unit 240 converts the communication data into an initial data frame. The preset frame format includes target frame marking information for identifying the target processing unit 100. Each processing unit 100 has its own unique frame marking information to determine which processing unit 100 the data to be sent is sent to for processing. Data is transmitted in parallel between the data exchange unit and the processing unit 100, and in serial between multiple data exchange units. The serial conversion unit 250 is required to serialize the data before sending it to the serial bus.

In some embodiments of the present invention, referring to FIGS. 2 to 4 , each receiving unit 300 includes a parallel conversion unit 310 , a protocol parsing unit 320 , a receiving data buffer 330 , a receiving controller 340 and a watchdog unit 350 .

The parallel conversion unit 310 is used to receive the serial data frame and the clock signal sent by the sending unit 200 in the previous data exchange unit, and convert the serial data frame into a parallel data frame;

The protocol parsing unit 320 is used to parse the parallel data frames and restore them to communication data;

The receiving data buffer 330 is used to store the communication data sent by the protocol parsing unit 320; the communication data includes the target frame marking information for identifying the target processing unit 100;

The receiving controller 340 has a fourth connection terminal, a fifth connection terminal, a sixth connection terminal and a seventh connection terminal, the fourth connection terminal is connected to the corresponding processing unit 100, the fifth connection terminal is connected to the receiving data buffer 330, and the sixth connection terminal is connected to the sending controller 210 of the sending unit 200 in the current data exchange unit; the receiving controller 340 is used to send the communication data to the current processing unit 100 for data processing when the target frame marking information is equal to the current frame marking information of the current processing unit 100, or, when the target frame marking information is not equal to the current frame marking information, send the communication data to the sending unit 200 in the current data exchange unit, so as to be sent to the receiving unit 300 in the next data exchange unit through the sending unit 200 in the current data exchange unit, until the communication data is transmitted to the target processing unit 100;

The watchdog unit 350 is connected to the parallel conversion unit 310 and the seventh connection terminal respectively.

The receiving controller 340 is connected to the sending controller 210 of the sending unit 200 in the current data interaction unit, so that when the target frame marking information is equal to the current frame marking information of the current processing unit 100, the communication data can be sent to the current processing unit 100 for data processing, or, when the target frame marking information is not equal to the current frame marking information, the communication data can be sent to the sending unit 200 in the current data interaction unit, so as to be sent to the receiving unit 300 in the next data interaction unit through the sending unit 200 in the current data interaction unit until the communication data is transmitted to the target processing unit 100, thereby ensuring that the data is correctly transmitted to the target processing unit 100 for processing, and the data transmission has good stability and high reliability.

The watchdog unit 350 includes a frame watchdog and a diagnostic watchdog. The frame watchdog is used to monitor the target data frame, and the diagnostic watchdog is used to monitor the target diagnostic frame, monitor the target data frame and the target diagnostic frame, and generate an interrupt to the receiving controller 340 once an error occurs to ensure the normal operation of the system. In some embodiments, it can be determined whether an error occurs by judging the frame length of the target data frame and the target diagnostic frame, wherein the normal frame lengths of the target data frame and the target diagnostic frame need to be distinguished to distinguish the target data frame from the target diagnostic frame. It can also be determined whether an error occurs by judging whether the time of receiving the target data frame and the target diagnostic frame is within the normal range, which cannot be regarded as a limitation of the present invention.

The communication method of a multi-core system according to an embodiment of the present invention will be described clearly and completely below in conjunction with FIG. 1 to FIG. 10 . Obviously, the embodiments described below are only part of the embodiments of the present invention, not all of them.

The communication method of a multi-core system according to the second aspect of the present invention is applied to the multi-core system of the first aspect of the present invention. The communication method of the multi-core system includes:

Acquire the target data frame sent by the sending unit 200 in the previous data exchange unit and the current frame marking information of the current processing unit 100, wherein the target data frame includes the target frame marking information for identifying the target processing unit 100;

If the target frame mark information is equal to the current frame mark information, the target data frame is sent to the current processing unit 100 for data processing;

If the target frame marking information is not equal to the current frame marking information, the target data frame is sent to the sending unit 200 in the current data interaction unit, so as to be sent to the receiving unit 300 in the next data interaction unit through the sending unit 200 in the current data interaction unit until the target data frame is transmitted to the target processing unit 100.

The target data frame generated by the initial processing unit 100 includes target frame marking information for identifying the target processing unit 100. The target data frame is sent in sequence to the sending unit 200 in the data interaction unit corresponding to the initial processing unit 100, and is sent to the receiving unit 300 in the next-level data interaction unit. The receiving unit 300 in the next-level data interaction unit determines whether the target frame marking information is equal to the current frame marking information of the processing unit 100 corresponding to the data interaction unit at this level. If the target frame marking information is equal to the current frame marking information, the target data frame is sent to the processing unit 100 corresponding to the data interaction unit at this level for data processing; if the target frame marking information is not equal to the current frame marking information, the target data frame is sent to the sending unit 200 in the data interaction unit at this level, so as to be sent to the receiving unit 300 in the next data interaction unit through the sending unit 200 in the data interaction unit at this level, until the target data frame is transmitted to the target processing unit 100.

In one embodiment, the A processing unit 100 generates a target data frame, and the target frame marking information contained in the target data frame represents the ID number of the C processing unit 100. The A processing unit 100 sends the target data frame to the B receiving unit 300 through the A sending unit 200. The B receiving unit 300 confirms that the target frame marking information is not the ID number of the B processing unit 100, and sends the target data frame to the B sending unit 200, and sends it to the C receiving unit 300 through the B sending unit 200. The C receiving unit 300 confirms that the target frame marking information is the ID number of the C processing unit 100, and sends the target data frame to the C processing unit 100 for processing.

According to the communication method of the multi-core system of the embodiment of the present invention, multiple data interaction units are connected in series to form a closed serial bus, and the communication data of multiple processing units 100 can only be transmitted unidirectionally in this serial bus. The destination of the target data frame is determined by confirming whether the target frame marking information in the received target data frame is consistent with the current frame marking information of the current processing unit 100. If they are consistent, the target data frame is sent to the current processing unit 100 for data processing. If they are inconsistent, the target data frame is sent to the next data interaction unit until the target data frame is transmitted to the target processing unit 100. This can not only ensure low bus complexity, simple circuit structure, small hardware area, good scalability and low expansion cost, but also ensure that the data is correctly transmitted to the target processing unit 100 for processing, and the data transmission stability and reliability are high.

In some embodiments of the present invention, referring to FIGS. 1 to 7 , before acquiring the target data frame sent by the sending unit 200 in the previous data exchange unit and the current frame marking information of the current processing unit 100, the communication method of the multi-core system further includes:

Acquire a target diagnosis frame sent by the sending unit 200 in the previous data exchange unit, where the target diagnosis frame includes diagnosis identification information and is generated by a host, which is any one of the multiple processing units 100;

If the diagnostic identification information is equal to the preset diagnostic value, the target diagnostic frame is sent to the sending unit 200 in the current data interaction unit, so as to be sent to the receiving unit 300 in the next data interaction unit through the sending unit 200 in the current data interaction unit, until the target diagnostic frame is transmitted to the receiving unit 300 in the data interaction unit corresponding to the host.

The serial bus of the multi-core system of the embodiment of the present invention is an expandable bus. After the processing unit 100 expanded on the original multi-core system is connected to the serial bus, it is necessary to confirm before data communication to prevent connection errors or timing deviations caused by changes in the external environment from affecting communication. Before data communication, the host sends a target diagnostic frame (diagnostic identification information is 0000) to the next level processing unit 100. After each level of processing unit 100 receives the target diagnostic frame and confirms that the diagnostic identification information is 0000, it is transmitted to the next level and then transmitted back to the host in sequence. When the host does not receive the target diagnostic frame (diagnostic identification information is 0000), it is judged that the connection is wrong, the system is wrong, and data communication cannot be performed. Otherwise, the normal communication process of the target data frame can be performed.

It should be noted that the diagnosis identification information needs to be distinguished from the target frame marking information. The specific diagnosis identification information and target frame marking information can be defined as needed and are not limited here.

In some embodiments of the present invention, referring to FIG. 1 , FIG. 3 and FIG. 8 , the communication method of the multi-core system further includes:

If the host receives the target diagnostic frame within a preset time period after sending the target diagnostic frame, it sends the target data frame to the next data exchange unit;

If the host fails to receive the target diagnostic frame within a preset time period after sending the target diagnostic frame, a system error signal is generated.

After the host sends the target diagnostic frame, the target diagnostic frame will be transmitted in sequence on the serial bus and finally returned to the host. The preset time period indicates the time it should take for the target diagnostic frame to return to the host under normal system operation. If the target diagnostic frame is received within the preset time period, it means that the multi-core system can communicate normally. If the target diagnostic frame is not received within the preset time period, it means that the system has an error and a system error signal is generated to remind the staff to perform maintenance.

In some embodiments of the present invention, referring to FIGS. 1 to 4 and 9 , after sending the target data frame to the sending unit 200 in the current data exchange unit, the communication method of the multi-core system further includes:

The sending unit 200 in the current data exchange unit sends a clock signal to the receiving unit 300 in the next data exchange unit to perform clock synchronization;

The sending unit 200 in the current data exchange unit sends the target data frame to the receiving unit 300 in the next data exchange unit.

The clock transmission is hierarchically synchronized, that is, the TCLK of the sending unit 200 of the previous level is transmitted to the RCLK of the receiving unit 300 of the next level, so that the data of each level is transmitted synchronously, and the delay deviation of each node is avoided when a single global clock (one TCLK is connected to all receiving units 300 and sending units 200) is used.

It can be understood that TCLK and RCLK are used to distinguish the clocks of the transmitting unit 200 and the next-stage receiving unit 300, and are substantially the same clock.

In some embodiments of the present invention, referring to FIGS. 1 to 5 and 10 , the sending unit 200 in the current data exchange unit sends the target data frame to the receiving unit 300 in the next data exchange unit, including:

The sending unit 200 in the current data exchange unit splits the target data frame into a first data frame and a second data frame;

The first data frame is sent to the receiving unit 300 in the next data exchange unit at the rising edge of the clock signal, and the second data frame is sent to the receiving unit 300 in the next data exchange unit at the falling edge of the clock signal.

In one embodiment of the present invention, as shown in Figure 5, the target data frame can be split into odd bits and even bits, the odd bits constitute the first data frame TData0, and the even bits constitute the second data frame TData1, and then at the rising edge t1 of the clock signal, the first data frame TData0 is sent to the receiving unit 300 in the next data exchange unit to become RData0, and at the falling edge t2 of the clock signal, the second data frame TData1 is sent to the receiving unit 300 in the next data exchange unit to become RData1. Splitting one data into two or more data can improve data transmission efficiency.

Here, it should be noted that the target data frame can also be split according to other rules, and the number of splits can be greater, which cannot be regarded as a limitation of the present invention. In addition, the second data frame TData1 can also be sent to the receiving unit 300 in the next data exchange unit as RData1 at the rising edge t1 of the clock signal, and the first data frame TData0 can be sent to the receiving unit 300 in the next data exchange unit as RData0 at the falling edge t2 of the clock signal, which cannot be regarded as a limitation of the present invention.

It can be understood that TData and RData are only used to distinguish the data sent by the sending unit 200 and the data received by the next-level receiving unit 300, and are essentially the same data, that is, TData0 and RData0 are the same data, and TData1 and RData1 are the same data.

In addition, an embodiment of the present invention further provides a control device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor. The processor and the memory may be connected via a bus or other means.

The memory, as a non-transient computer-readable storage medium, can be used to store non-transient software programs and non-transient computer executable programs. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely disposed relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

The non-transitory software program and instructions required to implement the communication method of the multi-core system in the above embodiment are stored in the memory, and when executed by the processor, the communication method of the multi-core system in the above embodiment is executed.

The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separated, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, an embodiment of the present invention also provides a computer-readable storage medium, which stores computer-executable instructions. The computer-executable instructions are executed by a processor or a controller, so that the processor or the controller can execute the communication method of the multi-core system in the above embodiment.

It will be appreciated by those skilled in the art that all or some of the steps and systems in the methods disclosed above may be implemented as software, firmware, hardware, and appropriate combinations thereof. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or transient medium). As known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

The embodiments of the present invention are described in detail above in conjunction with the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present invention.

Claims (8)

1. A multi-core system, comprising:

A plurality of processing units;

The data interaction units are in one-to-one correspondence with the processing units, each data interaction unit comprises a sending unit and a receiving unit which are respectively connected with the corresponding processing units, the sending unit in each data interaction unit is connected with the receiving unit, and the sending unit in each data interaction unit is connected with the receiving unit in the adjacent data interaction unit, so that the data interaction units are connected in series to form a closed serial bus; the communication data generated by the initial processing unit are sequentially transmitted through a plurality of data interaction units according to target frame marking information which is contained in the communication data and is used for marking a target processing unit until the communication data are transmitted to the target processing unit, and the initial processing unit and the target processing unit are any two of the plurality of processing units;

each of the transmitting units includes:

The transmission controller is provided with a first connecting end, a second connecting end and a third connecting end, and the first connecting end is used for receiving the communication data transmitted by the corresponding processing unit;

The input end of the clock management unit is connected with the second connecting end, and the clock management unit is used for providing clock signals;

The transmission data buffer is provided with a first data interaction end and a first data output end, the first data interaction end is connected with the third connecting end, and the transmission data buffer is used for storing the communication data transmitted by the transmission controller;

The input end of the protocol conversion unit is connected with the first data output end, and the protocol conversion unit is used for converting the communication data sent by the sending data buffer into a preset frame format to obtain an initial data frame;

The serial conversion unit is respectively connected with the output end of the clock management unit and the output end of the protocol conversion unit, and is used for serializing the initial data frame to obtain a serial data frame and transmitting the serial data frame and the clock signal to the receiving unit in the next data interaction unit;

each of the receiving units includes:

The parallel conversion unit is used for receiving the serial data frame and the clock signal sent by the sending unit in the last data interaction unit and converting the serial data frame into a parallel data frame;

A protocol analysis unit, configured to analyze the parallel data frame and restore the parallel data frame to the communication data;

A received data buffer for storing the communication data transmitted by the protocol parsing unit; the communication data includes target frame marking information for identifying a target processing unit;

The receiving controller is provided with a fourth connecting end, a fifth connecting end, a sixth connecting end and a seventh connecting end, wherein the fourth connecting end is connected with the corresponding processing unit, the fifth connecting end is connected with the receiving data buffer, and the sixth connecting end is connected with the transmitting controller of the transmitting unit in the current data interaction unit; the receiving controller is configured to send the communication data to a current processing unit for data processing if the target frame tag information is equal to current frame tag information of the current processing unit, or send the communication data to the sending unit in the current data interaction unit if the target frame tag information is not equal to the current frame tag information, so as to send the communication data to the receiving unit in a next data interaction unit through the sending unit in the current data interaction unit until the communication data is transmitted to the target processing unit;

And the watchdog unit is respectively connected with the parallel conversion unit and the seventh connecting end.

2. A communication method of a multi-core system, applied to the multi-core system according to claim 1, the communication method of the multi-core system comprising:

Acquiring a target data frame sent by the sending unit in the last data interaction unit and current frame marking information of the current processing unit, wherein the target data frame comprises target frame marking information for identifying a target processing unit;

If the target frame marking information is equal to the current frame marking information, the target data frame is sent to the current processing unit for data processing;

and if the target frame marking information is not equal to the current frame marking information, transmitting the target data frame to the transmitting unit in the current data interaction unit so as to transmit the target data frame to the receiving unit in the next data interaction unit through the transmitting unit in the current data interaction unit until the target data frame is transmitted to the target processing unit.

3. The communication method of a multi-core system according to claim 2, wherein before the acquisition of the target data frame transmitted by the transmitting unit in the last data interaction unit and the current frame marking information of the current processing unit, the communication method of a multi-core system further comprises:

Acquiring a target diagnosis frame sent by the sending unit in the last data interaction unit, wherein the target diagnosis frame comprises diagnosis identification information, the target diagnosis frame is generated by a host, and the host is any one of a plurality of processing units;

And if the diagnosis identification information is equal to a preset diagnosis value, transmitting the target diagnosis frame to the transmitting unit in the current data interaction unit, so as to transmit the target diagnosis frame to the receiving unit in the next data interaction unit through the transmitting unit in the current data interaction unit until the target diagnosis frame is transmitted to the receiving unit in the data interaction unit corresponding to the host.

4. The communication method of a multi-core system according to claim 3, characterized in that the communication method of a multi-core system further comprises:

if the host computer receives the target diagnosis frame within a preset time period after sending the target diagnosis frame, sending the target data frame to the next data interaction unit;

And if the host computer does not receive the target diagnosis frame within a preset time period after sending the target diagnosis frame, generating a system error reporting signal.

5. The communication method of a multi-core system according to claim 2, characterized in that after said transmitting the target data frame to the transmitting unit in the current data interaction unit, the communication method of a multi-core system further comprises:

The sending unit in the current data interaction unit sends a clock signal to the receiving unit in the next data interaction unit so as to perform clock synchronization;

and the sending unit in the current data interaction unit sends the target data frame to the receiving unit in the next data interaction unit.

6. The communication method of the multi-core system according to claim 5, wherein the transmitting unit in the current data interaction unit transmits the target data frame to the receiving unit in the next data interaction unit, comprising:

Splitting the target data frame into a first data frame and a second data frame by the sending unit in the current data interaction unit;

The first data frame is sent to the receiving unit in the next data interaction unit on the rising edge of the clock signal, and the second data frame is sent to the receiving unit in the next data interaction unit on the falling edge of the clock signal.

7. A control device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the communication method of the multi-core system according to any one of claims 2 to 6 when executing the computer program.

8. A computer-readable storage medium storing computer-executable instructions for performing the communication method of the multi-core system of any one of claims 2 to 6.