CN107528557A - A kind of operational amplifier of data-driven - Google Patents

Abstract

The embodiment of the present invention discloses a data-driven operational amplifier, which includes: a loop-folded transconductance operational amplifier circuit connected to each other with N-type and P-type complementary inputs and a data-driven operational amplifier bias circuit; the data-driven The operational amplifier bias circuit includes an input differential signal comparator; the input differential signal comparator is used to detect the input differential signal, and increases the bias current of the circuit when the input differential signal is greater than or equal to the opening threshold of the input differential signal comparator, when When the input differential signal is less than the turn-on threshold of the input differential signal comparator, the bias current of the holding circuit does not change. And it can dynamically adjust the amplifier current, comparator opening threshold and comparator speed according to application requirements, and control the working window of high current. Through the solution of this embodiment, the speed of the high-performance switched capacitor circuit is improved, the power consumption is reduced, and the yield rate is improved.

Description

A Data-Driven Operational Amplifier

technical field

The embodiment of the present invention relates to the VLSI design technology in the field of microelectronics and solid state electronics, especially to a data-driven operational amplifier.

Background technique

Operational amplifier is one of the most important modules of many analog circuits. It is widely used in analog signal processing circuits such as analog-to-digital conversion circuits and filters. It usually determines the accuracy, speed and power consumption that high-performance switched capacitor circuits can achieve. In a switched capacitor circuit, the load is usually purely capacitive. At this time, a single-stage operational transconductance amplifier OTA is superior to a multi-stage operational amplifier. Therefore, the traditional folded operational transconductance amplifier has been widely used. However, the traditional folding OTA has disadvantages such as slow speed and high power consumption, especially when the load capacitance is large, the speed of the operational amplifier becomes the main bottleneck restricting the speed of the switched capacitor circuit.

Contents of the invention

In order to solve the above technical problems, an embodiment of the present invention provides a data-driven operational amplifier, which can increase the speed of a high-performance switched capacitor circuit, reduce power consumption, and improve yield.

In order to achieve the purpose of the embodiment of the present invention, the embodiment of the present invention provides a data-driven operational amplifier, which includes: a loop-folded transconductance operational amplifier circuit connected to each other with N-type and P-type complementary inputs and a data-driven operational amplifier an amplifier bias circuit; the data-driven operational amplifier bias circuit includes an input differential signal comparator;

The input differential signal comparator is used to detect the input differential signal, and increase the bias current of the circuit when the input differential signal is greater than or equal to the opening threshold of the input differential signal comparator, when the input differential signal When it is less than the opening threshold of the input differential signal comparator, the bias current of the holding circuit will not change.

Optionally, the loop-folded transconductance operational amplifier circuit of the N-type and P-type complementary inputs includes:

An N-type complementary input differential pair unit and an N-type bias voltage transistor unit, an N-type bias tail current transistor unit, and an N-type cascode transistor pair unit connected to the N-type complementary input differential pair unit; and,

A P-type complementary input differential pair unit and a P-type bias voltage transistor unit, a P-type bias tail current transistor unit, and a P-type cascode transistor pair unit connected to the P-type complementary input differential pair unit.

Optionally,

The N-type complementary input differential pair unit includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; wherein, the gates of the first NMOS transistor and the second NMOS transistor are both connected to the first differential signal VINN in the input differential signal; the gates of the third NMOS transistor and the fourth NMOS transistor are both connected to the second differential signal VINP in the input differential signal;

The N-type bias voltage transistor unit includes: a fifth NMOS transistor; the gate of the fifth NMOS transistor is connected to the first bias voltage, the source is grounded, and the drain is connected to the first NMOS transistor and the second NMOS transistor. The sources of the transistor, the third NMOS transistor and the fourth NMOS transistor are connected.

Optionally,

The P-type complementary input differential pair unit includes: a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, and a twelfth PMOS transistor; wherein, the gates of the ninth PMOS transistor and the tenth PMOS transistor Both poles are connected to the first differential signal VINN; the gates of the eleventh PMOS transistor and the gates of the twelfth PMOS transistor are both connected to the second differential signal VINP;

The P-type bias tail current transistor unit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; wherein, the gate of the first PMOS transistor is connected to the second PMOS transistor connected to the gate of the fourth NMOS transistor and then connected to the drain of the fourth NMOS transistor; the gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor and then connected to the drain of the second NMOS transistor connected, the sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor are connected to a power supply voltage;

The P-type cascode transistor pair unit includes: a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor; wherein, the gate of the fifth PMOS transistor is connected to the sixth PMOS transistor The gate of the transistor is connected to the second bias voltage after being connected; the gate of the seventh PMOS transistor is also connected to the second bias voltage after being connected to the gate of the eighth PMOS transistor; The source of the PMOS transistor is connected to the drain of the second PMOS transistor, the source of the sixth PMOS transistor is connected to the drain of the third PMOS transistor, and the drain of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor. The drain of the fourth NMOS transistor is connected, the drain of the sixth PMOS transistor is connected to the drain of the second NMOS transistor, and the source of the seventh PMOS transistor is connected to the drain of the first NMOS transistor and then connected to the drain of the first PMOS transistor, the source of the eighth PMOS transistor is connected to the drain of the third NMOS transistor and then connected to the drain of the fourth PMOS transistor;

The P-type bias voltage transistor unit includes: a thirteenth PMOS transistor; the gate of the thirteenth PMOS transistor is connected to the common mode control signal, the source is connected to the power supply voltage, and the drain is connected to the ninth PMOS transistor. tube, the tenth PMOS tube, the eleventh PMOS tube and the sources of the twelfth PMOS tube are connected.

Optionally,

The N-type bias tail current transistor unit includes: a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; wherein the gate of the sixth NMOS transistor is connected to the gate of the seventh NMOS transistor The gate is connected to the drain of the twelfth PMOS transistor, and the gate of the eighth NMOS transistor is connected to the gate of the ninth NMOS transistor and then connected to the drain of the tenth PMOS transistor. connected, the sources of the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, and the ninth NMOS transistor are grounded;

The N-type cascode transistor pair unit includes: a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, and a thirteenth NMOS transistor; wherein, the gate of the tenth NMOS transistor is connected to the The gate of the eleventh NMOS transistor is connected to the third bias voltage, and the gate of the twelfth NMOS transistor is connected to the gate of the thirteenth NMOS transistor and then connected to the third bias voltage. The source of the tenth NMOS transistor is connected to the drain of the seventh NMOS transistor, the source of the eleventh NMOS transistor is connected to the drain of the eighth NMOS transistor, and the tenth NMOS transistor The drain of the transistor is connected to the drain of the twelfth PMOS transistor, the drain of the eleventh NMOS transistor is connected to the drain of the tenth PMOS transistor, and the source of the twelfth NMOS transistor is connected to the drain of the tenth PMOS transistor. The drain of the ninth PMOS transistor is connected to the drain of the sixth NMOS transistor, and the source of the thirteenth NMOS transistor is connected to the drain of the eleventh PMOS transistor and then connected to the drain of the eleventh PMOS transistor. connected to the drain of the ninth NMOS transistor.

Optionally,

The drain of the seventh PMOS transistor is connected to the drain of the twelfth NMOS transistor to output a first output differential signal VOUTP, and the drain of the eighth PMOS transistor is connected to the drain of the thirteenth NMOS transistor A second output differential signal VOUTN is output, and the first output differential signal VOUTP and the second output differential signal VOUTN together constitute a fully differential output signal.

Optionally, the data-driven operational amplifier bias circuit includes: a bias voltage generation circuit, an input differential signal comparator, and a data-driven current branch.

Optionally,

The bias voltage generation circuit includes: a first bias current source, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor tube, the twenty-first NMOS tube, the twenty-first NMOS tube, the twenty-second NMOS tube, the twenty-third NMOS tube, the twenty-fourth NMOS tube, the twenty-fifth NMOS tube, the twenty-sixth NMOS tube, Twenty-seventh NMOS tube, twenty-eighth NMOS tube, twenty-ninth NMOS tube, fourteenth PMOS tube, fifteenth PMOS tube, sixteenth PMOS tube, seventeenth PMOS tube, eighteenth PMOS tube , the nineteenth PMOS tube, the twentieth PMOS tube, the twenty-first PMOS tube, the twenty-second PMOS tube, the twenty-third PMOS tube, the twenty-fourth PMOS tube, the twenty-fifth PMOS tube, the second Sixteen PMOS tubes and twenty-seventh PMOS tubes;

Wherein, the negative electrode of the first bias current source is connected to the power supply voltage, the positive electrode of the first bias current source is connected to the drain of the fourteenth NMOS transistor, and then connected to the fourteenth NMOS transistor, Gates of the fifteenth NMOS transistor, the sixteenth NMOS transistor, the seventeenth NMOS transistor, the eighteenth NMOS transistor, the nineteenth NMOS transistor, the twentieth NMOS transistor, and the twenty-first NMOS transistor are connected, and the gates of the first NMOS transistor The source of the fourteenth NMOS transistor is connected to the drain of the fifteenth NMOS transistor, the source of the sixteenth NMOS transistor is connected to the drain of the seventeenth NMOS transistor, and the eighteenth NMOS transistor The source of the twentieth NMOS transistor is connected to the drain of the nineteenth NMOS transistor, the source of the twentieth NMOS transistor is connected to the drain of the twenty-first NMOS transistor, and the drain of the twenty-second NMOS transistor and then connected to the gate of the twenty-third NMOS transistor and the twenty-fourth NMOS transistor, the source of the twenty-second NMOS transistor is connected to the gate of the twenty-third NMOS transistor connected to the drain of the twenty-fourth NMOS transistor and then connected to the source of the twenty-fifth NMOS transistor; the source of the twenty-third NMOS transistor is connected to the source of the twenty-eighth NMOS transistor connected to the drain, the source of the twenty-fourth NMOS transistor is connected to the drain of the twenty-ninth NMOS transistor, the gate of the twenty-eighth NMOS transistor is connected to the first control word, and the second The gate of the nineteenth NMOS transistor is connected to the second control word, the gate of the twenty-fifth NMOS transistor is connected to the drain and then connected to the gate of the twenty-sixth NMOS transistor as the third bias voltage, The drain of the twenty-sixth NMOS transistor is connected to the gate of the twenty-seventh NMOS transistor as the first bias voltage, and the source of the twenty-sixth NMOS transistor is connected to the gate of the twenty-seventh NMOS transistor. The drains of the seven NMOS transistors are connected, and the fifteenth NMOS transistor, the seventeenth NMOS transistor, the nineteenth NMOS transistor, the twenty-first NMOS transistor, the twenty-seventh NMOS transistor, the twenty-eighth NMOS transistor and the The source of the twenty-ninth NMOS transistor is grounded, the gate and drain of the fourteenth PMOS transistor are connected to the gate of the fifteenth PMOS transistor and the gate of the sixteenth PMOS transistor, and then connected to the gate of the sixteenth PMOS transistor. The drain of the sixteenth NMOS transistor is connected, the source of the fourteenth PMOS transistor is connected to the drain of the fifteenth PMOS transistor and the drain of the sixteenth PMOS transistor, and then connected to the drain of the sixteenth PMOS transistor. The source of the seventeenth PMOS transistor is connected, the source of the fifteenth PMOS transistor is connected to the drain of the twenty-sixth PMOS transistor, the source of the sixteenth PMOS transistor is connected to the drain of the twenty-seventh PMOS transistor The gate of the twenty-sixth PMOS transistor is connected to the third control word, the gate of the twenty-seventh PMOS transistor is connected to the fourth control word, and the gate and drain of the seventeenth PMOS transistor After being connected, it is connected to the drain of the eighteenth NMOS transistor as the second bias voltage, and the second bias voltage is connected to the eighteenth PMOS transistor, the twenty-second PMOS transistor, the twenty-second The PMOS transistor is connected to the gate of the twenty-fourth PMOS transistor, and the The drain of the eighteenth PMOS transistor is connected to the drain of the twentieth NMOS transistor, the source of the eighteenth PMOS transistor is connected to the drain of the nineteenth PMOS transistor, and the nineteenth PMOS transistor The gate of the transistor is connected to the gate of the twenty-first PMOS transistor and then connected to the drain of the eighteenth PMOS transistor as a fourth bias voltage, and the fourth bias voltage is connected to the second The thirteenth PMOS transistor is connected to the gate of the twenty-fifth PMOS transistor, the source of the twenty-first PMOS transistor is connected to the drain of the twenty-first PMOS transistor, and the drain of the twenty-first PMOS transistor connected to the drain of the twenty-second NMOS transistor, the source of the twenty-second PMOS transistor is connected to the drain of the twenty-third PMOS transistor, and the drain of the twenty-second PMOS transistor connected to the drain of the twenty-fifth NMOS transistor, the source of the twenty-fourth PMOS transistor is connected to the drain of the twenty-fifth PMOS transistor, and the drain of the twenty-fourth PMOS transistor connected to the drain of the twenty-sixth NMOS transistor, the nineteenth PMOS transistor, the twenty-first PMOS transistor, the twenty-third PMOS transistor, the twenty-fifth PMOS transistor, the twenty-sixth PMOS transistor, The source of the twenty-seventh PMOS tube is connected to the power supply voltage;

The input differential signal comparator includes: a first comparator and a second comparator; wherein, the negative input terminal of the first comparator and the positive input terminal of the second comparator are connected to the first differential signal VINN , the positive input terminal of the first comparator and the negative input terminal of the second comparator are connected to the second differential signal VINP, the first comparator outputs a first control signal VC1, and the second comparator Outputting the second control signal VC2;

The data driving current branch includes: a second bias current source, a third bias current source, a 30th NMOS transistor, a 31st NMOS transistor, a 32nd NMOS transistor, a 33rd NMOS transistor, Thirty-fourth NMOS tube and thirty-fifth NMOS tube;

Wherein, the negative electrode of the second bias current source and the negative electrode of the third bias current source are connected to the power supply voltage, the source of the 30th NMOS transistor is connected to the source of the 31st NMOS transistor After being connected, it is connected to the anode of the second bias current source, the grid of the 30th NMOS transistor is connected to the first control signal VC1, and the grid of the 31st NMOS transistor is connected to the second Control signal VC2, the drain of the 30th NMOS transistor is connected to the drain of the 31st NMOS transistor and then connected to the drain of the 34th NMOS transistor, the 34th NMOS transistor The gate of the transistor is connected to the fifth control word, the source of the thirty-second NMOS transistor is connected to the source of the thirty-third NMOS transistor and then connected to the anode of the third bias current source, The gate of the thirty-second NMOS transistor is connected to the first control signal VC1, the gate of the thirty-third NMOS transistor is connected to the second control signal VC2, and the drain of the thirty-second NMOS transistor connected to the drain of the thirty-third NMOS transistor and then connected to the drain of the thirty-fifth NMOS transistor; the gate of the thirty-fifth NMOS transistor is connected to the sixth control word; The source of the thirty-fourth NMOS transistor and the source of the thirty-fifth NMOS transistor are connected to the drain of the fourteenth NMOS transistor.

Optionally, both the first comparator and the second comparator include: a comparator main circuit and a bias circuit with adjustable bias current;

The comparator main circuit includes: a thirty-sixth NMOS transistor, a thirty-seventh NMOS transistor, a thirty-eighth NMOS transistor, a thirty-ninth NMOS transistor, a fortieth NMOS transistor, a forty-first NMOS transistor, a Forty-two NMOS tubes, forty-third NMOS tubes, forty-fourth NMOS tubes, forty-fifth NMOS tubes, forty-sixth NMOS tubes, forty-seventh NMOS tubes, forty-eighth NMOS tubes, and second The eighteenth PMOS tube, the twenty-ninth PMOS tube, the thirty-first PMOS tube, the thirty-first PMOS tube, the thirty-second PMOS tube, the thirty-third PMOS tube, the thirty-fourth PMOS tube, the thirty-fifth PMOS tube, thirty-sixth PMOS tube, thirty-seventh PMOS tube, thirty-eighth PMOS tube, thirty-ninth PMOS tube, fortieth PMOS tube, forty-first PMOS tube, forty-second PMOS tube and the forty-third PMOS tube;

Wherein, the gates of the thirty-sixth NMOS transistor and the thirty-seventh NMOS transistor are connected to the third differential signal VCN in the input differential signal, and the thirty-eighth NMOS transistor and the thirty-ninth NMOS transistor The gates of the transistors are all connected to the fourth differential signal VCP in the input differential signal, the grid of the fortieth NMOS transistor is connected to the fifth bias voltage, the source is grounded, and the drain is connected to the thirty-sixth NMOS transistor. tube, the sources of the thirty-seventh NMOS tube, the thirty-eighth NMOS tube, and the thirty-ninth NMOS tube, and the gate of the twenty-eighth PMOS tube is connected to the gate of the twenty-ninth PMOS tube Then it is connected to the drain of the thirty-ninth NMOS transistor, and the sources of the twenty-eighth PMOS transistor, the twenty-ninth PMOS transistor, the thirty-first PMOS transistor and the thirty-first PMOS transistor are connected to the power supply voltage , the gate of the thirty-second PMOS transistor is connected to the gate of the thirty-third PMOS transistor and then connected to the sixth bias voltage, and the gate of the thirty-fourth PMOS transistor is connected to the gate of the thirty-third PMOS transistor. The gates of the five PMOS transistors are connected to the sixth bias voltage, the source of the thirty-second PMOS transistor is connected to the drain of the twenty-ninth PMOS transistor, and the thirty-third PMOS transistor is connected to the drain of the twenty-ninth PMOS transistor. The source of the transistor is connected to the drain of the thirtieth PMOS transistor, the drain of the thirty-second PMOS transistor is connected to the drain of the thirty-ninth NMOS transistor, and the thirty-third PMOS transistor The drain of the thirty-seventh NMOS transistor is connected to the drain, the source of the thirty-fourth PMOS transistor is connected to the drain of the thirty-sixth NMOS transistor, and then connected to the twenty-eighth NMOS transistor. The drain of the PMOS transistor is connected, the source of the thirty-fifth PMOS transistor is connected to the drain of the thirty-eighth NMOS transistor and then connected to the drain of the thirty-first PMOS transistor, and the source of the thirty-eighth PMOS transistor is connected to the drain of the thirty-first PMOS transistor. The gates of the thirty-sixth PMOS transistor and the thirty-seventh PMOS transistor are connected to the third differential signal VCN, and the gates of the thirty-eighth PMOS transistor and the thirty-ninth PMOS transistor are connected to the fourth differential signal VCN. The differential signal VCP is connected, the gates of the fortieth PMOS transistor and the forty-first PMOS transistor are connected to the seventh bias voltage, and the source of the fortieth PMOS transistor is connected to the drain of the forty-second PMOS transistor pole, the source of the forty-first PMOS transistor is connected to the drain of the forty-third PMOS transistor, the gate of the forty-second PMOS transistor is connected to the seventh control word, and the forty-third PMOS transistor The gate of the transistor is connected to the eighth control word, the sources of the forty-second PMOS transistor and the forty-third PMOS transistor are connected to the power supply voltage, and the drains of the fortieth PMOS transistor and the forty-first PMOS transistor are connected to the sources of the thirty-sixth PMOS transistor, the thirty-seventh PMOS transistor, the thirty-eighth PMOS transistor, and the thirty-ninth PMOS transistor, and the gate of the forty-first NMOS transistor is connected to the first The gate of the forty-second NMOS transistor is connected to the drain of the thirty-ninth PMOS transistor, and the gate of the forty-third NMOS transistor is connected to the gate of the forty-fourth NMOS transistor. It is then connected to the drain of the thirty-seventh PMOS transistor, so The sources of the forty-first NMOS transistor, the forty-second NMOS transistor, the forty-third NMOS transistor, and the forty-fourth NMOS transistor are grounded, and the gate of the forty-fifth NMOS transistor is connected to the forty-fifth NMOS transistor. The gates of the six NMOS transistors are connected to the eighth bias voltage, and the gates of the forty-seventh NMOS transistor are connected to the gates of the forty-eighth NMOS transistors and then connected to the eighth bias voltage, The source of the forty-fifth NMOS transistor is connected to the drain of the forty-second NMOS transistor, the source of the forty-sixth NMOS transistor is connected to the drain of the forty-third NMOS transistor, The drain of the forty-fifth NMOS transistor is connected to the drain of the thirty-ninth PMOS transistor, the drain of the forty-sixth NMOS transistor is connected to the drain of the thirty-seventh PMOS transistor, The source of the forty-seventh NMOS transistor is connected to the drain of the thirty-sixth PMOS transistor and then connected to the drain of the forty-first NMOS transistor, and the source of the forty-eighth NMOS transistor The electrode is connected to the drain of the thirty-eighth PMOS transistor and then connected to the drain of the forty-fourth NMOS transistor, and the drain of the forty-eighth NMOS transistor is connected to the drain of the thirty-fifth PMOS transistor connected to the drain of the thirtieth PMOS transistor and the gate of the thirty-first PMOS transistor, and the forty-seventh NMOS transistor is connected to the thirty-fourth PMOS transistor as Comparator output VCOUT;

The bias circuit with adjustable bias current includes: a fourth bias current source, a fifth bias current source, a forty-ninth NMOS transistor, a fiftieth NMOS transistor, a fifty-first NMOS transistor, a fiftieth NMOS transistor Two NMOS tubes, fifty-third NMOS tubes, fifty-fourth NMOS tubes, fifty-fifth NMOS tubes, fifty-sixth NMOS tubes, fifty-seventh NMOS tubes, fifty-eighth NMOS tubes, fifty-ninth NMOS tubes NMOS tube, sixtieth NMOS tube, sixty-first NMOS tube, sixty-second NMOS tube, sixty-third NMOS tube, forty-fourth PMOS tube, forty-fifth PMOS tube, forty-sixth PMOS tube , the forty-seventh PMOS transistor, the forty-eighth PMOS transistor, the forty-ninth PMOS transistor, the fiftieth PMOS transistor, the fifty-first PMOS transistor, the fifty-second PMOS transistor, the fifty-third PMOS transistor, and the fifty-third PMOS transistor Fifty-four PMOS tubes;

Wherein, the negative electrode of the fourth bias current source and the negative electrode of the fifth bias current source are connected to the power supply voltage, and the drain of the forty-ninth NMOS transistor is connected to the forty-ninth NMOS transistor, the first The gates of the fifty NMOS transistors, the fifty-first NMOS transistors, the fifty-second NMOS transistors, the fifty-third NMOS transistors, the fifty-fourth NMOS transistors, the fifty-fifth NMOS transistors, and the fifty-sixth NMOS transistors are connected to each other. , the source of the forty-ninth NMOS transistor is connected to the drain of the fiftieth NMOS transistor, the source of the fifty-first NMOS transistor is connected to the drain of the fifty-second NMOS transistor, The source of the fifty-third NMOS transistor is connected to the drain of the fifty-fourth NMOS transistor, the source of the fifty-fifth NMOS transistor is connected to the drain of the fifty-sixth NMOS transistor, The drain of the fifty-seventh NMOS transistor is connected to the gate and then connected to the gate of the fifty-eighth NMOS transistor, and the source of the fifty-seventh NMOS transistor is connected to the gate of the fifty-eighth NMOS transistor. The drain of the transistor is connected to the source of the fifty-ninth NMOS transistor, and the gate of the fifty-ninth NMOS transistor is connected to the drain and then connected to the gate of the sixtieth NMOS transistor. As the eighth bias voltage, the drain of the sixtieth NMOS transistor is connected to the gate of the sixty-first NMOS transistor as the fifth bias voltage, and the source of the sixtieth NMOS transistor The pole is connected to the drain of the sixty-first NMOS transistor, and the fifty-second NMOS transistor, the fifty-second NMOS transistor, the fifty-fourth NMOS transistor, the fifty-sixth NMOS transistor, and the fifty-eighth NMOS transistor , the source of the sixty-first NMOS transistor is grounded, the gate of the forty-fourth PMOS transistor is connected to the gate and drain of the forty-fifth PMOS transistor and then connected to the fifty-first NMOS transistor connected to the drain of the forty-fourth PMOS transistor, the source of the forty-fourth PMOS transistor is connected to the drain of the forty-fifth PMOS transistor and then connected to the source of the forty-sixth PMOS transistor, and the fortieth The gates and drains of the six PMOS transistors are connected and then connected to the drain of the fifty-third NMOS transistor as the sixth bias voltage, and the second bias voltage is the same as that of the forty-seventh PMOS transistor , the gates of the forty-ninth PMOS transistor, the fifty-first PMOS transistor and the fifty-third PMOS transistor are connected, and the drain of the forty-seventh PMOS transistor is connected with the drain of the fifty-fifth NMOS transistor , the source of the forty-seventh PMOS transistor is connected to the drain of the forty-eighth PMOS transistor, and the gate of the forty-eighth PMOS transistor is connected to the gate of the fiftieth PMOS transistor connected to the drain of the forty-seventh PMOS transistor as the seventh bias voltage, and the fourth bias voltage is connected to the gates of the fifty-second PMOS transistor and the fifty-fourth PMOS transistor , the source of the forty-ninth PMOS transistor is connected to the drain of the fiftieth PMOS transistor, and the drain of the forty-ninth PMOS transistor is connected to the drain of the fifty-seventh NMOS transistor, The source of the fifty-first PMOS transistor and the source of the fifty-second PMOS transistor The drain of the fifty-first PMOS transistor is connected to the drain of the fifty-ninth NMOS transistor, and the source of the fifty-third PMOS transistor is connected to the drain of the fifty-fourth PMOS transistor. The drains of the fifty-third PMOS transistors are connected to the drains of the sixtieth NMOS transistors, the forty-fifth PMOS transistors, the forty-eighth PMOS transistors, the fiftieth PMOS transistors, The sources of the fifty-second PMOS transistor and the fifty-fourth PMOS transistor are connected to the power supply voltage, the anode of the fourth bias current source is connected to the drain of the sixty-second NMOS transistor, and the sixth The gate of the twelve NMOS transistors is connected to the ninth control word, the anode of the fifth bias current source is connected to the drain of the sixty-third NMOS transistor, and the gate of the sixty-third NMOS transistor is connected to the In the tenth control word, the sources of the sixty-second NMOS transistor and the sixty-third NMOS transistor are connected to the drain of the forty-ninth NMOS transistor.

Optionally, the loop-folded transconductance operational amplifier circuit with N-type and P-type complementary inputs also includes: a common-mode feedback circuit; the common-mode feedback circuit includes: a fully differential signal and a common-mode signal input transistor unit, a bias voltage a transistor unit and a common-mode feedback control signal generating unit;

The fully differential signal and common mode signal input transistor unit includes: a sixty-fourth NMOS transistor, a sixty-fifth NMOS transistor, a sixty-sixth NMOS transistor, and a sixty-seventh NMOS transistor;

Wherein, the gate of the sixty-fourth NMOS transistor is connected to the second output differential signal VOUTN, the gate of the sixty-seventh NMOS transistor is connected to the first output differential signal VOUTP, and the sixty-fifth The gate of the NMOS transistor is connected to the gate of the sixty-sixth NMOS transistor and then connected to the common mode input voltage VCM;

The bias voltage transistor unit includes: a sixty-eighth NMOS transistor and a sixty-ninth NMOS transistor;

Wherein, the drain of the sixty-eighth NMOS transistor is connected to the source of the sixty-fourth NMOS transistor and the source of the sixty-fifth NMOS transistor, and the drain of the sixty-ninth NMOS transistor The source of the sixty-sixth NMOS transistor is connected to the source of the sixty-seventh NMOS transistor, and the gate of the sixty-eighth NMOS transistor is connected to the gate of the sixty-ninth NMOS transistor connected to the first bias voltage, the source of the sixty-eighth NMOS transistor and the source of the sixty-ninth NMOS transistor are grounded;

The common-mode feedback control signal generation unit includes: a fifty-fifth PMOS transistor, a fifty-sixth PMOS transistor, and a first resistor R1 and a second resistor R2 connected in series;

Wherein, the gate of the fifty-fifth PMOS transistor is connected to the gate of the fifty-sixth PMOS transistor and then connected to the serial terminal of the first resistor R1 and the second resistor R2, and the fifty-fifth The drain of the fifth PMOS transistor is connected to the non-serial connection end of the first resistor R1 and then connected to the drain of the sixty-fourth NMOS transistor and the drain of the sixty-seventh NMOS transistor, and connected to It is followed by a common mode control signal VCMFB, and the drain of the fifty-sixth PMOS transistor is connected to the non-serial end of the second resistor R2, and then connected to the drain of the sixty-fifth NMOS transistor and the sixtieth The drains of the six NMOS transistors are connected, and the sources of the fifty-fifth PMOS transistor and the fifty-sixth PMOS transistor are connected to the power supply voltage.

Embodiments of the present invention include: a loop-folded transconductance operational amplifier circuit with complementary input of N-type and P-type connected to each other and a data-driven operational amplifier bias circuit; the data-driven operational amplifier bias circuit includes an input differential signal comparator ; The input differential signal comparator is used to detect the input differential signal, and increase the bias current of the circuit when the input differential signal is greater than or equal to the opening threshold of the input differential signal comparator, when the input differential signal When the signal is smaller than the opening threshold of the input differential signal comparator, the bias current of the holding circuit does not change. And it can dynamically adjust the amplifier current, comparator opening threshold and comparator speed according to application requirements, and control the working window of high current. Through the solution of this embodiment, the speed of the high-performance switched capacitor circuit is improved, the power consumption is reduced, and the yield rate is improved.

Additional features and advantages of the embodiments of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments of the invention. The objectives and other advantages of the embodiments of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and accompanying drawings.

Description of drawings

The accompanying drawings are used to provide a further understanding of the technical solutions of the embodiments of the present invention, and constitute a part of the description, and are used together with the embodiments of the application to explain the technical solutions of the embodiments of the present invention, and do not constitute limitations to the technical solutions of the embodiments of the present invention .

FIG. 1 is a schematic diagram of a data-driven operational amplifier according to an embodiment of the present invention;

2 is a schematic circuit diagram of a first comparator and a second comparator according to an embodiment of the present invention;

FIG. 3 is a schematic circuit diagram of a common-mode feedback circuit according to an embodiment of the present invention.

detailed description

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

In order to achieve the purpose of the embodiment of the present invention, the embodiment of the present invention provides a data-driven operational amplifier, which includes: a loop-folded transconductance operational amplifier circuit connected to each other with N-type and P-type complementary inputs and a data-driven operational amplifier an amplifier bias circuit; the data-driven operational amplifier bias circuit includes an input differential signal comparator;

The input differential signal comparator is used to detect the input differential signal, and increase the bias current of the circuit when the input differential signal is greater than or equal to the opening threshold of the input differential signal comparator, when the input differential signal When it is less than the opening threshold of the input differential signal comparator, the bias current of the holding circuit will not change.

In the embodiment of the present invention, in order to overcome the disadvantages of slow speed and high power consumption of the current folding OTA (single-stage operational transconductance amplifier), the embodiment of the present invention designs a data-driven operational amplifier. In the embodiment of the present invention, the input differential signal is detected by the comparator. When the input differential signal is greater than the comparator open threshold, the bias current of the circuit is increased to increase the speed of the amplifier. When the input differential signal is smaller than the comparator open threshold, the bias current of the circuit is The current does not increase, thereby saving power consumption. In addition, according to different application requirements, the bias current of the data driving branch or the opening threshold of the comparator or the speed of the comparator can be adjusted. Through the solution of the embodiment of the present invention, the speed of high-performance switched capacitor circuits such as high-performance analog-to-digital converters and filters can be increased, and the compromise between static power consumption, maximum output current and crossover distortion of traditional class AB amplifiers can be avoided Compared with the traditional class A amplifier, it not only has the advantages of high speed and high linearity, but also overcomes the disadvantage of large static bias current.

Optionally, the loop-folded transconductance operational amplifier circuit of the N-type and P-type complementary inputs includes:

An N-type complementary input differential pair unit and an N-type bias voltage transistor unit, an N-type bias tail current transistor unit, and an N-type cascode transistor pair unit connected to the N-type complementary input differential pair unit; and,

A P-type complementary input differential pair unit and a P-type bias voltage transistor unit, a P-type bias tail current transistor unit, and a P-type cascode transistor pair unit connected to the P-type complementary input differential pair unit.

In an embodiment of the present invention, FIG. 1 is a complementary-input loop-folded transconductance operational amplifier and a bias circuit with a data-driven branch. The complementary input loop folding OTA is different from the conventional OTA, which uses NMOS (N-channelMetal-Oxide-Semiconductor, N-channel metal-oxide-semiconductor) tube and PMOS (P-channelMetal-Oxide-Semiconductor, P-channel metal -oxide-semiconductor) tube branch complementary input.

In the embodiment of the present invention, transistors P1a, P1b, P2a, and P2b in FIG. 1 are P-type input devices, and N1a, N1b, N2a, and N2b are N-type input devices. VINN and VINP are input differential signals, VINN is added to the gates of P1a, P1b, N1a, and N1b, and VINP is added to the gates of P2a, P2b, N2a, and N2b. Transistor P0 provides bias current for P-type input branches P1a, P1b, P2a, P2b, and transistor N0 provides bias current for N-type input branches N1a, N1b, N2a, N2b. Transistors N5, N6, N7 and N8 are bias tail current transistors of the P-type input branch, and transistors P5, P6, P7 and P8 are bias tail current transistors of the N-type input branch. Transistors N3, N4, N9, and N10 are cascode transistor pairs of the P-type input branch, and transistors P3, P4, P9, and P10 are cascode transistor pairs of the N-type input branch. The drain of the transistor P9 is connected to the drain of the transistor N9 to provide a differential output VOUTP, and the drain of the transistor P10 is connected to the drain of the transistor N10 to provide another differential output VOUTN. VOUTP and VOUTN form a fully differential output. The bias voltage of transistor N0 is Vb1, the bias voltage of transistors N3, N4, N9, and N10 is Vb2, the bias voltage of transistors P3, P4, P9, and P10 is Vb3, and the bias voltage of transistor P0 is common mode feedback Common-mode control signal VCMFB generated in the circuit. In the complementary circular folding OTA adopted by the present invention, the cascode transistors N9 and N10 of the P-type input branch and the cascode transistors P9 and P10 of the N-type input branch share the same current, thereby more fully utilizing The current of each branch increases the unity gain bandwidth GBW of the op amp. The connection relationship of each unit in FIG. 1 will be described in detail below.

The N-type complementary input differential pair unit includes: a first NMOS transistor (N1a), a second NMOS transistor (N1b), a third NMOS transistor (N2a), and a fourth NMOS transistor (N2b), wherein the first NMOS transistor (N1a ), the gates of the second NMOS transistor (N1b) are connected to one of the differential signals VINN (that is, the first differential signal VINN) in the input full differential signal, the third NMOS transistor (N2a), the fourth NMOS transistor (N2b) The gates of the gates are all connected to another differential signal VINP (second differential signal VINP) in the aforementioned input fully differential signal;

The N-type bias voltage transistor unit includes: a fifth NMOS transistor (N0), the gate of the fifth NMOS transistor (N0) is connected to the first bias voltage (Vb1), the source is grounded (GND), and the drain is connected to the first bias voltage (Vb1). The sources of the first NMOS transistor (N1a), the second NMOS transistor (N1b), the third NMOS transistor (N2a) and the fourth NMOS transistor (N2b).

The P-type complementary input differential pair unit includes: a ninth PMOS transistor (P1a), a tenth PMOS transistor (P1b), an eleventh PMOS transistor (P2a) and a twelfth PMOS transistor (P2b); wherein, the ninth PMOS The gates of the transistor (P1a) and the tenth PMOS transistor (P1b) are connected to one of the differential signals VINN in the input full differential signal, and the gates of the eleventh PMOS transistor (P2a) and the twelfth PMOS transistor (P2b) Both are connected to another differential signal VINP among the aforementioned input fully differential signals.

The P-type bias tail current transistor unit includes: a first PMOS transistor (P5), a second PMOS transistor (P6), a third PMOS transistor (P7) and a fourth PMOS transistor (P8); wherein, the first PMOS transistor The grid of (P5) is connected with the grid of the second PMOS transistor (P6) and then connected with the drain of the fourth NMOS transistor (N2b), and the grid of the third PMOS transistor (P7) is connected with the drain of the fourth PMOS transistor The gate of (P8) is connected and then connected with the drain of the second NMOS transistor (N1b), the first PMOS transistor (P5), the second PMOS transistor (P6), the third PMOS transistor (P7) and the fourth PMOS transistor (P7) The source of the PMOS transistor (P8) is connected to the power supply voltage (VDD).

The P-type cascode transistor pair unit includes: a fifth PMOS transistor (P3), a sixth PMOS transistor (P4), a seventh PMOS transistor (P9) and an eighth PMOS transistor (P10); wherein, the fifth PMOS transistor (PMOS) The grid of the transistor (P3) is connected to the grid of the sixth PMOS transistor (P4) and then connected to the second bias voltage (Vb3), and the grid of the seventh PMOS transistor (P9) is connected to the grid of the eighth PMOS transistor (P10). After the electrodes are connected, the second bias voltage (Vb3) is also connected, the source of the fifth PMOS transistor (P3) is connected to the drain of the second PMOS transistor (P6), and the source of the sixth PMOS transistor (P4) is connected to the drain of the second PMOS transistor (P4). The drain of the third PMOS transistor (P7) is connected to each other, the drain of the fifth PMOS transistor (P3) is connected to the drain of the fourth NMOS transistor (N2b), and the drain of the sixth PMOS transistor (P4) is connected to the drain of the fourth NMOS transistor (P4). The drain of the second NMOS transistor (N1b) is connected, the source of the seventh PMOS transistor (P9) is connected to the drain of the first NMOS transistor (N1a) and then connected to the first PMOS transistor (P5) The drain of the eighth PMOS transistor (P10) is connected to the drain of the third NMOS transistor (N2a) and then connected to the drain of the fourth PMOS transistor (P8).

The P-type bias voltage transistor unit includes: a thirteenth PMOS transistor (P0); the gate of the thirteenth PMOS transistor (P0) is connected to the common-mode control signal (VCMFB), the source is connected to the power supply voltage (VDD), and the drain The poles are connected to the sources of the ninth PMOS transistor (P1a), the tenth PMOS transistor (P1b), the eleventh PMOS transistor (P2a) and the twelfth PMOS transistor (P2b).

The N-type bias tail current transistor unit includes: a sixth NMOS transistor (N5), a seventh NMOS transistor (N6), an eighth NMOS transistor (N7) and a ninth NMOS transistor (N8); wherein, the sixth NMOS transistor The gate of (N5) is connected with the gate of the seventh NMOS transistor (N6) and then connected with the drain of the twelfth PMOS transistor (P2b), and the gate of the eighth NMOS transistor (N7) is connected with the gate of the ninth NMOS The gate of the transistor (N8) is connected to the drain of the tenth PMOS transistor (P1b), and the sixth NMOS transistor (N5), the seventh NMOS transistor (N6), the eighth NMOS transistor (N7) and the The source of the nine NMOS transistors (N8) is grounded (GND).

The N-type cascode transistor pair unit includes: a tenth NMOS transistor (N3), an eleventh NMOS transistor (N4), a twelfth NMOS transistor (N9) and a thirteenth NMOS transistor (N10); wherein, The grid of the tenth NMOS transistor (N3) is connected to the grid of the eleventh NMOS transistor (N4) and then connected to the third bias voltage (Vb2), and the grid of the twelfth NMOS transistor (N9) is connected to the grid of the thirteenth NMOS transistor (N9). The gate of the tube (N10) is connected to the third bias voltage (Vb2), the source of the tenth NMOS tube (N3) is connected to the drain of the seventh NMOS tube (N6), and the eleventh NMOS tube The source of (N4) is connected to the drain of the eighth NMOS transistor (N7), the drain of the tenth NMOS transistor (N3) is connected to the drain of the twelfth PMOS transistor (P2b), and the eleventh NMOS transistor (P2b) is connected to the drain. The drain of the NMOS transistor (N4) is connected to the drain of the tenth PMOS transistor (P1b), and the source of the twelfth NMOS transistor (N9) is connected to the drain of the ninth PMOS transistor (P1a). Connected to the drain of the sixth NMOS transistor (N5), the source of the thirteenth NMOS transistor (N10) is connected to the drain of the eleventh PMOS transistor (P2a) and then connected to the ninth NMOS transistor The drain of (N8) is connected.

The drain of the seventh PMOS transistor (P9) is connected to the drain of the twelfth NMOS transistor (N9) to output a differential signal (VOUTP), that is, the first output differential signal VOUTP; the eighth PMOS transistor (P10) The drain is connected to the drain of the thirteenth NMOS transistor (N10) to output another differential signal (VOUTN), that is, the second output differential signal VOUTN; the differential signals VOUTP and VOUTN together constitute a fully differential output signal.

Optionally, the data-driven operational amplifier bias circuit includes: a bias voltage generation circuit, an input differential signal comparator, and a data-driven current branch.

In the embodiment of the present invention, the bias circuit of the OTA is different from the conventional bias circuit. In addition to the usual circuit for providing the bias voltage of the operational amplifier, a data driving branch and two comparators are added. Transistors M1, M2, M3, M4, M5, M6a, M6b, M7, M8, M9, M10, M11, M12, M13, M14, M15, M16, M17a, M17b, M18, M19, M20, M21, M22, M23 , M24, MK3, MK4, MK5, MK6 constitute the operational amplifier bias main circuit, the gate of the transistor M24 is connected to the bias voltage Vb1, the gates of the transistors M18 and M23 are connected to the bias voltage Vb2, and the transistors M7, M12, M14, M19 The gate of M21 is connected to the bias voltage Vb3, and the gates of the transistors M13, M15, M20, and M22 are connected to the bias voltage Vb4. By controlling the on-off of the transistors MK3 and MK4 through the control words EN3 and EN4, the parallel-connected M6a and M6b can be selectively connected to the circuit, thereby changing the value of the bias voltage Vb3. By controlling the on-off of the transistors MK5 and MK6 through the control words EN5 and EN6, the parallel-connected M17a and M17b can be selectively connected to the circuit, thereby changing the value of the bias voltage Vb2. Current source I1 provides conventional bias current for the bias circuit. The negative input terminal of the comparator COMP1 and the positive input terminal of the comparator COMP2 are connected to the differential input signal VINN, and the positive input terminal of the comparator COMP1 and the negative input terminal of the comparator COMP2 are connected to the differential input signal VINP. The data drive branch is composed of transistors MS1, MS2, MS3, MS4, MK1, MK2 and current sources I2, I3. The gates of transistors MS1 and MS3 are connected to the output of comparator COMP1, and the gates of transistors MS2 and MS4 are connected to comparator COMP2. output. When the input differential signal is large, one of the comparator COMP1 and the comparator COMP2 will be triggered and output a high level, so that one of the transistor MS1 and the transistor MS2, one of the transistor MS3 and the transistor MS4 will respond accordingly Turning on, the current of the current source I2 or I3 is added to the bias circuit, thereby increasing the speed of the OTA. The control words EN1, EN2 can selectively turn on the transistors MK1, MK2, thereby controlling the magnitude of the current of the data driving branch. The connection relationship of each circuit in the data-driven operational amplifier bias circuit will be described in detail below.

The bias voltage generating circuit includes: a first bias current source (I1), a fourteenth NMOS transistor (M1), a fifteenth NMOS transistor (M2), a sixteenth NMOS transistor (M3), a seventeenth NMOS transistor tube (M4), eighteenth NMOS tube (M8), nineteenth NMOS tube (M9), twentieth NMOS tube (M10), twenty-first NMOS tube (M11), twenty-second NMOS tube (M16 ), the twenty-third NMOS tube (M17a), the twenty-fourth NMOS tube (M17b), the twenty-fifth NMOS tube (M18), the twenty-sixth NMOS tube (M23), the twenty-seventh NMOS tube (M24 ), the twenty-eighth NMOS transistor (MK5), the twenty-ninth NMOS transistor (MK6), the fourteenth PMOS transistor (M5), the fifteenth PMOS transistor (M6a), the sixteenth PMOS transistor (M6b), the Seventeenth PMOS tube (M7), eighteenth PMOS tube (M12), nineteenth PMOS tube (M13), twentieth PMOS tube (M14), twenty-first PMOS tube (M15), twenty-second PMOS tube Tube (M19), twenty-third PMOS tube (M20), twenty-fourth PMOS tube (M21), twenty-fifth PMOS tube (M22), twenty-sixth PMOS tube (MK3) and twenty-seventh PMOS tube Tube (MK4);

Wherein, the negative electrode of the first bias current source (I1) is connected to the power supply voltage (VDD), the positive electrode of the first bias current source (I1) is connected to the drain of the fourteenth NMOS transistor (M1) and then connected to the fourteenth NMOS transistor (M1). tube (M1), fifteenth NMOS tube (M2), sixteenth NMOS tube (M3), seventeenth NMOS tube (M4), eighteenth NMOS tube (M8), nineteenth NMOS tube (M9), The gate of the 20th NMOS transistor (M10) is connected to the gate of the 21st NMOS transistor (M11), the source of the 14th NMOS transistor (M1) is connected to the drain of the 15th NMOS transistor (M2), and the drain of the 10th NMOS transistor (M1) is connected. The source of the sixth NMOS transistor (M3) is connected to the drain of the seventeenth NMOS transistor (M4), the source of the eighteenth NMOS transistor (M8) is connected to the drain of the nineteenth NMOS transistor (M9), and the second The source of the tenth NMOS transistor (M10) is connected to the drain of the twenty-first NMOS transistor (M11), and the drain of the twenty-second NMOS transistor (M16) is connected to the gate and then connected to the twenty-third NMOS transistor (M16). M17a) is connected to the gate of the twenty-fourth NMOS transistor (M17b), the source of the twenty-second NMOS transistor (M16) is connected to the twenty-third NMOS transistor (M17a) and the twenty-fourth NMOS transistor (M17b) After the drain is connected, it is connected to the source of the twenty-fifth NMOS transistor (M18), and the source of the twenty-third NMOS transistor (M17a) is connected to the drain of the twenty-eighth NMOS transistor (MK5). The source of the fourth NMOS transistor (M17b) is connected to the drain of the twenty-ninth NMOS transistor (MK6), the gate of the twenty-eighth NMOS transistor (MK5) is connected to the first control word (EN5), and the twenty-ninth NMOS transistor (MK5) is connected to the first control word (EN5). The gate of the transistor (MK6) is connected to the second control word (EN6), the gate of the twenty-fifth NMOS transistor (M18) is connected to the drain and then connected to the gate of the twenty-sixth NMOS transistor (M23) as the first Three bias voltages (Vb2), the drain of the twenty-sixth NMOS transistor (M23) is connected to the gate of the twenty-seventh NMOS transistor (M24) as the first bias voltage (Vb1), the twenty-sixth NMOS transistor The source of (M23) is connected to the drain of the twenty-seventh NMOS transistor (M24), the fifteenth NMOS transistor (M2), the seventeenth NMOS transistor (M4), the nineteenth NMOS transistor (M9), the second The source ground (GND) of the eleventh NMOS transistor (M11), the twenty-seventh NMOS transistor (M24), the twenty-eighth NMOS transistor (MK5), and the twenty-ninth NMOS transistor (MK6), and the fourteenth PMOS transistor The gate and drain of (M5) are connected to the gate of the fifteenth PMOS transistor (M6a) and the gate of the sixteenth PMOS transistor (M6b) and then connected to the drain of the aforementioned sixteenth NMOS transistor (M3) , the source of the fourteenth PMOS transistor (M5) is connected to the drain of the fifteenth PMOS transistor (M6a) and the drain of the sixteenth PMOS transistor (M6b) and then connected to the source of the seventeenth PMOS transistor (M7) Pole connected, fifteenth PMO The source of the S tube (M6a) is connected to the drain of the twenty-sixth PMOS transistor (MK3), the source of the sixteenth PMOS transistor (M6b) is connected to the drain of the twenty-seventh PMOS transistor (MK4), and the drain of the twenty-seventh PMOS transistor (MK4) is connected. The gate of the twenty-sixth PMOS transistor (MK3) is connected to the third control word (EN3), the gate of the twenty-seventh PMOS transistor (MK4) is connected to the fourth control word (EN4), and the gate of the seventeenth PMOS transistor (M7) and then connected to the drain of the eighteenth NMOS transistor (M8) as the second bias voltage (Vb3), the second bias voltage (Vb3) is connected to the eighteenth PMOS transistor (M12), The gates of the twentieth PMOS transistor (M14), the twenty-second PMOS transistor (M19) and the twenty-fourth PMOS transistor (M21) are connected, and the drain of the eighteenth PMOS transistor (M12) is connected to the aforementioned twentieth NMOS transistor. The drain of the transistor (M10) is connected, the source of the eighteenth PMOS transistor (M12) is connected to the drain of the nineteenth PMOS transistor (M13), and the gate of the nineteenth PMOS transistor (M13) is connected to the twenty-first PMOS transistor (M13). The gate of the PMOS transistor (M15) is connected and then connected to the drain of the eighteenth PMOS transistor (M12) as the fourth bias voltage (Vb4), and the fourth bias voltage (Vb4) is connected with the twenty-third PMOS transistor (M20) is connected to the gate of the twenty-fifth PMOS transistor (M22), the source of the twentieth PMOS transistor (M14) is connected to the drain of the twenty-first PMOS transistor (M15), and the twentieth PMOS transistor ( The drain of M14) is connected to the drain of the aforementioned twenty-second NMOS transistor (M16), the source of the twenty-second PMOS transistor (M19) is connected to the drain of the twenty-third PMOS transistor (M20), and the second The drain of the twelve PMOS transistors (M19) is connected to the drain of the twenty-fifth NMOS transistor (M18), and the source of the twenty-fourth PMOS transistor (M21) is connected to the drain of the twenty-fifth PMOS transistor (M22). The drain of the twenty-fourth PMOS transistor (M21) is connected to the drain of the aforementioned twenty-sixth NMOS transistor (M23), the nineteenth PMOS transistor (M13), the twenty-first PMOS transistor (M15), The sources of the twenty-third PMOS transistor (M20), the twenty-fifth PMOS transistor (M22), the twenty-sixth PMOS transistor (MK3), and the twenty-seventh PMOS transistor (MK4) are connected to the power supply voltage (VDD).

The input differential signal comparator includes: two comparators (COMP1, COMP2), that is, the first comparator COMP1 and the second comparator COMP2; wherein, the negative input terminal of the first comparator (COMP1) and the second comparator The positive input terminal of (COMP2) is connected to the input differential signal VINN (ie, the first differential signal VINN), and the positive input terminal of the first comparator (COMP1) and the negative input terminal of the second comparator (COMP2) are connected to the input differential signal VINP ( That is, the second differential signal VINP), the first comparator ( COMP1 ) outputs the first control signal VC1 , and the second comparator ( COMP2 ) outputs the second control signal VC2 .

The data driving current branch includes: a second bias current source (I2), a third bias current source (I3), a thirtieth NMOS transistor (MS1), a thirty-first NMOS transistor (MS2), and a third bias current source (I3). Twelve NMOS transistors (MS3), thirty-third NMOS transistors (MS4), thirty-fourth NMOS transistors (MK1) and thirty-fifth NMOS transistors (MK2);

Wherein, the negative electrode of the second bias current source (I2) and the negative electrode of the third bias current source (I3) are connected to the power supply voltage (VDD), and the source electrode of the 30th NMOS transistor (MS1) is connected to the source electrode of the 31st NMOS transistor ( The source of MS2) is connected to the positive electrode of the second bias current source (I2), the grid of the 30th NMOS transistor (MS1) is connected to the first control signal VC1, and the gate of the 31st NMOS transistor (MS2) connected to the second control signal VC2, the drain of the 30th NMOS transistor (MS1) is connected to the drain of the 31st NMOS transistor (MS2) and then connected to the drain of the 34th NMOS transistor (MK1), The gate of the thirty-fourth NMOS transistor (MK1) is connected to the fifth control word (EN1), the source of the thirty-second NMOS transistor (MS3) is connected to the source of the thirty-third NMOS transistor (MS4) and then connected to the source of the thirty-third NMOS transistor (MS4). The positive pole of the third bias current source (I3) is connected, the gate of the thirty-second NMOS transistor (MS3) is connected to the first control signal VC1, the gate of the thirty-third NMOS transistor (MS4) is connected to the second control signal VC2, The drain of the thirty-second NMOS transistor (MS3) is connected to the drain of the thirty-third NMOS transistor (MS4) and then connected to the drain of the thirty-fifth NMOS transistor (MK2), and the thirty-fifth NMOS transistor ( The gate of MK2) is connected to the sixth control word (EN2), the source of the thirty-fourth NMOS transistor (MK1) and the source of the thirty-fifth NMOS transistor (MK2) are connected to the fourteenth NMOS transistor (M1) connected to the drain.

Optionally, both the first comparator and the second comparator include: a comparator main circuit and a bias circuit with adjustable bias current.

In an embodiment of the present invention, FIG. 2 is a circuit diagram of a comparator in the present invention. The main circuit of the comparator also adopts a complementary input loop structure, consisting of transistors MK7, MK8, PC0a, PC0b, PC1a, PC1b, PC2a, PC2b, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, NC0, NC1a, NC1b, NC2a, NC2b, NC3, NC4, NC5, NC6, NC7, NC8, NC9, NC10. According to different application requirements, through the control words EN7, EN8 to control the on-off of the transistors MK7, MK8, the transistor PC0a or PC0b can be selectively connected to the circuit to adjust the bias current of the P input branch and change the opening of the comparator. threshold. Transistors MC1, MC2, MC3, MC4, MC5, MC6, MC7, MC8, MC9, MC10, MC11, MC12, MC13, MC14, MC15, MC16, MC17, MC18, MC19, MC20, MC21, MC22, MC23, MC24 composition comparison tor bias the main circuit. The bias current of the comparator is provided by current sources IC1 and IC2. According to different application requirements, the on-off of the transistors MK9 and MK10 can be controlled through the control words EN9 and EN10 to adjust the magnitude of the comparator bias current, thereby adjusting the comparator’s speed. Through the setting of control words EN7, EN8, EN9, EN10, the working window of high current can be controlled.

The comparator main circuit includes: the thirty-sixth NMOS transistor (NC1a), the thirty-seventh NMOS transistor (NC1b), the thirty-eighth NMOS transistor (NC2a), the thirty-ninth NMOS transistor (NC2b), the fourth Ten NMOS tubes (NC0), forty-first NMOS tubes (NC5), forty-second NMOS tubes (NC6), forty-third NMOS tubes (NC7), forty-fourth NMOS tubes (NC8), forty-second Five NMOS tubes (NC3), forty-sixth NMOS tubes (NC4), forty-seventh NMOS tubes (NC9), forty-eighth NMOS tubes (NC10), twenty-eighth PMOS tubes (PC5), twenty-eighth Nine PMOS transistors (PC6), thirty-first PMOS transistors (PC7), thirty-first PMOS transistors (PC8), thirty-second PMOS transistors (PC3), thirty-third PMOS transistors (PC4), thirty-fourth PMOS tube (PC9), thirty-fifth PMOS tube (PC10), thirty-sixth PMOS tube (PC1a), thirty-seventh PMOS tube (PC1b), thirty-eighth PMOS tube (PC2a), thirty-ninth PMOS transistor (PC2b), fortieth PMOS transistor (PC0a), forty-first PMOS transistor (PC0b), forty-second PMOS transistor (MK7) and forty-third PMOS transistor (MK8);

Wherein, the gates of the thirty-sixth NMOS transistor (NC1a) and the thirty-seventh NMOS transistor (NC1b) are connected to one of the differential signal VCN (that is, the third differential signal VCN) in the input full differential signal, and the thirty-sixth The gates of the eighth NMOS transistor (NC2a) and the thirty-ninth NMOS transistor (NC2b) are connected to another differential signal VCP (that is, the fourth differential signal VCP) in the aforementioned input full differential signal, and the fortieth NMOS transistor (NC0 ) the gate is connected to the fifth bias voltage (VCb1), the source is grounded (GND), and the drain is connected to the thirty-sixth NMOS transistor (NC1a), the thirty-seventh NMOS transistor (NC1b), and the thirty-eighth NMOS transistor ( NC2a) and the source of the thirty-ninth NMOS transistor (NC2b), the gate of the twenty-eighth PMOS transistor (PC5) is connected to the gate of the twenty-ninth PMOS transistor (PC6) and then connected to the gate of the thirty-ninth NMOS transistor (PC6) The drain of the transistor (NC2b) is connected, and the source electrodes of the twenty-eighth PMOS transistor (PC5), the twenty-ninth PMOS transistor (PC6), the thirty-first PMOS transistor (PC7) and the thirty-first PMOS transistor (PC8) Connected to the power supply voltage (VDD), the gate of the thirty-second PMOS transistor (PC3) is connected to the gate of the thirty-third PMOS transistor (PC4) and then connected to the sixth bias voltage (VCb3), the thirty-fourth PMOS transistor The gate of (PC9) is connected to the gate of the thirty-fifth PMOS transistor (PC10) and then connected to the sixth bias voltage (VCb3), and the source of the thirty-second PMOS transistor (PC3) is connected to the gate of the twenty-ninth PMOS transistor (PC10). The drain of the thirty-third PMOS transistor (PC4) is connected to the drain of the thirty-third PMOS transistor (PC7), and the drain of the thirty-second PMOS transistor (PC3) is connected to the drain of the third PMOS transistor (PC3). The drain of the nineteenth NMOS transistor (NC2b) is connected, the drain of the thirty-third PMOS transistor (PC4) is connected to the drain of the thirty-seventh NMOS transistor (NC1b), and the source of the thirty-fourth PMOS transistor (PC9) The electrode is connected to the drain of the thirty-sixth NMOS transistor (NC1a) and then connected to the drain of the twenty-eighth PMOS transistor (PC5), and the source of the thirty-fifth PMOS transistor (PC10) is connected to the drain of the thirty-eighth NMOS transistor (PC10). The drain of the transistor (NC2a) is connected to the drain of the thirty-first PMOS transistor (PC8), and the gates of the thirty-sixth PMOS transistor (PC1a) and the thirty-seventh PMOS transistor (PC1b) are connected to the input One of the differential signals VCN (that is, the third differential signal VCN) in the fully differential signal is connected, and the gates of the thirty-eighth PMOS transistor (PC2a) and the thirty-ninth PMOS transistor (PC2b) are connected to the aforementioned input fully differential signal. Another differential signal VCP (that is, the fourth differential signal VCP) is connected, the gates of the fortieth PMOS transistor (PC0a) and the forty-first PMOS transistor (PC0b) are connected to the seventh bias voltage (VCb4), the fortieth The source of the PMOS transistor (PC0a) is connected to the drain of the forty-second PMOS transistor (MK7), and the forty-first The source of the PMOS transistor (PC0b) is connected to the drain of the forty-third PMOS transistor (MK8), the gate of the forty-second PMOS transistor (MK7) is connected to the seventh control word (EN7), and the forty-third PMOS transistor ( The gate of MK8) is connected to the eighth control word (EN8), the sources of the forty-second PMOS transistor (MK7) and the forty-third PMOS transistor (MK8) are connected to the power supply voltage (VDD), and the fortieth PMOS transistor (PC0a ) and the drain of the forty-first PMOS transistor (PC0b) are connected to the thirty-sixth PMOS transistor (PC1a), the thirty-seventh PMOS transistor (PC1b), the thirty-eighth PMOS transistor (PC2a) and the thirty-ninth PMOS transistor The source of the transistor (PC2b), the gate of the forty-first NMOS transistor (NC5) is connected to the gate of the forty-second NMOS transistor (NC6) and then connected to the drain of the thirty-ninth PMOS transistor (PC2b) , the gate of the forty-third NMOS transistor (NC7) is connected to the gate of the forty-fourth NMOS transistor (NC8) and then connected to the drain of the thirty-seventh PMOS transistor (PC1b), the forty-first NMOS transistor (NC5), the forty-second NMOS transistor (NC6), the source ground (GND) of the forty-third NMOS transistor (NC7) and the forty-fourth NMOS transistor (NC8), the forty-fifth NMOS transistor (NC3) The grid of the forty-sixth NMOS transistor (NC4) is connected to the eighth bias voltage (VCb2), and the grid of the forty-seventh NMOS transistor (NC9) is connected to the grid of the forty-eighth NMOS transistor (NC10). After the gate of the grid is connected, it is also connected to the eighth bias voltage (VCb2), the source of the forty-fifth NMOS transistor (NC3) is connected to the drain of the forty-second NMOS transistor (NC6), and the forty-sixth NMOS transistor (NC6) is connected to the drain. The source of NC4) is connected to the drain of the forty-third NMOS transistor (NC7), the drain of the forty-fifth NMOS transistor (NC3) is connected to the drain of the thirty-ninth PMOS transistor (PC2b), and the fortieth The drain of the sixth NMOS transistor (NC4) is connected to the drain of the thirty-seventh PMOS transistor (PC1b), and the source of the forty-seventh NMOS transistor (NC9) is connected to the drain of the thirty-sixth PMOS transistor (PC1a) Then it is connected to the drain of the forty-first NMOS transistor (NC5), and the source of the forty-eighth NMOS transistor (NC10) is connected to the drain of the thirty-eighth PMOS transistor (PC2a) and then connected to the forty-fourth NMOS transistor (PC2a). The drain of the NMOS transistor (NC8) is connected, and the drain of the forty-eighth NMOS transistor (NC10) is connected to the drain of the thirty-fifth PMOS transistor (PC10) and then connected to the gate of the thirty-fifth PMOS transistor (PC7). It is connected to the gate of the thirty-first PMOS transistor (PC8), and the forty-seventh NMOS transistor (NC9) is connected to the thirty-fourth PMOS transistor (PC9) as a comparator output VCOUT.

The bias circuit with adjustable bias current includes: a fourth bias current source (IC1), a fifth bias current source (IC2), a forty-ninth NMOS transistor (MC1), a fiftieth NMOS transistor (MC2 ), the fifty-first NMOS tube (MC3), the fifty-second NMOS tube (MC4), the fifty-third NMOS tube (MC8), the fifty-fourth NMOS tube (MC9), the fifty-fifth NMOS tube (MC10 ), the fifty-sixth NMOS tube (MC11), the fifty-seventh NMOS tube (MC16), the fifty-eighth NMOS tube (MC17), the fifty-ninth NMOS tube (MC18), the sixtieth NMOS tube (MC23) , the sixty-first NMOS tube (MC24), the sixty-second NMOS tube (MK9), the sixty-third NMOS tube (MK10), the forty-fourth PMOS tube (MC5), the forty-fifth PMOS tube (MC6) , the forty-sixth PMOS transistor (MC7), the forty-seventh PMOS transistor (MC12), the forty-eighth PMOS transistor (MC13), the forty-ninth PMOS transistor (MC14), the fiftieth PMOS transistor (MC15), Fifty-first PMOS transistor (MC19), fifty-second PMOS transistor (MC20), fifty-third PMOS transistor (MC21) and fifty-fourth PMOS transistor (MC22);

Wherein, the cathode of the fourth bias current source (IC1) and the cathode of the fifth bias current source (IC2) are connected to the power supply voltage (VDD), and the drain of the forty-ninth NMOS transistor (MC1) is connected to the drain of the forty-ninth NMOS transistor (MC1), the fiftieth NMOS tube (MC2), the fifty-first NMOS tube (MC3), the fifty-second NMOS tube (MC4), the fifty-third NMOS tube (MC8), the fifty-fourth NMOS tube ( MC9), the gates of the fifty-fifth NMOS transistor (MC10) and the fifty-sixth NMOS transistor (MC11) are connected, the source of the forty-ninth NMOS transistor (MC1) is connected to the drain of the fiftieth NMOS transistor (MC2) The source of the fifty-first NMOS transistor (MC3) is connected to the drain of the fifty-second NMOS transistor (MC4), and the source of the fifty-third NMOS transistor (MC8) is connected to the fifty-fourth NMOS transistor ( MC9) is connected to the drain, the source of the fifty-fifth NMOS transistor (MC10) is connected to the drain of the fifty-sixth NMOS transistor (MC11), and the drain of the fifty-seventh NMOS transistor (MC16) is connected to the gate Then it is connected to the gate of the fifty-eighth NMOS transistor (MC17), and the source of the fifty-seventh NMOS transistor (MC16) is connected to the drain of the fifty-eighth NMOS transistor (MC17) and then connected to the fifty-ninth NMOS transistor (MC17). The source of the NMOS transistor (MC18) is connected, the gate of the fifty-ninth NMOS transistor (MC18) is connected to the drain, and then connected to the gate of the sixtieth NMOS transistor (MC23) as the eighth bias voltage (VCb2) , the drain of the sixtieth NMOS transistor (MC23) is connected to the gate of the sixtieth NMOS transistor (MC24) as the fifth bias voltage (VCb1), and the source of the sixtieth NMOS transistor (MC23) is connected to the gate of the sixth NMOS transistor (MC23). The drains of the eleventh NMOS transistor (MC24) are connected, the fiftieth NMOS transistor (MC2), the fifty-second NMOS transistor (MC4), the fifty-fourth NMOS transistor (MC9), and the fifty-sixth NMOS transistor (MC11) , the source electrode of the fifty-eighth NMOS transistor (MC17), the sixty-first NMOS transistor (MC24) is grounded (GND), the gate of the forty-fourth PMOS transistor (MC5) is connected to the forty-fifth PMOS transistor (MC6) The gate and drain of the gate are connected to the drain of the aforementioned fifty-first NMOS transistor (MC3), and the source of the forty-fourth PMOS transistor (MC5) is connected to the drain of the forty-fifth PMOS transistor (MC6). After being connected, it is connected to the source of the forty-sixth PMOS transistor (MC7), and the gate and drain of the forty-sixth PMOS transistor (MC7) are connected to the drain of the aforementioned fifty-third NMOS transistor (MC8). Connected as the sixth bias voltage (VCb3), the second bias voltage (Vb3) is connected to the forty-seventh PMOS transistor (MC12), the forty-ninth PMOS transistor (MC14), and the fifty-first PMOS transistor (MC19) It is connected to the gate of the fifty-third PMOS transistor (MC21), and the drain of the forty-seventh PMOS transistor (MC12) is connected to the aforementioned fifty-fifth N The drain of the MOS transistor (MC10) is connected, the source of the forty-seventh PMOS transistor (MC12) is connected to the drain of the forty-eighth PMOS transistor (MC13), and the gate of the forty-eighth PMOS transistor (MC13) is connected to the drain electrode of the forty-eighth PMOS transistor (MC13). The gate of the fiftieth PMOS transistor (MC15) is connected to the drain of the forty-seventh PMOS transistor (MC12) as the seventh bias voltage (VCb4), and the fourth bias voltage (Vb4) is the same as the fifth The gate of the twelve PMOS transistor (MC20) is connected to the gate of the fifty-fourth PMOS transistor (MC22), the source of the forty-ninth PMOS transistor (MC14) is connected to the drain of the fiftieth PMOS transistor (MC15), and the fourth The drain of the nineteenth PMOS transistor (MC14) is connected to the drain of the aforementioned fifty-seventh NMOS transistor (MC16), and the source of the fifty-first PMOS transistor (MC19) is connected to the drain of the fifty-second PMOS transistor (MC20). The drain of the fifty-first PMOS transistor (MC19) is connected to the drain of the aforementioned fifty-ninth NMOS transistor (MC18), and the source of the fifty-third PMOS transistor (MC21) is connected to the fifty-fourth PMOS transistor (MC22) is connected to the drain, the drain of the fifty-third PMOS transistor (MC21) is connected to the drain of the aforementioned sixtieth NMOS transistor (MC23), the forty-fifth PMOS transistor (MC6), the forty-eighth PMOS The sources of the tube (MC13), the fiftieth PMOS tube (MC15), the fifty-second PMOS tube (MC20), and the fifty-fourth PMOS tube (MC22) are connected to the power supply voltage (VDD), and the fourth bias current source ( The anode of IC1) is connected to the drain of the sixty-second NMOS transistor (MK9), the gate of the sixty-second NMOS transistor (MK9) is connected to the ninth control word (EN9), and the fifth bias current source (IC2) The anode is connected to the drain of the sixty-third NMOS transistor (MK10), the gate of the sixty-third NMOS transistor (MK10) is connected to the tenth control word (EN10), and the source of the sixty-second NMOS transistor (MK9) is connected to The source of the sixty-third NMOS transistor ( MK10 ) is connected to the drain of the forty-ninth NMOS transistor ( MC1 ).

Optionally, the loop-folded transconductance operational amplifier circuit with N-type and P-type complementary inputs also includes: a common-mode feedback circuit; the common-mode feedback circuit includes: a fully differential signal and a common-mode signal input transistor unit, a bias voltage A transistor unit and a common mode feedback control signal generating unit.

In the embodiment of the present invention, FIG. 3 is a connection diagram of a common mode feedback circuit. N-type transistors M25, M26, M27, and M28 are the input transistors of the common-mode feedback circuit, wherein the gate of transistor M25 is connected to the full differential output signal VOUTN, the gate of transistor M28 is connected to another full differential output signal VOUTP, and transistors M26 and M27 The gate of the gate is connected to the common-mode input voltage VCM. Transistors M29 and M30 provide bias current for the input transistors, and gates of M29 and M30 are connected to bias voltage Vb1. The voltage difference of the input transistors M25, M28 and M26, M27 generates the common mode control signal VCMFB used by the OTA in FIG. 1 through the transistors M31, M32 and series resistors R1, R2. VDD and GND can be power supply voltages of 2.5V and 0V, respectively.

The fully differential signal and common mode signal input transistor unit includes: a sixty-fourth NMOS transistor (M25), a sixty-fifth NMOS transistor (M26), a sixty-sixth NMOS transistor (M27) and a sixty-seventh NMOS transistor ( M28);

Wherein, the gate of the sixty-fourth NMOS transistor (M25) is connected to the output differential signal VOUTN, the gate of the sixty-seventh NMOS transistor (M28) is connected to the other output differential signal VOUTP, and the sixty-fifth NMOS transistor The gate of (M26) is connected to the gate of the sixty-sixth NMOS transistor (M27) and then connected to the common mode input voltage (VCM).

The bias voltage transistor unit includes: a sixty-eighth NMOS transistor (M29) and a sixty-ninth NMOS transistor (M30);

Wherein, the drain of the sixty-eighth NMOS transistor (M29) is connected to the source of the sixty-fourth NMOS transistor (M25) and the source of the sixty-fifth NMOS transistor (M26), and the sixty-ninth NMOS transistor The drain of (M30) is connected to the source of the sixty-sixth NMOS transistor (M27) and the source of the sixty-seventh NMOS transistor (M28), and the gate of the sixty-eighth NMOS transistor (M29) is connected to the source of the sixth NMOS transistor (M29). The gate of the sixty-ninth NMOS transistor (M30) is connected to the first bias voltage (Vb1), and the source of the sixty-eighth NMOS transistor (M29) is connected to the source of the sixty-ninth NMOS transistor (M30). pole ground (GND).

The common-mode feedback control signal generation unit includes: a fifty-fifth PMOS transistor (M31), a fifty-sixth PMOS transistor (M32) and two resistors connected in series, that is, the first resistor R1 and the second resistor R1 connected in series with each other Resistor R2;

Wherein, the gate of the fifty-fifth PMOS transistor (M31) is connected to the gate of the fifty-sixth PMOS transistor (M32) and then connected to the serial connection end of the resistor R1 and the resistor R2, and the fifty-fifth PMOS transistor (M31) The drain of the resistor R1 is connected to the non-serial connection end of the resistor R1, and then connected to the drain of the sixty-fourth NMOS transistor (M25) and the drain of the sixty-seventh NMOS transistor (M28), and then connected to the common mode control signal ( VCMFB), the drain of the fifty-sixth PMOS transistor (M32) is connected to the non-serial end of the resistor R2 and then connected to the drain of the sixty-fifth NMOS transistor (M26) and the sixty-sixth NMOS transistor (M27 ) is connected to the drain, and the source of the fifty-fifth PMOS transistor (M31) and the source of the fifty-sixth PMOS transistor (M32) are connected to the power supply voltage (VDD).

Embodiments of the present invention include: a loop-folded transconductance operational amplifier circuit with complementary input of N-type and P-type connected to each other and a data-driven operational amplifier bias circuit; the data-driven operational amplifier bias circuit includes an input differential signal comparator ; The input differential signal comparator is used to detect the input differential signal, and increase the bias current of the circuit when the input differential signal is greater than or equal to the opening threshold of the input differential signal comparator, when the input differential signal When the signal is smaller than the opening threshold of the input differential signal comparator, the bias current of the holding circuit does not change. Through the solution of this embodiment, the speed of the high-performance switched capacitor circuit is improved, the power consumption is reduced, the yield rate is improved, and it has the advantages of high speed and high linearity.

In the embodiment of the present invention, the differential input signal is compared by the comparator (COMP1, COMP2) to detect the virtual ground state of the positive and negative input terminals (VINN, VINP) of the closed-loop amplifier, and the output level of the comparator is used to control the current source, such as The output level control switch (MS1, MS2) of the comparator can increase the bias current when the differential input signal is large, improve the speed of the circuit, and dynamically adjust the amplifier current according to the application requirements, as well as the comparator open threshold and The comparator speed controls the operating window for high currents. This circuit is suitable for switched capacitor circuits with large load capacitance, such as analog-to-digital conversion circuits, filters, etc., which can increase the speed of the circuit, reduce power consumption, and improve yield. It can meet different application requirements through configuration, and is in line with current research on integrated circuits. and the direction of development.

Although the implementation manner disclosed in the embodiment of the present invention is as above, the content described is only the implementation manner adopted for understanding the present invention, and is not intended to limit the embodiment of the present invention. Any person skilled in the field of the embodiments of the present invention can make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed by the embodiments of the present invention, but the embodiments of the present invention The scope of patent protection must still be subject to the scope defined in the appended claims.

Claims (10)

1. A data-driven operational amplifier, characterized in that, said operational amplifier comprises: a circularly folded transconductance operational amplifier circuit of interconnected N-type and P-type complementary inputs and a data-driven operational amplifier bias circuit; A data-driven operational amplifier bias circuit including an input differential signal comparator; The input differential signal comparator is used to detect the input differential signal, and increase the bias current of the circuit when the input differential signal is greater than or equal to the opening threshold of the input differential signal comparator, when the input differential signal When it is less than the opening threshold of the input differential signal comparator, the bias current of the holding circuit will not change. 2. The operational amplifier of data drive according to claim 1, is characterized in that, the circular folding transconductance operational amplifier circuit of described N type and P type complementary input comprises: An N-type complementary input differential pair unit and an N-type bias voltage transistor unit, an N-type bias tail current transistor unit, and an N-type cascode transistor pair unit connected to the N-type complementary input differential pair unit; and, A P-type complementary input differential pair unit and a P-type bias voltage transistor unit, a P-type bias tail current transistor unit, and a P-type cascode transistor pair unit connected to the P-type complementary input differential pair unit. 3. The operational amplifier driven by data according to claim 2, characterized in that, The N-type complementary input differential pair unit includes: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor; wherein, the gates of the first NMOS transistor and the second NMOS transistor are both connected to the first differential signal VINN in the input differential signal; the gates of the third NMOS transistor and the fourth NMOS transistor are both connected to the second differential signal VINP in the input differential signal; The N-type bias voltage transistor unit includes: a fifth NMOS transistor; the gate of the fifth NMOS transistor is connected to the first bias voltage, the source is grounded, and the drain is connected to the first NMOS transistor and the second NMOS transistor. The sources of the transistor, the third NMOS transistor and the fourth NMOS transistor are connected. 4. The operational amplifier driven by data according to claim 3, characterized in that, The P-type complementary input differential pair unit includes: a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, and a twelfth PMOS transistor; wherein, the gates of the ninth PMOS transistor and the tenth PMOS transistor Both poles are connected to the first differential signal VINN; the gates of the eleventh PMOS transistor and the gates of the twelfth PMOS transistor are both connected to the second differential signal VINP; The P-type bias tail current transistor unit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor; wherein, the gate of the first PMOS transistor is connected to the second PMOS transistor connected to the gate of the fourth NMOS transistor and then connected to the drain of the fourth NMOS transistor; the gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor and then connected to the drain of the second NMOS transistor connected, the sources of the first PMOS transistor, the second PMOS transistor, the third PMOS transistor and the fourth PMOS transistor are connected to a power supply voltage; The P-type cascode transistor pair unit includes: a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, and an eighth PMOS transistor; wherein, the gate of the fifth PMOS transistor is connected to the sixth PMOS transistor The gate of the transistor is connected to the second bias voltage after being connected; the gate of the seventh PMOS transistor is also connected to the second bias voltage after being connected to the gate of the eighth PMOS transistor; The source of the PMOS transistor is connected to the drain of the second PMOS transistor, the source of the sixth PMOS transistor is connected to the drain of the third PMOS transistor, and the drain of the fifth PMOS transistor is connected to the drain of the fifth PMOS transistor. The drain of the fourth NMOS transistor is connected, the drain of the sixth PMOS transistor is connected to the drain of the second NMOS transistor, and the source of the seventh PMOS transistor is connected to the drain of the first NMOS transistor and then connected to the drain of the first PMOS transistor, the source of the eighth PMOS transistor is connected to the drain of the third NMOS transistor and then connected to the drain of the fourth PMOS transistor; The P-type bias voltage transistor unit includes: a thirteenth PMOS transistor; the gate of the thirteenth PMOS transistor is connected to the common mode control signal, the source is connected to the power supply voltage, and the drain is connected to the ninth PMOS transistor. tube, the tenth PMOS tube, the eleventh PMOS tube and the sources of the twelfth PMOS tube are connected. 5. The operational amplifier driven by data according to claim 4, characterized in that, The N-type bias tail current transistor unit includes: a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, and a ninth NMOS transistor; wherein the gate of the sixth NMOS transistor is connected to the gate of the seventh NMOS transistor The gate is connected to the drain of the twelfth PMOS transistor, and the gate of the eighth NMOS transistor is connected to the gate of the ninth NMOS transistor and then connected to the drain of the tenth PMOS transistor. connected, the sources of the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, and the ninth NMOS transistor are grounded; The N-type cascode transistor pair unit includes: a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, and a thirteenth NMOS transistor; wherein, the gate of the tenth NMOS transistor is connected to the The gate of the eleventh NMOS transistor is connected to the third bias voltage, and the gate of the twelfth NMOS transistor is connected to the gate of the thirteenth NMOS transistor and then connected to the third bias voltage. The source of the tenth NMOS transistor is connected to the drain of the seventh NMOS transistor, the source of the eleventh NMOS transistor is connected to the drain of the eighth NMOS transistor, and the tenth NMOS transistor The drain of the transistor is connected to the drain of the twelfth PMOS transistor, the drain of the eleventh NMOS transistor is connected to the drain of the tenth PMOS transistor, and the source of the twelfth NMOS transistor is connected to the drain of the tenth PMOS transistor. The drain of the ninth PMOS transistor is connected to the drain of the sixth NMOS transistor, and the source of the thirteenth NMOS transistor is connected to the drain of the eleventh PMOS transistor and then connected to the drain of the eleventh PMOS transistor. connected to the drain of the ninth NMOS transistor. 6. The operational amplifier driven by data according to claim 5, characterized in that, The drain of the seventh PMOS transistor is connected to the drain of the twelfth NMOS transistor to output a first output differential signal VOUTP, and the drain of the eighth PMOS transistor is connected to the drain of the thirteenth NMOS transistor A second output differential signal VOUTN is output, and the first output differential signal VOUTP and the second output differential signal VOUTN together constitute a fully differential output signal. 7. The operational amplifier driven by data according to claim 1 or 5, characterized in that, the operational amplifier bias circuit driven by the data comprises: a bias voltage generation circuit, an input differential signal comparator and a data-driven current branch . 8. The operational amplifier driven by data according to claim 7, characterized in that, The bias voltage generation circuit includes: a first bias current source, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor tube, the twenty-first NMOS tube, the twenty-first NMOS tube, the twenty-second NMOS tube, the twenty-third NMOS tube, the twenty-fourth NMOS tube, the twenty-fifth NMOS tube, the twenty-sixth NMOS tube, Twenty-seventh NMOS tube, twenty-eighth NMOS tube, twenty-ninth NMOS tube, fourteenth PMOS tube, fifteenth PMOS tube, sixteenth PMOS tube, seventeenth PMOS tube, eighteenth PMOS tube , the nineteenth PMOS tube, the twentieth PMOS tube, the twenty-first PMOS tube, the twenty-second PMOS tube, the twenty-third PMOS tube, the twenty-fourth PMOS tube, the twenty-fifth PMOS tube, the second Sixteen PMOS tubes and twenty-seventh PMOS tubes; Wherein, the negative electrode of the first bias current source is connected to the power supply voltage, the positive electrode of the first bias current source is connected to the drain of the fourteenth NMOS transistor, and then connected to the fourteenth NMOS transistor, Gates of the fifteenth NMOS transistor, the sixteenth NMOS transistor, the seventeenth NMOS transistor, the eighteenth NMOS transistor, the nineteenth NMOS transistor, the twentieth NMOS transistor, and the twenty-first NMOS transistor are connected, and the gates of the first NMOS transistor The source of the fourteenth NMOS transistor is connected to the drain of the fifteenth NMOS transistor, the source of the sixteenth NMOS transistor is connected to the drain of the seventeenth NMOS transistor, and the eighteenth NMOS transistor The source of the twentieth NMOS transistor is connected to the drain of the nineteenth NMOS transistor, the source of the twentieth NMOS transistor is connected to the drain of the twenty-first NMOS transistor, and the drain of the twenty-second NMOS transistor and then connected to the gate of the twenty-third NMOS transistor and the twenty-fourth NMOS transistor, the source of the twenty-second NMOS transistor is connected to the gate of the twenty-third NMOS transistor connected to the drain of the twenty-fourth NMOS transistor and then connected to the source of the twenty-fifth NMOS transistor; the source of the twenty-third NMOS transistor is connected to the source of the twenty-eighth NMOS transistor connected to the drain, the source of the twenty-fourth NMOS transistor is connected to the drain of the twenty-ninth NMOS transistor, the gate of the twenty-eighth NMOS transistor is connected to the first control word, and the second The gate of the nineteenth NMOS transistor is connected to the second control word, the gate of the twenty-fifth NMOS transistor is connected to the drain and then connected to the gate of the twenty-sixth NMOS transistor as the third bias voltage, The drain of the twenty-sixth NMOS transistor is connected to the gate of the twenty-seventh NMOS transistor as the first bias voltage, and the source of the twenty-sixth NMOS transistor is connected to the gate of the twenty-seventh NMOS transistor. The drains of the seven NMOS transistors are connected, and the fifteenth NMOS transistor, the seventeenth NMOS transistor, the nineteenth NMOS transistor, the twenty-first NMOS transistor, the twenty-seventh NMOS transistor, the twenty-eighth NMOS transistor and the The source of the twenty-ninth NMOS transistor is grounded, the gate and drain of the fourteenth PMOS transistor are connected to the gate of the fifteenth PMOS transistor and the gate of the sixteenth PMOS transistor, and then connected to the gate of the sixteenth PMOS transistor. The drain of the sixteenth NMOS transistor is connected, the source of the fourteenth PMOS transistor is connected to the drain of the fifteenth PMOS transistor and the drain of the sixteenth PMOS transistor, and then connected to the drain of the sixteenth PMOS transistor. The source of the seventeenth PMOS transistor is connected, the source of the fifteenth PMOS transistor is connected to the drain of the twenty-sixth PMOS transistor, the source of the sixteenth PMOS transistor is connected to the drain of the twenty-seventh PMOS transistor The gate of the twenty-sixth PMOS transistor is connected to the third control word, the gate of the twenty-seventh PMOS transistor is connected to the fourth control word, and the gate and drain of the seventeenth PMOS transistor After being connected, it is connected to the drain of the eighteenth NMOS transistor as the second bias voltage, and the second bias voltage is connected to the eighteenth PMOS transistor, the twenty-second PMOS transistor, the twenty-second The PMOS transistor is connected to the gate of the twenty-fourth PMOS transistor, and the The drain of the eighteenth PMOS transistor is connected to the drain of the twentieth NMOS transistor, the source of the eighteenth PMOS transistor is connected to the drain of the nineteenth PMOS transistor, and the nineteenth PMOS transistor The gate of the transistor is connected to the gate of the twenty-first PMOS transistor and then connected to the drain of the eighteenth PMOS transistor as a fourth bias voltage, and the fourth bias voltage is connected to the second The thirteenth PMOS transistor is connected to the gate of the twenty-fifth PMOS transistor, the source of the twenty-first PMOS transistor is connected to the drain of the twenty-first PMOS transistor, and the drain of the twenty-first PMOS transistor connected to the drain of the twenty-second NMOS transistor, the source of the twenty-second PMOS transistor is connected to the drain of the twenty-third PMOS transistor, and the drain of the twenty-second PMOS transistor connected to the drain of the twenty-fifth NMOS transistor, the source of the twenty-fourth PMOS transistor is connected to the drain of the twenty-fifth PMOS transistor, and the drain of the twenty-fourth PMOS transistor connected to the drain of the twenty-sixth NMOS transistor, the nineteenth PMOS transistor, the twenty-first PMOS transistor, the twenty-third PMOS transistor, the twenty-fifth PMOS transistor, the twenty-sixth PMOS transistor, The source of the twenty-seventh PMOS tube is connected to the power supply voltage; The input differential signal comparator includes: a first comparator and a second comparator; wherein, the negative input terminal of the first comparator and the positive input terminal of the second comparator are connected to the first differential signal VINN , the positive input terminal of the first comparator and the negative input terminal of the second comparator are connected to the second differential signal VINP, the first comparator outputs a first control signal VC1, and the second comparator Outputting the second control signal VC2; The data driving current branch includes: a second bias current source, a third bias current source, a 30th NMOS transistor, a 31st NMOS transistor, a 32nd NMOS transistor, a 33rd NMOS transistor, Thirty-fourth NMOS tube and thirty-fifth NMOS tube; Wherein, the negative electrode of the second bias current source and the negative electrode of the third bias current source are connected to the power supply voltage, the source of the 30th NMOS transistor is connected to the source of the 31st NMOS transistor After being connected, it is connected to the anode of the second bias current source, the grid of the 30th NMOS transistor is connected to the first control signal VC1, and the grid of the 31st NMOS transistor is connected to the second Control signal VC2, the drain of the 30th NMOS transistor is connected to the drain of the 31st NMOS transistor and then connected to the drain of the 34th NMOS transistor, the 34th NMOS transistor The gate of the transistor is connected to the fifth control word, the source of the thirty-second NMOS transistor is connected to the source of the thirty-third NMOS transistor and then connected to the anode of the third bias current source, The gate of the thirty-second NMOS transistor is connected to the first control signal VC1, the gate of the thirty-third NMOS transistor is connected to the second control signal VC2, and the drain of the thirty-second NMOS transistor connected to the drain of the thirty-third NMOS transistor and then connected to the drain of the thirty-fifth NMOS transistor; the gate of the thirty-fifth NMOS transistor is connected to the sixth control word; The source of the thirty-fourth NMOS transistor and the source of the thirty-fifth NMOS transistor are connected to the drain of the fourteenth NMOS transistor. 9. The data-driven operational amplifier according to claim 8, wherein the first comparator and the second comparator both comprise: a comparator main circuit and a bias circuit with adjustable bias current; The comparator main circuit includes: a thirty-sixth NMOS transistor, a thirty-seventh NMOS transistor, a thirty-eighth NMOS transistor, a thirty-ninth NMOS transistor, a fortieth NMOS transistor, a forty-first NMOS transistor, a Forty-two NMOS tubes, forty-third NMOS tubes, forty-fourth NMOS tubes, forty-fifth NMOS tubes, forty-sixth NMOS tubes, forty-seventh NMOS tubes, forty-eighth NMOS tubes, and second The eighteenth PMOS tube, the twenty-ninth PMOS tube, the thirty-first PMOS tube, the thirty-first PMOS tube, the thirty-second PMOS tube, the thirty-third PMOS tube, the thirty-fourth PMOS tube, the thirty-fifth PMOS tube, thirty-sixth PMOS tube, thirty-seventh PMOS tube, thirty-eighth PMOS tube, thirty-ninth PMOS tube, fortieth PMOS tube, forty-first PMOS tube, forty-second PMOS tube and the forty-third PMOS tube; Wherein, the gates of the thirty-sixth NMOS transistor and the thirty-seventh NMOS transistor are connected to the third differential signal VCN in the input differential signal, and the thirty-eighth NMOS transistor and the thirty-ninth NMOS transistor The gates of the transistors are all connected to the fourth differential signal VCP in the input differential signal, the grid of the fortieth NMOS transistor is connected to the fifth bias voltage, the source is grounded, and the drain is connected to the thirty-sixth NMOS transistor. tube, the sources of the thirty-seventh NMOS tube, the thirty-eighth NMOS tube, and the thirty-ninth NMOS tube, and the gate of the twenty-eighth PMOS tube is connected to the gate of the twenty-ninth PMOS tube Then it is connected to the drain of the thirty-ninth NMOS transistor, and the sources of the twenty-eighth PMOS transistor, the twenty-ninth PMOS transistor, the thirty-first PMOS transistor and the thirty-first PMOS transistor are connected to the power supply voltage , the gate of the thirty-second PMOS transistor is connected to the gate of the thirty-third PMOS transistor and then connected to the sixth bias voltage, and the gate of the thirty-fourth PMOS transistor is connected to the gate of the thirty-third PMOS transistor. The gates of the five PMOS transistors are connected to the sixth bias voltage, the source of the thirty-second PMOS transistor is connected to the drain of the twenty-ninth PMOS transistor, and the thirty-third PMOS transistor is connected to the drain of the twenty-ninth PMOS transistor. The source of the transistor is connected to the drain of the thirtieth PMOS transistor, the drain of the thirty-second PMOS transistor is connected to the drain of the thirty-ninth NMOS transistor, and the thirty-third PMOS transistor The drain of the thirty-seventh NMOS transistor is connected to the drain, the source of the thirty-fourth PMOS transistor is connected to the drain of the thirty-sixth NMOS transistor, and then connected to the twenty-eighth NMOS transistor. The drain of the PMOS transistor is connected, the source of the thirty-fifth PMOS transistor is connected to the drain of the thirty-eighth NMOS transistor and then connected to the drain of the thirty-first PMOS transistor, and the source of the thirty-eighth PMOS transistor is connected to the drain of the thirty-first PMOS transistor. The gates of the thirty-sixth PMOS transistor and the thirty-seventh PMOS transistor are connected to the third differential signal VCN, and the gates of the thirty-eighth PMOS transistor and the thirty-ninth PMOS transistor are connected to the fourth differential signal VCN. The differential signal VCP is connected, the gates of the fortieth PMOS transistor and the forty-first PMOS transistor are connected to the seventh bias voltage, and the source of the fortieth PMOS transistor is connected to the drain of the forty-second PMOS transistor pole, the source of the forty-first PMOS transistor is connected to the drain of the forty-third PMOS transistor, the gate of the forty-second PMOS transistor is connected to the seventh control word, and the forty-third PMOS transistor The gate of the transistor is connected to the eighth control word, the sources of the forty-second PMOS transistor and the forty-third PMOS transistor are connected to the power supply voltage, and the drains of the fortieth PMOS transistor and the forty-first PMOS transistor are connected to the sources of the thirty-sixth PMOS transistor, the thirty-seventh PMOS transistor, the thirty-eighth PMOS transistor, and the thirty-ninth PMOS transistor, and the gate of the forty-first NMOS transistor is connected to the first The gate of the forty-second NMOS transistor is connected to the drain of the thirty-ninth PMOS transistor, and the gate of the forty-third NMOS transistor is connected to the gate of the forty-fourth NMOS transistor. It is then connected to the drain of the thirty-seventh PMOS transistor, so The sources of the forty-first NMOS transistor, the forty-second NMOS transistor, the forty-third NMOS transistor, and the forty-fourth NMOS transistor are grounded, and the gate of the forty-fifth NMOS transistor is connected to the forty-fifth NMOS transistor. The gates of the six NMOS transistors are connected to the eighth bias voltage, and the gates of the forty-seventh NMOS transistor are connected to the gates of the forty-eighth NMOS transistors and then connected to the eighth bias voltage, The source of the forty-fifth NMOS transistor is connected to the drain of the forty-second NMOS transistor, the source of the forty-sixth NMOS transistor is connected to the drain of the forty-third NMOS transistor, The drain of the forty-fifth NMOS transistor is connected to the drain of the thirty-ninth PMOS transistor, the drain of the forty-sixth NMOS transistor is connected to the drain of the thirty-seventh PMOS transistor, The source of the forty-seventh NMOS transistor is connected to the drain of the thirty-sixth PMOS transistor and then connected to the drain of the forty-first NMOS transistor, and the source of the forty-eighth NMOS transistor The electrode is connected to the drain of the thirty-eighth PMOS transistor and then connected to the drain of the forty-fourth NMOS transistor, and the drain of the forty-eighth NMOS transistor is connected to the drain of the thirty-fifth PMOS transistor The drain is connected to the gate of the 30th PMOS transistor and the gate of the thirty-first PMOS transistor, and the forty-seventh NMOS transistor is connected to the thirty-fourth PMOS transistor as Comparator output VCOUT; The bias circuit with adjustable bias current includes: a fourth bias current source, a fifth bias current source, a forty-ninth NMOS transistor, a fiftieth NMOS transistor, a fifty-first NMOS transistor, a fiftieth NMOS transistor Two NMOS tubes, fifty-third NMOS tubes, fifty-fourth NMOS tubes, fifty-fifth NMOS tubes, fifty-sixth NMOS tubes, fifty-seventh NMOS tubes, fifty-eighth NMOS tubes, fifty-ninth NMOS tubes NMOS tube, sixtieth NMOS tube, sixty-first NMOS tube, sixty-second NMOS tube, sixty-third NMOS tube, forty-fourth PMOS tube, forty-fifth PMOS tube, forty-sixth PMOS tube , the forty-seventh PMOS transistor, the forty-eighth PMOS transistor, the forty-ninth PMOS transistor, the fiftieth PMOS transistor, the fifty-first PMOS transistor, the fifty-second PMOS transistor, the fifty-third PMOS transistor, and the fifty-third PMOS transistor Fifty-four PMOS tubes; Wherein, the negative electrode of the fourth bias current source and the negative electrode of the fifth bias current source are connected to the power supply voltage, and the drain of the forty-ninth NMOS transistor is connected to the forty-ninth NMOS transistor, the first The gates of the fifty NMOS transistors, the fifty-first NMOS transistors, the fifty-second NMOS transistors, the fifty-third NMOS transistors, the fifty-fourth NMOS transistors, the fifty-fifth NMOS transistors, and the fifty-sixth NMOS transistors are connected to each other. , the source of the forty-ninth NMOS transistor is connected to the drain of the fiftieth NMOS transistor, the source of the fifty-first NMOS transistor is connected to the drain of the fifty-second NMOS transistor, The source of the fifty-third NMOS transistor is connected to the drain of the fifty-fourth NMOS transistor, the source of the fifty-fifth NMOS transistor is connected to the drain of the fifty-sixth NMOS transistor, The drain of the fifty-seventh NMOS transistor is connected to the gate and then connected to the gate of the fifty-eighth NMOS transistor, and the source of the fifty-seventh NMOS transistor is connected to the gate of the fifty-eighth NMOS transistor. The drain of the transistor is connected to the source of the fifty-ninth NMOS transistor, and the gate of the fifty-ninth NMOS transistor is connected to the drain and then connected to the gate of the sixtieth NMOS transistor. As the eighth bias voltage, the drain of the sixtieth NMOS transistor is connected to the gate of the sixty-first NMOS transistor as the fifth bias voltage, and the source of the sixtieth NMOS transistor The pole is connected to the drain of the sixty-first NMOS transistor, and the fifty-second NMOS transistor, the fifty-second NMOS transistor, the fifty-fourth NMOS transistor, the fifty-sixth NMOS transistor, and the fifty-eighth NMOS transistor , the source of the sixty-first NMOS transistor is grounded, the gate of the forty-fourth PMOS transistor is connected to the gate and drain of the forty-fifth PMOS transistor and then connected to the fifty-first NMOS transistor connected to the drain of the forty-fourth PMOS transistor, the source of the forty-fourth PMOS transistor is connected to the drain of the forty-fifth PMOS transistor and then connected to the source of the forty-sixth PMOS transistor, and the fortieth The gates and drains of the six PMOS transistors are connected and then connected to the drain of the fifty-third NMOS transistor as the sixth bias voltage, and the second bias voltage is the same as that of the forty-seventh PMOS transistor , the gates of the forty-ninth PMOS transistor, the fifty-first PMOS transistor and the fifty-third PMOS transistor are connected, and the drain of the forty-seventh PMOS transistor is connected with the drain of the fifty-fifth NMOS transistor , the source of the forty-seventh PMOS transistor is connected to the drain of the forty-eighth PMOS transistor, and the gate of the forty-eighth PMOS transistor is connected to the gate of the fiftieth PMOS transistor connected to the drain of the forty-seventh PMOS transistor as the seventh bias voltage, and the fourth bias voltage is connected to the gates of the fifty-second PMOS transistor and the fifty-fourth PMOS transistor , the source of the forty-ninth PMOS transistor is connected to the drain of the fiftieth PMOS transistor, and the drain of the forty-ninth PMOS transistor is connected to the drain of the fifty-seventh NMOS transistor, The source of the fifty-first PMOS transistor and the source of the fifty-second PMOS transistor The drain of the fifty-first PMOS transistor is connected to the drain of the fifty-ninth NMOS transistor, and the source of the fifty-third PMOS transistor is connected to the drain of the fifty-fourth PMOS transistor. The drains of the fifty-third PMOS transistors are connected to the drains of the sixtieth NMOS transistors, the forty-fifth PMOS transistors, the forty-eighth PMOS transistors, the fiftieth PMOS transistors, The sources of the fifty-second PMOS transistor and the fifty-fourth PMOS transistor are connected to the power supply voltage, the anode of the fourth bias current source is connected to the drain of the sixty-second NMOS transistor, and the sixth The gate of the twelve NMOS transistors is connected to the ninth control word, the anode of the fifth bias current source is connected to the drain of the sixty-third NMOS transistor, and the gate of the sixty-third NMOS transistor is connected to the In the tenth control word, the sources of the sixty-second NMOS transistor and the sixty-third NMOS transistor are connected to the drain of the forty-ninth NMOS transistor. 10. The operational amplifier driven by data according to claim 8, characterized in that, the loop folding transconductance operational amplifier circuit of said N-type and P-type complementary input also comprises: a common-mode feedback circuit; said common-mode feedback circuit Including: fully differential signal and common mode signal input transistor unit, bias voltage transistor unit and common mode feedback control signal generation unit; The fully differential signal and common mode signal input transistor unit includes: a sixty-fourth NMOS transistor, a sixty-fifth NMOS transistor, a sixty-sixth NMOS transistor, and a sixty-seventh NMOS transistor; Wherein, the gate of the sixty-fourth NMOS transistor is connected to the second output differential signal VOUTN, the gate of the sixty-seventh NMOS transistor is connected to the first output differential signal VOUTP, and the sixty-fifth The gate of the NMOS transistor is connected to the gate of the sixty-sixth NMOS transistor and then connected to the common mode input voltage VCM; The bias voltage transistor unit includes: a sixty-eighth NMOS transistor and a sixty-ninth NMOS transistor; Wherein, the drain of the sixty-eighth NMOS transistor is connected to the source of the sixty-fourth NMOS transistor and the source of the sixty-fifth NMOS transistor, and the drain of the sixty-ninth NMOS transistor The source of the sixty-sixth NMOS transistor is connected to the source of the sixty-seventh NMOS transistor, and the gate of the sixty-eighth NMOS transistor is connected to the gate of the sixty-ninth NMOS transistor connected to the first bias voltage, the source of the sixty-eighth NMOS transistor and the source of the sixty-ninth NMOS transistor are grounded; The common-mode feedback control signal generation unit includes: a fifty-fifth PMOS transistor, a fifty-sixth PMOS transistor, and a first resistor R1 and a second resistor R2 connected in series; Wherein, the gate of the fifty-fifth PMOS transistor is connected to the gate of the fifty-sixth PMOS transistor and then connected to the serial terminal of the first resistor R1 and the second resistor R2, and the fifty-fifth The drain of the fifth PMOS transistor is connected to the non-serial connection end of the first resistor R1 and then connected to the drain of the sixty-fourth NMOS transistor and the drain of the sixty-seventh NMOS transistor, and connected to It is followed by a common mode control signal VCMFB, and the drain of the fifty-sixth PMOS transistor is connected to the non-serial end of the second resistor R2, and then connected to the drain of the sixty-fifth NMOS transistor and the sixtieth The drains of the six NMOS transistors are connected, and the sources of the fifty-fifth PMOS transistor and the fifty-sixth PMOS transistor are connected to the power supply voltage.