CN107481991B - Package substrate, electronic package and manufacturing method thereof - Google Patents
Package substrate, electronic package and manufacturing method thereof Download PDFInfo
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- CN107481991B CN107481991B CN201610504135.0A CN201610504135A CN107481991B CN 107481991 B CN107481991 B CN 107481991B CN 201610504135 A CN201610504135 A CN 201610504135A CN 107481991 B CN107481991 B CN 107481991B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A package substrate, an electronic package and a fabrication method thereof are provided, the package substrate includes: the packaging substrate comprises an insulating protective layer, a circuit layer embedded in the insulating protective layer and not penetrating through the insulating protective layer, and a conductive column penetrating through the insulating protective layer and electrically connected with the circuit layer, so that the packaging substrate only comprises one circuit layer without using a core layer, and the thickness of the packaging substrate can be greatly reduced.
Description
Technical Field
The present invention relates to a package substrate, and more particularly, to a coreless package substrate, an electronic package thereof, and a method for fabricating the same.
Background
With the rapid development of the electronic industry, many high-grade electronic products are gradually developed in the direction of light, thin, short, small and high-level integration, and with the evolution of the packaging technology, the packaging technology of the chip is more and more diversified, and the size or volume of the semiconductor package is also continuously reduced, so as to make the semiconductor package achieve the purpose of light, thin, short and small
Fig. 1 is a schematic cross-sectional view of a conventional flip-chip semiconductor package 1. As shown in fig. 1, the semiconductor package 1 includes a package substrate 1a and a semiconductor device 9.
The package substrate 1a includes: a core layer 10; a first circuit layer 12a and a second circuit layer 12b formed on the surface of the core layer 10; a conductive via 13 penetrating the core layer 10 to electrically connect the first circuit layer 12a and the second circuit layer 12 b; a first insulating layer 11a and a second insulating layer 11b respectively formed on the first circuit layer 12a and the second circuit layer 12b and exposing a portion of the first circuit layer 12a and the second circuit layer 12 b.
The semiconductor device 9 has a plurality of electrode pads 90 for bonding a plurality of conductive bumps 91 for flip-chip bonding to the first circuit layer 12 a.
In the conventional package substrate 1a, at least two circuit layers (a first circuit layer 12a and a second circuit layer 12b) are provided, and the first circuit layer 12a and the second circuit layer 12b are electrically connected by the conductive via 13.
However, the conductive via 13 is formed in the core layer 10 by mechanical drilling or laser drilling to form a through hole 100 penetrating the core layer 10, and then copper is electroplated in the through hole 100, thereby increasing the complexity of the process.
In addition, since the conventional package substrate 1a includes the core layer 10 and at least two wiring layers, it is difficult to reduce the thickness of the package substrate 1a, and therefore, even when the thickness of the package substrate 1a is difficult to reduce, it is difficult to effectively reduce the thickness of the entire semiconductor package 1.
Therefore, how to overcome the various problems of the prior art has become an issue to be solved.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, the present invention provides a package substrate, an electronic package and a fabrication method thereof, which can greatly reduce the thickness of the package substrate.
The package substrate of the present invention includes: an insulating protection layer having a first surface and a second surface opposite to each other; a circuit layer embedded in the first surface of the insulating protection layer and exposed out of the first surface but not exposed out of the second surface; and the conductive column is penetratingly formed in the insulating protection layer, exposed out of the first surface and the second surface and electrically connected with the circuit layer.
The invention also provides a manufacturing method of the packaging substrate, which comprises the following steps: providing an insulating protection layer with a first surface and a second surface which are opposite, wherein the insulating protection layer is provided with a plurality of openings and at least one through hole, the openings are formed on the first surface and are not communicated with the second surface, and the through hole is communicated with the first surface and the second surface; and forming a circuit layer in the opening, forming a conductive column in the through hole, and electrically connecting the conductive column with the circuit layer.
In the foregoing method, the second surface of the insulating passivation layer is bonded to a carrier, and the opening and the through hole are formed. And removing the carrier after the circuit layer and the conductive post are formed.
In the package substrate and the method for fabricating the same, the insulating passivation layer is a solder mask layer.
In the foregoing package substrate and the method for fabricating the same, the surface of the circuit layer is flush with the first surface of the insulating protection layer.
In an embodiment of the package substrate and the method for manufacturing the same, the conductive pillar has a first end surface and a second end surface opposite to each other, such that the first end surface is exposed to the first surface, and the second end surface is exposed to the second surface. For example, the first end face is flush with the first surface and/or the second end face is flush with the second surface.
The present invention also provides an electronic package comprising: the package substrate described above; and the electronic element is arranged on the first surface of the insulating protective layer and is electrically connected with the conductive column.
The invention also provides a method for manufacturing the electronic package, which comprises the following steps: providing the packaging substrate; and arranging an electronic element on the first surface of the insulating protection layer, and electrically connecting the electronic element with the conductive column.
In the electronic package and the manufacturing method thereof, the first end surface of the conductive pillar is electrically connected to the electronic element.
In the electronic package and the method for manufacturing the same, a package layer is formed on the first surface of the insulating protection layer to cover the electronic element.
In addition, the electronic package and the method for manufacturing the same further include disposing a plurality of conductive elements on the second surface of the insulating passivation layer, and electrically connecting the conductive elements to the conductive pillars.
Therefore, the package substrate, the electronic package and the manufacturing method thereof of the invention do not need to use a core layer, so that the conventional conductive hole penetrating through the core layer is not required to be manufactured, and compared with the prior art, the purposes of simple manufacturing steps and cost reduction are achieved.
In addition, the thickness of the packaging substrate can be greatly reduced because the packaging substrate does not have the existing core layer, so that the overall thickness of the electronic packaging part can be effectively reduced under the condition that the thickness of the packaging substrate is reduced.
Drawings
FIG. 1 is a schematic cross-sectional view of a conventional flip-chip semiconductor package;
fig. 2A to 2E are schematic cross-sectional views illustrating a method for fabricating a package substrate according to the present invention; and
fig. 3A and 3B are schematic cross-sectional views illustrating a method for manufacturing an electronic package according to the present invention; fig. 3A 'and 3B' illustrate another embodiment of fig. 3A and 3B.
Description of the symbols:
1 semiconductor package
1a,2 Package substrate
10 core layer
100,211 through hole
11a first insulating layer
11b second insulating layer
12a first wiring layer
12b second wiring layer
13 conductive via
20 load bearing member
200 bonding layer
21 insulating protective layer
21a first surface
21b second surface
210 open pore
211' concave hole
22 circuit layer
22a surface
23 conductive post
23a first end face
23b second end face
3, 3' electronic package
30 electronic component
30a acting surface
30b non-active surface
300,90 electrode pad
31,91 conductive bump
31' bonding wire
32 conductive element
33 encapsulation layer
9 a semiconductor element.
Detailed Description
The following description of the embodiments of the present invention is provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein.
It should be understood that the structures, ratios, sizes, and the like shown in the drawings and described in the specification are only used for understanding and reading the contents disclosed in the specification, and are not used for limiting the conditions under which the present invention can be implemented, so that the present invention has no technical significance, and any structural modifications, ratio relationship changes or size adjustments should still fall within the scope of the technical contents disclosed in the present invention without affecting the efficacy and the achievable purpose of the present invention. In addition, the terms "upper", "lower", "first", "second", and "a" used in the present specification are for clarity of description, and are not intended to limit the scope of the present invention, and the relative relationship between the terms and the terms is not to be construed as a substantial change in the technical content of the present invention.
Fig. 2A to fig. 2E are schematic cross-sectional views illustrating a method for manufacturing the package substrate 2 according to the present invention.
As shown in fig. 2A to 2B, a carrier 20 is provided, and an insulating protective layer 21 is disposed on both upper and lower sides of the carrier 20, and the insulating protective layer 21 has a first surface 21a and a second surface 21B opposite to each other, and is bonded to the carrier 20 by the second surface 21B. Next, a plurality of openings 210 and a plurality of through holes 211 are formed on the first surface 21a of the insulating protection layer 21.
In the present embodiment, the carrier 20 is bonded to the insulating protection layer 21 by a bonding layer 200 (such as a release film, a metal layer or an adhesive layer).
In addition, the insulating passivation layer 21 is a solder mask, the openings 210 are not connected to the second surface 21b, and the through holes 211 are connected to the first surface 21a and the second surface 21 b.
In addition, as shown in fig. 2A, the through hole 211 is formed by forming a plurality of recesses 211' at the same time when forming the openings 210, and as shown in fig. 2B, the through hole 211' is formed at the recess 211 '.
As shown in fig. 2C, a circuit layer 22 is formed in the openings 210, and a plurality of conductive pillars 23 are formed in the through holes 211, such that the conductive pillars 23 are electrically connected to the circuit layer 22.
In the present embodiment, the circuit layer 22 is embedded in the first surface 21a of the insulating protection layer 21, and the surface 22a of the circuit layer 22 is flush with the first surface 21a of the insulating protection layer 21.
In addition, the conductive pillar 23 has a first end surface 23a corresponding to the first surface 21a and a second end surface 23b corresponding to the second surface 21b, such that the first end surface 23a is exposed to the first surface 21a and the second end surface 23b is exposed to the second surface 21 b. For example, the first surface 21a is flush with the first end surface 23a, and the second surface 21b is flush with the second end surface 23 b.
As shown in fig. 2D to 2E, the carrier 20 is removed to obtain a plurality of package substrates 2.
In the present embodiment, the carrier 20 and each of the package substrates 2 are separated by a bonding layer 200.
The manufacturing method of the packaging substrate of the invention mainly takes the insulating protection layer 21 as a main body, and avoids using a core layer, so that the existing conductive hole penetrating through the core layer is not required to be manufactured, and the manufacturing steps and the cost can be simplified.
In addition, the present invention has only one circuit layer without using the existing core layer, thereby greatly reducing the thickness of the package substrate 2.
As shown in fig. 3A and 3B, in the subsequent application of the package substrate 2, at least one electronic component 30 is disposed on the first surface 21a of the insulating protection layer 21, a packaging layer 33 such as a molding compound (molding compound) is formed on the first surface 21a of the insulating protection layer 21 to cover the electronic component 30, and a plurality of conductive elements 32 such as solder balls are formed on the second surface 21B of the insulating protection layer 21 to form the electronic package 3 of the present invention.
In the present embodiment, the conductive elements 32 are correspondingly bonded to the second end surfaces 23b of the conductive posts 23, so that the conductive elements 32 are electrically connected to the conductive posts 23.
In addition, the electronic component 30 is an active component, such as a semiconductor chip, a passive component, such as a resistor, a capacitor, and an inductor, or a combination thereof. For example, the electronic component 30 has an active surface 30a and an inactive surface 30b opposite to each other, the active surface 30a has a plurality of electrode pads 300, and the electronic component 30 is electrically connected to the conductive posts 23 through the electrode pads 300.
Specifically, as shown in fig. 3A, the electrode pads 300 of the electronic element 30 are flip-chip bonded to the first end surfaces 23A of the conductive posts 23 through a plurality of conductive bumps 31, so that the electronic element 30 is electrically connected to the conductive posts 23. Alternatively, as shown in fig. 3A ' and 3B ', the electronic component 30 is disposed on the first surface 21a of the insulating protection layer 21 by a non-active surface 30B, and a plurality of bonding wires 31 ' electrically connect the electrode pads 300 and the first end surfaces 23A of the conductive pillars 23, so that the electronic component 30 is electrically connected to the conductive pillars 23.
In the electronic package 3, 3' of the present invention, the thickness of the package substrate 2 can be reduced, and the overall thickness can be effectively reduced.
The present invention provides a package substrate 2, including: an insulating passivation layer 21, a circuit layer 22 and a plurality of conductive pillars 23.
The insulating passivation layer 21 has a first surface 21a and a second surface 21b opposite to each other, and the insulating passivation layer 21 is a solder mask.
The circuit layer 22 is embedded in the first surface 21a of the insulating protection layer 21 and exposed out of the first surface 21a and not exposed out of the second surface 21 b.
The conductive pillars 23 are penetratingly formed in the insulating protection layer 21 and exposed from the first surface 21a and the second surface 21b and electrically connected to the circuit layer 22.
In one embodiment, the surface 22a of the circuit layer 22 is flush with the first surface 21a of the insulating protection layer 21.
In one embodiment, the conductive pillar 23 has a first end surface 23a and a second end surface 23b opposite to each other, such that the first end surface 23a is exposed to the first surface 21a, and the second end surface 23b is exposed to the second surface 21 b. For example, the first surface 21a is flush with the first end surface 23a, and the second surface 21b is flush with the second end surface 23 b.
The invention also provides an electronic package 3, 3' comprising: the package substrate 2 and the electronic component 30.
The electronic component 30 is disposed on the first surface 21a of the insulating protection layer 21 and electrically connected to the conductive pillar 23.
In one embodiment, the first end surface 23a of the conductive pillar 23 is electrically connected to the electronic element 30.
In one embodiment, the electronic package 3, 3' further includes a plurality of conductive elements 32 disposed on the second surface 21b of the insulating passivation layer 21 and electrically connected to the conductive pillars 23.
In summary, the package substrate, the electronic package and the method for fabricating the same of the present invention use the insulating protection layer as a main body to avoid using a core layer, thereby eliminating the need to fabricate the conventional conductive via penetrating the core layer, simplifying the fabrication process and reducing the cost.
In addition, the thickness of the packaging substrate can be greatly reduced because the packaging substrate does not have the existing core layer, so that the thickness of the whole electronic packaging part can be effectively reduced under the condition that the thickness of the packaging substrate is reduced.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of the invention should be determined from the following claims.
Claims (26)
1. A package substrate, comprising:
the insulating protective layer is provided with a first surface and a second surface which are opposite, and an opening and a through hole are formed on the first surface;
a circuit layer embedded in the opening of the first surface of the insulating protection layer and exposed to the first surface but not to the second surface; and
and the conductive column is penetratingly formed in the through hole of the insulating protection layer, exposed out of the first surface and the second surface and electrically connected with the circuit layer, the electronic element is arranged on the first surface of the insulating protection layer and electrically connected with the conductive column, and the plurality of conductive elements are arranged on the second surface of the insulating protection layer and electrically connected with the conductive column.
2. The package substrate of claim 1, wherein the insulating passivation layer is a solder mask.
3. The package substrate of claim 1, wherein a surface of the circuit layer is flush with the first surface of the insulating protection layer.
4. The package substrate of claim 1, wherein the conductive pillar has a first end surface and a second end surface opposite to each other, such that the first end surface is exposed to the first surface and the second end surface is exposed to the second surface.
5. The package substrate of claim 4, wherein the first end face is flush with the first surface and/or the second end face is flush with the second surface.
6. A method for manufacturing a package substrate, the method comprising:
providing an insulating protection layer with a first surface and a second surface which are opposite, wherein the insulating protection layer is provided with a plurality of openings and at least one through hole, the openings are formed on the first surface and are not communicated with the second surface, and the through hole is communicated with the first surface and the second surface; and
forming a circuit layer in the opening, forming a conductive column in the through hole, and electrically connecting the conductive column to the circuit layer, wherein the first surface of the insulating protection layer is provided with an electronic element and is electrically connected to the conductive column, and the second surface of the insulating protection layer is provided with a plurality of conductive elements and is electrically connected to the conductive column.
7. The method of claim 6, wherein the insulating passivation layer is a solder mask.
8. The method of claim 6, wherein a surface of the circuit layer is flush with the first surface of the insulating protection layer.
9. The method for manufacturing the package substrate according to claim 6, wherein the conductive pillar has a first end surface and a second end surface opposite to each other, such that the first end surface is exposed to the first surface and the second end surface is exposed to the second surface.
10. The method for manufacturing the package substrate of claim 9, wherein the first end face is flush with the first surface and/or the second end face is flush with the second surface.
11. The method of claim 6, further comprising bonding the insulating passivation layer to a carrier via a second surface thereof, and forming the opening and the via.
12. The method for manufacturing a package substrate according to claim 11, further comprising removing the carrier after forming the circuit layer and the conductive pillars.
13. An electronic package, comprising:
a package substrate as recited in claim 1; and
and the electronic element is arranged on the first surface of the insulating protection layer and is electrically connected with the conductive column.
14. The electronic package according to claim 13, wherein the insulating passivation layer is a solder mask.
15. The electronic package according to claim 13, wherein a surface of the circuit layer is flush with the first surface of the insulating protection layer.
16. The electronic package according to claim 13, wherein the conductive pillar has a first end surface and a second end surface opposite to each other, such that the first end surface is exposed to the first surface and the second end surface is exposed to the second surface.
17. The electronic package according to claim 16, wherein the first end face is flush with the first surface and/or the second end face is flush with the second surface.
18. The electronic package according to claim 16, wherein the first end surface of the conductive pillar is electrically connected to the electronic component.
19. The electronic package according to claim 13, further comprising an encapsulation layer formed on the first surface of the insulating protection layer to encapsulate the electronic component.
20. A method of fabricating an electronic package, the method comprising:
providing a package substrate according to claim 1; and
and arranging an electronic element on the first surface of the insulating protection layer, and electrically connecting the electronic element with the conductive column.
21. The method of claim 20, wherein the passivation layer is a solder mask layer.
22. The method of claim 20, wherein a surface of the circuit layer is flush with the first surface of the insulating passivation layer.
23. The method of claim 20, wherein the conductive pillar has a first end surface and a second end surface opposite to each other, such that the first end surface is exposed to the first surface and the second end surface is exposed to the second surface.
24. The method of claim 23, wherein the first end surface is flush with the first surface and/or the second end surface is flush with the second surface.
25. The method of manufacturing an electronic package according to claim 23, wherein the first end surface of the conductive pillar is electrically connected to the electronic component.
26. The method of claim 20, further comprising forming an encapsulation layer on the first surface of the insulating passivation layer to encapsulate the electronic component.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105118131A TWI607676B (en) | 2016-06-08 | 2016-06-08 | Package substrate and its electronic package and the manufacture thereof |
| TW105118131 | 2016-06-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107481991A CN107481991A (en) | 2017-12-15 |
| CN107481991B true CN107481991B (en) | 2020-04-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610504135.0A Active CN107481991B (en) | 2016-06-08 | 2016-06-30 | Package substrate, electronic package and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN107481991B (en) |
| TW (1) | TWI607676B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101399246A (en) * | 2007-09-29 | 2009-04-01 | 全懋精密科技股份有限公司 | Package substrate structure and production method thereof |
| KR20090065117A (en) * | 2007-12-17 | 2009-06-22 | 주식회사 심텍 | Ultra-thin semiconductor package substrate, method for manufacturing semiconductor package substrate, and method for manufacturing semiconductor device using same |
| CN101826469A (en) * | 2009-03-04 | 2010-09-08 | 日月光半导体制造股份有限公司 | Coreless packaging substrate and manufacturing method thereof |
| TW201248814A (en) * | 2011-05-24 | 2012-12-01 | Unimicron Technology Corp | Coreless package substrate and method of making same |
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| US20060065958A1 (en) * | 2004-09-29 | 2006-03-30 | Pei-Haw Tsao | Three dimensional package and packaging method for integrated circuits |
| TWI512922B (en) * | 2012-09-26 | 2015-12-11 | Unimicron Technology Corp | Package substrate and method of forming the same |
| TWI533771B (en) * | 2014-07-17 | 2016-05-11 | 矽品精密工業股份有限公司 | Coreless package substrate and fabrication method thereof |
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| CN101399246A (en) * | 2007-09-29 | 2009-04-01 | 全懋精密科技股份有限公司 | Package substrate structure and production method thereof |
| KR20090065117A (en) * | 2007-12-17 | 2009-06-22 | 주식회사 심텍 | Ultra-thin semiconductor package substrate, method for manufacturing semiconductor package substrate, and method for manufacturing semiconductor device using same |
| CN101826469A (en) * | 2009-03-04 | 2010-09-08 | 日月光半导体制造股份有限公司 | Coreless packaging substrate and manufacturing method thereof |
| TW201248814A (en) * | 2011-05-24 | 2012-12-01 | Unimicron Technology Corp | Coreless package substrate and method of making same |
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| Publication number | Publication date |
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| TWI607676B (en) | 2017-12-01 |
| CN107481991A (en) | 2017-12-15 |
| TW201743665A (en) | 2017-12-16 |
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