[go: up one dir, main page]

TWI533771B - Coreless package substrate and fabrication method thereof - Google Patents

Coreless package substrate and fabrication method thereof Download PDF

Info

Publication number
TWI533771B
TWI533771B TW103124499A TW103124499A TWI533771B TW I533771 B TWI533771 B TW I533771B TW 103124499 A TW103124499 A TW 103124499A TW 103124499 A TW103124499 A TW 103124499A TW I533771 B TWI533771 B TW I533771B
Authority
TW
Taiwan
Prior art keywords
layer
conductive
package substrate
electrical contact
openings
Prior art date
Application number
TW103124499A
Other languages
Chinese (zh)
Other versions
TW201605309A (en
Inventor
白裕呈
林俊賢
邱士超
蕭惟中
孫銘成
沈子傑
陳嘉成
Original Assignee
矽品精密工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 矽品精密工業股份有限公司 filed Critical 矽品精密工業股份有限公司
Priority to TW103124499A priority Critical patent/TWI533771B/en
Priority to CN201410368060.9A priority patent/CN105261606B/en
Priority to US14/583,317 priority patent/US9510463B2/en
Publication of TW201605309A publication Critical patent/TW201605309A/en
Application granted granted Critical
Publication of TWI533771B publication Critical patent/TWI533771B/en
Priority to US15/334,569 priority patent/US9899249B2/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

無核心層封裝基板及其製法 Coreless package substrate and its preparation method

本發明係關於一種無核心層封裝基板及其製法，特別是指一種形成突出構件於線路層之電性接觸墊上之無核心層封裝基板及其製法。 The present invention relates to a coreless layer package substrate and a method for fabricating the same, and more particularly to a coreless layer package substrate for forming a protruding member on an electrical contact pad of a circuit layer and a method for fabricating the same.

隨著電子產業的蓬勃發展，電子產品亦逐漸邁向多功能及高性能之發展趨勢。為滿足半導體封裝件朝向高積集度(integration)及微型化(miniaturization)之封裝需求，在無核心層封裝基板中線路層之複數電性接觸墊之尺寸愈來愈小，使得當以複數銲球將晶片接置於該些電性接觸墊上時，該銲球與該電性接觸墊間之接觸面積較小，因而容易導致該銲球與該電性接觸墊之間產生接合力不足而影響後續產品之信賴性。 With the rapid development of the electronics industry, electronic products are gradually moving towards multi-functional and high-performance development. In order to meet the packaging requirements of semiconductor package parts for high integration and miniaturization, the size of the plurality of electrical contact pads in the circuit layer of the coreless package substrate is getting smaller and smaller, so that when the plurality of solders are used When the ball is placed on the electrical contact pads, the contact area between the solder balls and the electrical contact pads is small, so that the bonding force between the solder balls and the electrical contact pads is easily caused. The reliability of subsequent products.

第1A圖係繪示習知技術之無核心層封裝基板1之剖視示意圖，第1B圖係繪示以銲球17將晶片16接置於習知技術第1A圖之無核心層封裝基板1上之剖視示意圖。 1A is a cross-sectional view showing a coreless package substrate 1 of the prior art, and FIG. 1B is a diagram showing a core 16 package substrate 1 in which the wafer 16 is soldered to the prior art. A schematic cross-sectional view of the above.

如圖所示，無核心層封裝基板1係包括一介電層10、一第一線路層11、一第二線路層12、複數導電盲孔13、 一第一絕緣保護層14以及一第二絕緣保護層15。 As shown, the coreless package substrate 1 includes a dielectric layer 10, a first circuit layer 11, a second circuit layer 12, and a plurality of conductive vias 13, A first insulating protective layer 14 and a second insulating protective layer 15.

該介電層10係具有相對之第一表面10a與第二表面10b，該第一線路層11係具有複數第一電性接觸墊111，該第二線路層12係具有複數第二電性接觸墊121，該些導電盲孔13係電性連接該第一線路層11及該第二線路層12。 The dielectric layer 10 has a first surface 10a and a second surface 10b. The first circuit layer 11 has a plurality of first electrical contact pads 111, and the second circuit layer 12 has a plurality of second electrical contacts. The pads 121 are electrically connected to the first circuit layer 11 and the second circuit layer 12.

該第一絕緣保護層14係形成於該介電層10之第一表面10a上，並具有複數第一開孔141以外露出該些第一電性接觸墊111之接觸面112。該第二絕緣保護層15係形成於該介電層10之第二表面10b上，並具有複數第二開孔151以外露出該些第二電性接觸墊121。 The first insulating protective layer 14 is formed on the first surface 10a of the dielectric layer 10 and has a plurality of first openings 141 to expose the contact faces 112 of the first electrical contact pads 111. The second insulating protective layer 15 is formed on the second surface 10b of the dielectric layer 10, and has a plurality of second openings 151 to expose the second electrical contact pads 121.

惟，上述第1A圖之無核心層封裝基板1之缺點在於：該第一電性接觸墊111之接觸面112係為平面，故如第1B圖所示，當以複數銲球17將晶片16接置於該些第一電性接觸墊111時，該銲球17與該第一電性接觸墊111間之接觸面積較小，因而容易導致該銲球17與該第一電性接觸墊111之間產生接合力不足的問題，進而影響後續產品之信賴性。 However, the coreless package substrate 1 of FIG. 1A has a disadvantage in that the contact surface 112 of the first electrical contact pad 111 is planar, so that the wafer 16 is formed by a plurality of solder balls 17 as shown in FIG. 1B. When the first electrical contact pads 111 are disposed, the contact area between the solder balls 17 and the first electrical contact pads 111 is small, so that the solder balls 17 and the first electrical contact pads 111 are easily caused. There is a problem of insufficient bonding force, which in turn affects the reliability of subsequent products.

因此，如何克服上述習知技術的問題，實已成目前亟欲解決的課題。 Therefore, how to overcome the problems of the above-mentioned prior art has become a problem that is currently being solved.

本發明係提供一種無核心層封裝基板，其包括：介電層，係具有相對之第一表面與第二表面；第一線路層，係嵌埋於該介電層內並外露於該第一表面，且該第一線路層係具有複數第一電性接觸墊；複數突出構件，係分別形成 於該些第一電性接觸墊上，且各該突出構件具有接觸面，以供外部之導電元件包覆於該突出構件之接觸面上；第二線路層，係形成於該介電層之第二表面上；以及複數導電盲孔，係分別形成於該介電層內以電性連接該第一線路層及該第二線路層。 The present invention provides a coreless package substrate, comprising: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and exposed to the first a surface, and the first circuit layer has a plurality of first electrical contact pads; the plurality of protruding members are respectively formed On the first electrical contact pads, and each of the protruding members has a contact surface for the outer conductive member to cover the contact surface of the protruding member; the second circuit layer is formed on the dielectric layer And a plurality of conductive blind vias respectively formed in the dielectric layer to electrically connect the first circuit layer and the second circuit layer.

該突出構件之接觸面可包括該突出構件之上表面與側表面，且該突出構件之寬度可小於或等於該第一電性接觸墊之寬度，該突出構件與該第一電性接觸墊可為相同材質所形成者或一體成形者，該突出構件可為導電柱或導電跡線之銲墊，該導電元件可為銲球。 The contact surface of the protruding member may include an upper surface and a side surface of the protruding member, and the protruding member may have a width smaller than or equal to a width of the first electrical contact pad, and the protruding member and the first electrical contact pad may be For the same material formed or integrally formed, the protruding member may be a conductive post or a conductive trace pad, and the conductive element may be a solder ball.

該第二線路層可具有複數第二電性接觸墊，該導電盲孔可形成於該第一線路層與該第二電性接觸墊之間。 The second circuit layer can have a plurality of second electrical contact pads, and the conductive blind vias can be formed between the first circuit layer and the second electrical contact pads.

該無核心層封裝基板可包括導電層，係形成於該突出構件之接觸面上或再形成於部分該第一電性接觸墊上；或者，該導電層係形成於該突出構件與該第一電性接觸墊之間。 The coreless package substrate may include a conductive layer formed on a contact surface of the protruding member or formed on a portion of the first electrical contact pad; or the conductive layer is formed on the protruding member and the first Between the contact pads.

該無核心層封裝基板可包括具有複數開孔之絕緣保護層，係形成於該介電層之第二表面與該第二線路層上，並藉由該些開孔分別外露出該第二線路層之第二電性接觸墊。 The coreless package substrate may include an insulating protective layer having a plurality of openings formed on the second surface of the dielectric layer and the second circuit layer, and the second lines are respectively exposed through the openings The second electrical contact pad of the layer.

本發明復提供一種無核心層封裝基板之製法，其包括：形成具有複數第一開孔之第一阻層於承載板上；形成複數突出構件於該些第一開孔內；形成具有複數第一電性 接觸墊之第一線路層於該第一阻層上，其中，該些第一電性接觸墊係對應形成於該些突出構件上；形成具有相對之第一表面與第二表面之介電層於該第一線路層上，以將該第一線路層嵌埋於該介電層內，其中，該介電層之第一表面係接合至該第一阻層，且該第一線路層係外露於該介電層之第一表面；形成複數導電盲孔於該介電層內以電性連接該第一線路層，並形成第二線路層於該介電層之第二表面上以電性連接該些導電盲孔；以及移除該第一阻層以外露出該些突出構件之接觸面。 The invention provides a method for manufacturing a coreless package substrate, comprising: forming a first resist layer having a plurality of first openings on a carrier plate; forming a plurality of protruding members in the first openings; forming a plurality of Electric a first circuit layer of the contact pad is disposed on the first resistive layer, wherein the first electrical contact pads are formed on the protruding members correspondingly; forming a dielectric layer having opposite first and second surfaces The first circuit layer is embedded in the dielectric layer on the first circuit layer, wherein a first surface of the dielectric layer is bonded to the first resistive layer, and the first circuit layer is Exposed on the first surface of the dielectric layer; forming a plurality of conductive blind vias in the dielectric layer to electrically connect the first wiring layer, and forming a second wiring layer on the second surface of the dielectric layer to be electrically And connecting the conductive blind holes; and removing the contact faces of the protruding members outside the first resist layer.

該介電層可具有複數第二開孔，該些導電盲孔係藉由填充導電材料於該些第二開孔內所形成。 The dielectric layer can have a plurality of second openings formed by filling a conductive material in the second openings.

該無核心層封裝基板之製法可包括：形成剝離層於該承載板之頂面與底面其中一者或二者上，該第一阻層係形成於該剝離層上，且該些第一開孔係外露出部分該剝離層。 The method for manufacturing the coreless package substrate may include: forming a peeling layer on one or both of a top surface and a bottom surface of the carrier sheet, the first resist layer being formed on the peeling layer, and the first opening A portion of the peeling layer is exposed outside the hole system.

該無核心層封裝基板之製法可包括：形成導電層於該第一阻層、該些第一開孔之壁面及該些第一開孔之剝離層上，該第一線路層係形成於該導電層上，該些突出構件係分別形成於該些第一開孔內之導電層上。 The method for manufacturing the coreless package substrate may include: forming a conductive layer on the first resist layer, a wall surface of the first openings, and a peeling layer of the first openings, wherein the first circuit layer is formed on the first circuit layer On the conductive layer, the protruding members are respectively formed on the conductive layers in the first openings.

該無核心層封裝基板之製法可包括：形成第二阻層於該第一線路層及該些第一電性接觸墊上；依據該第二阻層移除部分該導電層以外露出部分該第一阻層；以及移除該第二阻層以外露出該第一線路層及該些第一電性接觸墊。 The method for fabricating the coreless package substrate may include: forming a second resist layer on the first circuit layer and the first electrical contact pads; and removing the portion of the conductive layer from the exposed portion according to the second resist layer removing portion a resist layer; and removing the second circuit layer to expose the first circuit layer and the first electrical contact pads.

該無核心層封裝基板之製法可包括：形成具有複數第三開孔之絕緣保護層於該第二線路層及其複數第二電性接 觸墊上，並藉由該些第三開孔分別外露出該些第二電性接觸墊；以及去除該剝離層以移除該承載板。 The method for manufacturing the coreless package substrate may include: forming an insulating protection layer having a plurality of third openings in the second circuit layer and a plurality of second electrical connections thereof And contacting the second electrical contact pads by the third openings; and removing the peeling layer to remove the carrier.

該無核心層封裝基板之製法可包括：依序形成剝離層與第一導電層於該承載板之頂面與底面其中一者或二者上，該第一阻層係形成於該第一導電層上，且該些第一開孔係外露出部分該第一導電層。 The core layer package substrate may be formed by: sequentially forming a peeling layer and a first conductive layer on one or both of a top surface and a bottom surface of the carrier board, wherein the first resist layer is formed on the first conductive layer And the first openings expose a portion of the first conductive layer.

該無核心層封裝基板之製法可包括：形成第二導電層於該第一阻層及該些突出構件上，該第一線路層與該些第一電性接觸墊係形成於該第二導電層上。 The method of manufacturing the coreless package substrate may include: forming a second conductive layer on the first resistive layer and the protruding members, wherein the first circuit layer and the first electrical contact pads are formed on the second conductive layer On the floor.

該無核心層封裝基板之製法可包括：去除該剝離層以移除該承載板；移除該第一導電層與該第一阻層以外露出該些突出構件之接觸面；形成第二阻層於該些突出構件上；依據該第二阻層移除部分該第二導電層以外露出部分該介電層；以及移除該第二阻層以外露出該些突出構件之接觸面。 The method for manufacturing the coreless package substrate may include: removing the peeling layer to remove the carrier plate; removing the first conductive layer and the first resistive layer to expose the contact faces of the protruding members; forming a second resistive layer And exposing a portion of the dielectric layer to the second conductive layer according to the second resist layer removing portion; and removing the contact surface of the protruding members except the second resist layer.

由上可知，本發明之無核心層封裝基板及其製法中，主要係在第一線路層之複數第一電性接觸墊上形成複數具有立體之接觸面(如上表面及側表面)之突出構件，以供外部之複數導電元件(如銲球)分別包覆於該些突出構件之接觸面上，並可藉由該些導電元件將半導體元件(如晶片)接置於該些突出構件及第一電性接觸墊上。藉此，該突出構件與該導電元件之間可形成較大的接觸面積，以強化該第一電性接觸墊與該導電元件之接合力，進而提高後續產品之信賴性。 It can be seen from the above that in the coreless package substrate of the present invention and the manufacturing method thereof, a plurality of protruding members having a three-dimensional contact surface (such as a surface and a side surface) are formed on a plurality of first electrical contact pads of the first circuit layer. The plurality of conductive elements (such as solder balls) are externally coated on the contact faces of the protruding members, and the semiconductor elements (such as wafers) are attached to the protruding members and the first by the conductive elements. Electrical contact pads. Thereby, a large contact area can be formed between the protruding member and the conductive element to strengthen the bonding force between the first electrical contact pad and the conductive element, thereby improving the reliability of the subsequent product.

1、2、2'‧‧‧無核心層封裝基板 1, 2, 2' ‧ ‧ no core layer package substrate

10、27‧‧‧介電層 10, 27‧‧‧ dielectric layer

10a、27a‧‧‧第一表面 10a, 27a‧‧‧ first surface

10b、27b‧‧‧第二表面 10b, 27b‧‧‧ second surface

11、25‧‧‧第一線路層 11, 25‧‧‧ first line layer

111、251‧‧‧第一電性接觸墊 111, 251‧‧‧ first electrical contact pads

112、241‧‧‧接觸面 112, 241‧‧ ‧ contact surface

12、29‧‧‧第二線路層 12, 29‧‧‧ second circuit layer

121、281‧‧‧第二電性接觸墊 121, 281‧‧‧Second electrical contact pads

13、28‧‧‧導電盲孔 13, 28‧‧‧ Conductive blind holes

14‧‧‧第一絕緣保護層 14‧‧‧First insulation protection layer

141、221‧‧‧第一開孔 141, 221‧‧‧ first opening

15‧‧‧第二絕緣保護層 15‧‧‧Second insulation protection layer

151、271‧‧‧第二開孔 151, 271‧‧‧ second opening

16‧‧‧晶片 16‧‧‧ wafer

17‧‧‧銲球 17‧‧‧ solder balls

20‧‧‧承載板 20‧‧‧Loading board

20a‧‧‧頂面 20a‧‧‧ top

20b‧‧‧底面 20b‧‧‧ bottom

21‧‧‧剝離層 21‧‧‧ peeling layer

211、23‧‧‧導電層 211, 23‧‧‧ conductive layer

22‧‧‧第一阻層 22‧‧‧First resistance layer

24‧‧‧突出構件 24‧‧‧ protruding members

26‧‧‧第二阻層 26‧‧‧second barrier layer

30‧‧‧絕緣保護層 30‧‧‧Insulating protective layer

301‧‧‧第三開孔 301‧‧‧ third opening

31‧‧‧半導體元件 31‧‧‧Semiconductor components

32‧‧‧導電元件 32‧‧‧Conductive components

第1A圖係繪示習知技術之無核心層封裝基板之剖視示意圖；第1B圖係繪示以銲球將晶片接置於習知技術第1A圖之無核心層封裝基板上之剖視示意圖；第2A圖至第2L圖係繪示本發明之無核心層封裝基板及其製法之一實施例之剖視示意圖；第2M圖係繪示以導電元件將半導體元件接置於本發明第2L圖之無核心層封裝基板上之一實施例之剖視示意圖；第3A圖至第3L圖係繪示本發明之無核心層封裝基板及其製法之另一實施例之剖視示意圖；以及第3M圖係繪示以導電元件將半導體元件接置於本發明第3L圖之無核心層封裝基板上之另一實施例之剖視示意圖。 1A is a cross-sectional view showing a coreless package substrate of a prior art; FIG. 1B is a cross-sectional view showing a solder ball for attaching a wafer to a coreless package substrate of the prior art FIG. 2A to 2L are schematic cross-sectional views showing an embodiment of a coreless package substrate of the present invention and a method for fabricating the same; FIG. 2M is a view showing a semiconductor device connected to a conductive element by a conductive member; 2A to 3L are schematic cross-sectional views showing another embodiment of the coreless package substrate of the present invention and a method for fabricating the same; and FIGS. 3A to 3L are schematic cross-sectional views showing another embodiment of the coreless package substrate of the present invention; 3M is a cross-sectional view showing another embodiment in which a semiconductor element is placed on a coreless package substrate of the third embodiment of the present invention with a conductive member.

以下藉由特定的具體實施例說明本發明之實施方式，熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。 The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

須知，本說明書所附圖式所繪示之結構、比例、大小等，均僅用以配合說明書所揭示之內容，以供熟悉此技藝之人士之瞭解與閱讀，並非用以限定本發明可實施之限定條件，故不具技術上之實質意義，任何結構之修飾、比例關係之改變或大小之調整，在不影響本發明所能產生之功 效及所能達成之目的下，均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。 It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The qualifications are not technically meaningful, and any modification of the structure, change of the proportional relationship or adjustment of the size does not affect the work that can be produced by the present invention. Both the effects and the achievable objectives should still fall within the scope of the technical contents disclosed in the present invention.

同時，本說明書中所引用之如「上」、「一」、「第一」、「第二」、「表面」或「接觸面」等用語，亦僅為便於敘述之明瞭，而非用以限定本發明可實施之範圍，其相對關係之改變或調整，在無實質變更技術內容下，當亦視為本發明可實施之範疇。 At the same time, terms such as "upper", "one", "first", "second", "surface" or "contact surface" as used in this specification are for convenience only and are not intended to be used The scope of the invention can be implemented, and the relative changes or adjustments of the invention are considered to be within the scope of the invention.

第2A圖至第2L圖係繪示本發明之無核心層封裝基板2及其製法之一實施例之剖視示意圖，第2M圖係繪示以導電元件32將半導體元件31接置於本發明第2L圖之無核心層封裝基板2上之一實施例之剖視示意圖。 2A to 2L are schematic cross-sectional views showing an embodiment of the coreless package substrate 2 of the present invention and a method for fabricating the same, and FIG. 2M is a view showing the semiconductor element 31 connected to the present invention by a conductive member 32. A schematic cross-sectional view of an embodiment of the coreless package substrate 2 of the second embodiment.

如第2A圖所示，先提供一具有相對之頂面20a與底面20b之承載板20，並形成一或二剝離層21於該承載板20之頂面20a與底面20b其中一者或二者上。該承載板20可為不鏽鋼板。 As shown in FIG. 2A, a carrier 20 having an opposite top surface 20a and a bottom surface 20b is provided, and one or two peeling layers 21 are formed on one or both of the top surface 20a and the bottom surface 20b of the carrier board 20. on. The carrier plate 20 can be a stainless steel plate.

如第2B圖所示，依據該剝離層21是形成於該承載板20之頂面20a與底面20b其中一者或二者上，以形成一或二第一阻層22於該剝離層21上，且該第一阻層22係具有複數第一開孔221以外露出部分該剝離層21。 As shown in FIG. 2B, the peeling layer 21 is formed on one or both of the top surface 20a and the bottom surface 20b of the carrier 20 to form one or two first resist layers 22 on the peeling layer 21. And the first resist layer 22 has a plurality of first openings 221 and a portion of the peeling layer 21 exposed.

如第2C圖所示，依據該第一阻層22是形成於該一或二剝離層21上，以藉由濺鍍或其他方式形成一或二導電層23於該第一阻層22上、該些第一開孔221之壁面及該些第一開孔221之剝離層21上。該導電層23可為晶種層(seed layer)。 As shown in FIG. 2C, the first resist layer 22 is formed on the one or two peeling layers 21 to form one or two conductive layers 23 on the first resist layer 22 by sputtering or other methods. The wall surfaces of the first openings 221 and the peeling layers 21 of the first openings 221 are formed. The conductive layer 23 may be a seed layer.

如第2D圖所示，形成複數突出構件24於該些第一開孔221內之導電層23上，並形成具有複數第一電性接觸墊251之第一線路層25於該導電層23上，且形成該些第一電性接觸墊251於該些突出構件24及部分該導電層23上。該突出構件24可為導電柱(如銅柱)或導電跡線之銲墊等，且該突出構件24之寬度可小於或等於該第一電性接觸墊251之寬度，該突出構件24與該第一電性接觸墊251可為相同材質所形成者或一體成形者。 As shown in FIG. 2D, a plurality of protruding members 24 are formed on the conductive layer 23 in the first openings 221, and a first wiring layer 25 having a plurality of first electrical contact pads 251 is formed on the conductive layer 23. And forming the first electrical contact pads 251 on the protruding members 24 and a portion of the conductive layer 23. The protruding member 24 can be a conductive pillar (such as a copper pillar) or a conductive trace pad or the like, and the protruding member 24 can have a width smaller than or equal to a width of the first electrical contact pad 251, and the protruding member 24 and the The first electrical contact pad 251 can be formed of the same material or integrally formed.

如第2E圖所示，形成第二阻層26於該第一線路層25及該些第一電性接觸墊251上。 As shown in FIG. 2E, a second resist layer 26 is formed on the first circuit layer 25 and the first electrical contact pads 251.

如第2F圖所示，依據該第二阻層26移除部分該導電層23以外露出部分該第一阻層22，再移除該第二阻層26以外露出該第一線路層25及該些第一電性接觸墊251。 As shown in FIG. 2F, a portion of the first resist layer 22 is exposed outside the conductive layer 23 according to the second resist layer 26, and the first trace layer 26 is removed to expose the first trace layer 25 and the second trace layer 26 Some first electrical contact pads 251.

如第2G圖所示，形成具有相對之第一表面27a與第二表面27b之介電層27於該第一線路層25上以嵌埋該第一線路層25於該介電層27內。該介電層27之第一表面27a係接合至該第一阻層22，該第一線路層25或該導電層23係外露於該介電層27之第一表面27a。 As shown in FIG. 2G, a dielectric layer 27 having opposing first and second surfaces 27a, 27b is formed on the first wiring layer 25 to embed the first wiring layer 25 in the dielectric layer 27. The first surface 27a of the dielectric layer 27 is bonded to the first resistive layer 22, and the first wiring layer 25 or the conductive layer 23 is exposed on the first surface 27a of the dielectric layer 27.

如第2H圖所示，藉由雷射鑽孔或其他方式，自該第二表面27b形成複數第二開孔271於該介電層27中以外露出部分該第一線路層25。 As shown in FIG. 2H, a plurality of second openings 271 are formed in the dielectric layer 27 from the second surface 27b by laser drilling or other means to expose a portion of the first wiring layer 25.

如第2I圖所示，填充導電材料於該介電層27之第二開孔271內以形成複數導電盲孔28而電性連接該第一線路層25，並形成第二線路層29於該介電層27之第二表面27b 上以電性連接該些導電盲孔28。該導電盲孔28與該第二線路層29兩者可為同時形成、相同材質或一體成形；但在其他實施例中，兩者亦可為先後形成、不同材質或分別成形。 As shown in FIG. 2I, a conductive material is filled in the second opening 271 of the dielectric layer 27 to form a plurality of conductive blind vias 28 to electrically connect the first wiring layer 25, and a second wiring layer 29 is formed thereon. Second surface 27b of dielectric layer 27 The conductive blind holes 28 are electrically connected to each other. The conductive blind vias 28 and the second interconnect layer 29 may be formed simultaneously, of the same material or integrally formed; however, in other embodiments, the two may be formed sequentially, different materials, or separately formed.

如第2J圖所示，形成具有複數第三開孔301之絕緣保護層30於該第二線路層29及其複數第二電性接觸墊281上，並藉由該些第三開孔301分別外露出該些第二電性接觸墊281。 As shown in FIG. 2J, an insulating protective layer 30 having a plurality of third openings 301 is formed on the second wiring layer 29 and the plurality of second electrical contact pads 281, and the third openings 301 are respectively formed by the third openings 301. The second electrical contact pads 281 are exposed.

如第2K圖所示，去除該剝離層21以移除該承載板20而外露出該第一阻層22。 As shown in FIG. 2K, the peeling layer 21 is removed to remove the carrier sheet 20 to expose the first resist layer 22.

如第2L圖所示，移除該第一阻層22以外露出該些突出構件24之接觸面241或該導電層23，藉此形成一或二無核心層封裝基板2。該突出構件24之接觸面241可包括該突出構件24之上表面與側表面，且該突出構件24之上表面係高於該介電層27之第一表面27a，該第一線路層25上之導電層23係齊平於該介電層27之第一表面27a。 As shown in FIG. 2L, the contact surface 241 or the conductive layer 23 of the protruding members 24 is exposed outside the first resist layer 22, thereby forming one or two coreless package substrates 2. The contact surface 241 of the protruding member 24 may include an upper surface and a side surface of the protruding member 24, and the upper surface of the protruding member 24 is higher than the first surface 27a of the dielectric layer 27 on the first circuit layer 25. The conductive layer 23 is flush with the first surface 27a of the dielectric layer 27.

此外，如第2M圖所示，可藉由外部之複數導電元件(如銲球)32包覆該些突出構件24之接觸面(如上表面及側表面)241或該些接觸面241上之導電層23，以藉由該些導電元件32將半導體元件(如晶片)31接置於該些突出構件24及其下之第一電性接觸墊251上。 In addition, as shown in FIG. 2M, the contact faces (such as the surface and the side surface) 241 of the protruding members 24 or the conductive surfaces on the contact faces 241 may be covered by an external plurality of conductive members (such as solder balls) 32. The layer 23 is used to connect a semiconductor element (such as a wafer) 31 to the protruding members 24 and the first electrical contact pads 251 thereunder by the conductive elements 32.

第3A圖至第3L圖係繪示本發明之無核心層封裝基板2'及其製法之另一實施例之剖視示意圖，第3M圖係繪示以導電元件32將半導體元件31接置於本發明第3L圖之無核 心層封裝基板2'上之另一實施例之剖視示意圖。 3A to 3L are schematic cross-sectional views showing another embodiment of the coreless package substrate 2' of the present invention and a method for fabricating the same, and FIG. 3M is a view showing the semiconductor element 31 being placed by the conductive member 32. The coreless of the 3L figure of the present invention A schematic cross-sectional view of another embodiment of the core layer package substrate 2'.

如第3A圖所示，先提供一具有相對之頂面20a與底面20b之承載板20，並形成一或二剝離層21於該承載板20之頂面20a與底面20b其中一者或二者上，且藉由濺鍍或其他方式形成一或二導電層211於該剝離層21上。該承載板20可為不鏽鋼板，該導電層211可為晶種層。 As shown in FIG. 3A, a carrier board 20 having opposing top and bottom surfaces 20a and 20b is provided, and one or two peeling layers 21 are formed on one or both of the top surface 20a and the bottom surface 20b of the carrier board 20. And, one or two conductive layers 211 are formed on the peeling layer 21 by sputtering or other means. The carrier plate 20 can be a stainless steel plate, and the conductive layer 211 can be a seed layer.

如第3B圖所示，依據該剝離層21與該導電層211是形成於該承載板20之頂面20a與底面20b其中一者或二者上，以形成一或二第一阻層22於該導電層211上，且該第一阻層22係具有複數第一開孔221以外露出部分該導電層211。 As shown in FIG. 3B, the peeling layer 21 and the conductive layer 211 are formed on one or both of the top surface 20a and the bottom surface 20b of the carrier 20 to form one or two first resist layers 22. The conductive layer 211 is disposed on the conductive layer 211, and the conductive layer 211 is exposed outside the plurality of first openings 221.

如第3C圖所示，形成複數突出構件24於該些第一開孔221內所外露之導電層211上。該突出構件24可為導電柱(如銅柱)或導電跡線之銲墊等。 As shown in FIG. 3C, a plurality of protruding members 24 are formed on the conductive layer 211 exposed in the first openings 221. The protruding member 24 can be a conductive post (such as a copper post) or a conductive trace pad or the like.

如第3D圖所示，依據該第一阻層22是形成於該一或二導電層211上，以藉由濺鍍或其他方式形成一或二導電層23於該第一阻層22及該些突出構件24上。該導電層23可為晶種層。 As shown in FIG. 3D, the first resist layer 22 is formed on the one or two conductive layers 211 to form one or two conductive layers 23 on the first resist layer 22 by sputtering or other means. These are on the protruding member 24. The conductive layer 23 can be a seed layer.

如第3E圖所示，形成具有複數第一電性接觸墊251之第一線路層25於該導電層23上。該第一電性接觸墊251之寬度可小於、等於或大於該突出構件24之寬度。 As shown in FIG. 3E, a first wiring layer 25 having a plurality of first electrical contact pads 251 is formed on the conductive layer 23. The width of the first electrical contact pad 251 can be less than, equal to, or greater than the width of the protruding member 24.

在其他實施例中，亦可不必形成有該導電層23，從而直接形成該第一線路層25於該第一阻層22上，並形成該些第一電性接觸墊251於該些突出構件24上。 In other embodiments, the conductive layer 23 is not necessarily formed, so that the first circuit layer 25 is directly formed on the first resist layer 22, and the first electrical contact pads 251 are formed on the protruding members. 24 on.

如第3F圖所示，形成具有相對之第一表面27a與第二表面27b之介電層27於該導電層23與該第一線路層25上，以將該第一線路層25嵌埋於該介電層27內且外露於該第一表面27a，且該介電層27之第一表面27a係面向該第一阻層22。接著，可藉由雷射鑽孔或其他方式，自該第二表面27b形成複數第二開孔271於該介電層27中以外露出部分該第一線路層25。 As shown in FIG. 3F, a dielectric layer 27 having a first surface 27a and a second surface 27b opposite to each other is formed on the conductive layer 23 and the first wiring layer 25 to embed the first wiring layer 25 therein. The dielectric layer 27 is exposed to the first surface 27a, and the first surface 27a of the dielectric layer 27 faces the first resist layer 22. Then, a plurality of second openings 271 are formed from the second surface 27b to expose a portion of the first wiring layer 25 outside the dielectric layer 27 by laser drilling or other means.

在其他實施例中，亦可不必形成有該導電層23，從而直接形成該介電層27於該第一阻層22上，並形成該些第一電性接觸墊251於該些突出構件24上。 In other embodiments, the conductive layer 23 is not necessarily formed, so that the dielectric layer 27 is directly formed on the first resist layer 22, and the first electrical contact pads 251 are formed on the protruding members 24. on.

如第3G圖所示，填充導電材料於該介電層27之第二開孔271內以形成複數導電盲孔28而電性連接該第一線路層25，並形成第二線路層29於該介電層27之第二表面27b上以電性連接該些導電盲孔28。該導電盲孔28與該第二線路層29兩者可為同時形成、相同材質或一體成形；但在其他實施例中，兩者亦可為先後形成、不同材質或分別成形。 As shown in FIG. 3G, a conductive material is filled in the second opening 271 of the dielectric layer 27 to form a plurality of conductive blind vias 28 to electrically connect the first wiring layer 25, and a second wiring layer 29 is formed thereon. The conductive vias 28 are electrically connected to the second surface 27b of the dielectric layer 27. The conductive blind vias 28 and the second interconnect layer 29 may be formed simultaneously, of the same material or integrally formed; however, in other embodiments, the two may be formed sequentially, different materials, or separately formed.

如第3H圖所示，去除該剝離層21以移除該承載板20而外露出該導電層211與該第一阻層22。 As shown in FIG. 3H, the peeling layer 21 is removed to remove the carrier sheet 20 to expose the conductive layer 211 and the first resist layer 22.

如第3I圖所示，移除該導電層211與該第一阻層22以外露出該些突出構件24之接觸面241及部分該導電層23。 As shown in FIG. 3I, the contact surface 241 and a portion of the conductive layer 23 of the protruding members 24 are exposed outside the conductive layer 211 and the first resist layer 22.

如第3J圖所示，形成第二阻層26於該些突出構件24之上表面。 As shown in FIG. 3J, a second resist layer 26 is formed on the upper surface of the protruding members 24.

如第3K圖所示，依據該第二阻層26移除部分該導電層23以外露出部分該介電層27之第一表面27a。 As shown in FIG. 3K, a portion of the conductive layer 23 is removed from the second resist layer 26 to expose a portion of the first surface 27a of the dielectric layer 27.

如第3L圖所示，移除該第二阻層26以外露出該些突出構件24之接觸面241，藉此形成一或二無核心層封裝基板2。該突出構件24之接觸面241可包括該突出構件24之上表面與側表面，且該突出構件24之上表面係高於該介電層27之第一表面27a，該第一線路層25係齊平於該介電層27之第一表面27a。 As shown in FIG. 3L, the contact surface 241 of the protruding members 24 is exposed outside the second resist layer 26, thereby forming one or two coreless package substrates 2. The contact surface 241 of the protruding member 24 may include an upper surface and a side surface of the protruding member 24, and the upper surface of the protruding member 24 is higher than the first surface 27a of the dielectric layer 27, and the first circuit layer 25 is It is flush with the first surface 27a of the dielectric layer 27.

此外，如第3M圖所示，可藉由外部之複數導電元件(如銲球)32包覆該些突出構件24之接觸面(如上表面及側表面)241與該些突出構件24下之導電層23，以藉由該些導電元件32將半導體元件(如晶片)31接置於該些突出構件24上。 In addition, as shown in FIG. 3M, the contact faces (such as the upper surface and the side surface) 241 of the protruding members 24 and the conductive under the protruding members 24 may be covered by an external plurality of conductive members (such as solder balls) 32. Layer 23 is used to attach semiconductor components (e.g., wafers) 31 to the protruding members 24 by the conductive members 32.

本發明另提供一種無核心層封裝基板2，如第2L圖所示，請一併參考第2M圖。無核心層封裝基板2主要包括一介電層27、一第一線路層25、複數突出構件24、一第二線路層29以及複數導電盲孔28。 The present invention further provides a coreless package substrate 2, as shown in FIG. 2L, please refer to FIG. 2M together. The coreless package substrate 2 mainly includes a dielectric layer 27, a first wiring layer 25, a plurality of protruding members 24, a second wiring layer 29, and a plurality of conductive blind vias 28.

該介電層27係具有相對之第一表面27a與第二表面27b。該第一線路層25係嵌埋於該介電層27內並外露於該第一表面27a，且該第一線路層25係具有複數第一電性接觸墊251。 The dielectric layer 27 has opposing first and second surfaces 27a, 27b. The first circuit layer 25 is embedded in the dielectric layer 27 and exposed on the first surface 27a, and the first circuit layer 25 has a plurality of first electrical contact pads 251.

該些突出構件24係分別形成於該些第一電性接觸墊251上，且各該突出構件24具有接觸面241，以供外部之導電元件32包覆於該突出構件24之接觸面241上。該突 出構件24之接觸面241可包括該突出構件24之上表面與側表面，且該突出構件24之寬度可小於或等於該第一電性接觸墊251之寬度，該突出構件24與該第一電性接觸墊251可為相同材質所形成者或一體成形者，該突出構件24可為導電柱(如銅柱)或導電跡線之銲墊等，該導電元件32可為銲球等。 The protruding members 24 are respectively formed on the first electrical contact pads 251, and each of the protruding members 24 has a contact surface 241 for the outer conductive member 32 to be coated on the contact surface 241 of the protruding member 24. . The sudden The contact surface 241 of the output member 24 may include an upper surface and a side surface of the protruding member 24, and the width of the protruding member 24 may be less than or equal to the width of the first electrical contact pad 251, the protruding member 24 and the first The electrical contact pads 251 may be formed of the same material or integrally formed. The protruding members 24 may be conductive pillars (such as copper pillars) or conductive trace pads, etc., and the conductive component 32 may be solder balls or the like.

該第二線路層29係形成於該介電層27之第二表面27b上，並具有複數第二電性接觸墊281，該導電盲孔28可形成於該介電層27內以電性連接該第一線路層25及該第二線路層29之第二電性接觸墊281。 The second circuit layer 29 is formed on the second surface 27b of the dielectric layer 27 and has a plurality of second electrical contact pads 281. The conductive vias 28 can be formed in the dielectric layer 27 to be electrically connected. The first circuit layer 25 and the second electrical contact pad 281 of the second circuit layer 29.

該無核心層封裝基板2可包括導電層23，係形成於該突出構件24之接觸面241上或再形成於部分該第一電性接觸墊251上。該導電元件32係包覆該接觸面241之導電層23或再包覆該第一電性接觸墊251之導電層23。 The coreless package substrate 2 may include a conductive layer 23 formed on the contact surface 241 of the protruding member 24 or formed on a portion of the first electrical contact pad 251. The conductive element 32 covers the conductive layer 23 of the contact surface 241 or the conductive layer 23 of the first electrical contact pad 251.

該無核心層封裝基板2可包括具有複數開孔(如第三開孔301)之絕緣保護層30，該絕緣保護層30係形成於該介電層27之第二表面27b與該第二線路層29上，並藉由該些開孔(如第三開孔301)分別外露出該第二線路層29之第二電性接觸墊281。 The coreless package substrate 2 may include an insulating protective layer 30 having a plurality of openings (eg, third openings 301) formed on the second surface 27b of the dielectric layer 27 and the second line. On the layer 29, the second electrical contact pads 281 of the second circuit layer 29 are respectively exposed by the openings (such as the third openings 301).

本發明又提供一種無核心層封裝基板2'，如第3L圖所示，請一併參考第3M圖。第3L圖之無核心層封裝基板2'與上述第2L圖之無核心層封裝基板2大致相同，其主要差異如下：在第3L圖中，該導電層23係形成於該突出構件24 與該第一電性接觸墊251之間。因此，如第3M圖所示，該導電元件32可包覆該突出構件24之接觸面241或再包覆該突出構件24下之導電層23。 The present invention further provides a coreless package substrate 2'. As shown in FIG. 3L, please refer to FIG. 3M together. The coreless package substrate 2' of the third embodiment is substantially the same as the coreless package substrate 2 of the second embodiment, and the main difference is as follows: In the third embodiment, the conductive layer 23 is formed on the protruding member 24. Between the first electrical contact pad 251 and the first. Therefore, as shown in FIG. 3M, the conductive member 32 may cover the contact surface 241 of the protruding member 24 or re-coat the conductive layer 23 under the protruding member 24.

由上可知，本發明之無核心層封裝基板及其製法中，主要係在第一線路層之複數第一電性接觸墊上形成複數具有立體之接觸面(如上表面及側表面)之突出構件，以供外部之複數導電元件(如銲球)分別包覆於該些突出構件之接觸面上，並可藉由該些導電元件將半導體元件(如晶片)接置於該些突出構件及第一電性接觸墊上。藉此，該突出構件與該導電元件之間可形成較大的接觸面積，以強化該第一電性接觸墊與該導電元件之接合力，進而提高後續產品之信賴性。 It can be seen from the above that in the coreless package substrate of the present invention and the manufacturing method thereof, a plurality of protruding members having a three-dimensional contact surface (such as a surface and a side surface) are formed on a plurality of first electrical contact pads of the first circuit layer. The plurality of conductive elements (such as solder balls) are externally coated on the contact faces of the protruding members, and the semiconductor elements (such as wafers) are attached to the protruding members and the first by the conductive elements. Electrical contact pads. Thereby, a large contact area can be formed between the protruding member and the conductive element to strengthen the bonding force between the first electrical contact pad and the conductive element, thereby improving the reliability of the subsequent product.

上述實施例係用以例示性說明本發明之原理及其功效，而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下，對上述實施例進行修改。因此本發明之權利保護範圍，應如後述之申請專利範圍所列。 The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

2‧‧‧無核心層封裝基板 2‧‧‧No core layer package substrate

23‧‧‧導電層 23‧‧‧ Conductive layer

24‧‧‧突出構件 24‧‧‧ protruding members

241‧‧‧接觸面 241‧‧‧Contact surface

25‧‧‧第一線路層 25‧‧‧First line layer

251‧‧‧第一電性接觸墊 251‧‧‧First electrical contact pad

27‧‧‧介電層 27‧‧‧Dielectric layer

27a‧‧‧第一表面 27a‧‧‧ first surface

27b‧‧‧第二表面 27b‧‧‧second surface

28‧‧‧導電盲孔 28‧‧‧ Conductive blind holes

281‧‧‧第二電性接觸墊 281‧‧‧Second electrical contact pads

29‧‧‧第二線路層 29‧‧‧Second circuit layer

30‧‧‧絕緣保護層 30‧‧‧Insulating protective layer

301‧‧‧第三開孔 301‧‧‧ third opening

31‧‧‧半導體元件 31‧‧‧Semiconductor components

32‧‧‧導電元件 32‧‧‧Conductive components

Claims (19)

一種無核心層封裝基板，其包括：介電層，係具有相對之第一表面與第二表面；第一線路層，係嵌埋於該介電層內並具有複數外露於該介電層之第一表面之第一電性接觸墊；複數突出構件，係分別形成於該些外露於該介電層之第一表面之第一電性接觸墊上，且各該突出構件具有接觸面，以供外部之導電元件包覆於該突出構件之接觸面上；第二線路層，係形成於該介電層之第二表面上；以及複數導電盲孔，係分別形成於該介電層內以電性連接該第一線路層及該第二線路層。 A coreless package substrate comprising: a dielectric layer having opposite first and second surfaces; a first circuit layer embedded in the dielectric layer and having a plurality of exposed dielectric layers a first electrical contact pad of the first surface; a plurality of protruding members are respectively formed on the first electrical contact pads exposed on the first surface of the dielectric layer, and each of the protruding members has a contact surface for An external conductive element is coated on the contact surface of the protruding member; a second circuit layer is formed on the second surface of the dielectric layer; and a plurality of conductive blind holes are respectively formed in the dielectric layer to be electrically The first circuit layer and the second circuit layer are connected. 如申請專利範圍第1項所述之無核心層封裝基板，其中，該突出構件之接觸面係包括該突出構件之上表面與側表面。 The coreless package substrate of claim 1, wherein the contact surface of the protruding member comprises an upper surface and a side surface of the protruding member. 如申請專利範圍第1項所述之無核心層封裝基板，其中，該突出構件之寬度係小於或等於該第一電性接觸墊之寬度。 The coreless package substrate of claim 1, wherein the protruding member has a width less than or equal to a width of the first electrical contact pad. 如申請專利範圍第1項所述之無核心層封裝基板，其中，該突出構件與該第一電性接觸墊係為相同材質所形成者或一體成形者。 The coreless package substrate according to claim 1, wherein the protruding member and the first electrical contact pad are formed of the same material or integrally formed. 如申請專利範圍第1項所述之無核心層封裝基板，其中，該突出構件係為導電柱或導電跡線之銲墊，該導 電元件係為銲球。 The non-core layer package substrate according to claim 1, wherein the protruding member is a conductive pillar or a conductive trace pad, the guide The electrical component is a solder ball. 如申請專利範圍第1項所述之無核心層封裝基板，其中，該第二線路層係具有複數第二電性接觸墊，該導電盲孔係形成於該第一線路層與該第二電性接觸墊之間。 The coreless package substrate of claim 1, wherein the second circuit layer has a plurality of second electrical contact pads formed on the first circuit layer and the second circuit. Between the contact pads. 如申請專利範圍第1項所述之無核心層封裝基板，復包括導電層，係形成於該突出構件之接觸面上或再形成於部分該第一電性接觸墊上。 The non-core layer package substrate according to claim 1, further comprising a conductive layer formed on the contact surface of the protruding member or formed on a portion of the first electrical contact pad. 如申請專利範圍第1項所述之無核心層封裝基板，復包括導電層，係形成於該突出構件與該第一電性接觸墊之間。 The non-core layer package substrate according to claim 1, further comprising a conductive layer formed between the protruding member and the first electrical contact pad. 如申請專利範圍第1項所述之無核心層封裝基板，復包括具有複數開孔之絕緣保護層，係形成於該介電層之第二表面與該第二線路層上，並藉由該些開孔分別外露出該第二線路層之第二電性接觸墊。 The non-core layer package substrate according to claim 1, further comprising an insulating protection layer having a plurality of openings formed on the second surface of the dielectric layer and the second circuit layer, and The openings respectively expose the second electrical contact pads of the second circuit layer. 一種無核心層封裝基板之製法，其包括：形成具有複數第一開孔之第一阻層於承載板上；形成複數突出構件於該些第一開孔內；形成具有複數第一電性接觸墊之第一線路層於該第一阻層上，其中，該些第一電性接觸墊係對應形成於該些突出構件上；形成具有相對之第一表面與第二表面之介電層於該第一線路層上，以將該第一線路層嵌埋於該介電層內，其中，該介電層之第一表面係接合至該第一阻層， 且該第一線路層係外露於該介電層之第一表面；形成複數導電盲孔於該介電層內以電性連接該第一線路層，並形成第二線路層於該介電層之第二表面上以電性連接該些導電盲孔；以及移除該第一阻層以外露出該些突出構件之接觸面。 A method for manufacturing a coreless package substrate, comprising: forming a first resist layer having a plurality of first openings on a carrier plate; forming a plurality of protruding members in the first openings; forming a plurality of first electrical contacts a first circuit layer of the pad is disposed on the first resistive layer, wherein the first electrical contact pads are formed on the protruding members correspondingly; forming a dielectric layer having opposite first and second surfaces The first circuit layer is embedded in the dielectric layer, wherein a first surface of the dielectric layer is bonded to the first resistive layer, And the first circuit layer is exposed on the first surface of the dielectric layer; the plurality of conductive blind holes are formed in the dielectric layer to electrically connect the first circuit layer, and the second circuit layer is formed on the dielectric layer The second surface is electrically connected to the conductive blind holes; and the contact surface of the protruding members is exposed outside the first resist layer. 如申請專利範圍第10項所述之無核心層封裝基板之製法，其中，該介電層復具有複數第二開孔，該些導電盲孔係藉由填充導電材料於該些第二開孔內所形成。 The method for manufacturing a coreless package substrate according to claim 10, wherein the dielectric layer has a plurality of second openings, wherein the conductive vias are filled with a conductive material in the second openings. Formed inside. 如申請專利範圍第10項所述之無核心層封裝基板之製法，復包括形成剝離層於該承載板之頂面與底面其中一者或二者上，該第一阻層係形成於該剝離層上，且該些第一開孔係外露出部分該剝離層。 The method for manufacturing a coreless package substrate according to claim 10, further comprising forming a peeling layer on one or both of a top surface and a bottom surface of the carrier sheet, wherein the first resist layer is formed on the stripping layer On the layer, and the first openings expose a portion of the release layer. 如申請專利範圍第12項所述之無核心層封裝基板之製法，復包括形成導電層於該第一阻層、該些第一開孔之壁面及該些第一開孔之剝離層上，該第一線路層係形成於該導電層上，該些突出構件係分別形成於該些第一開孔內之導電層上。 The method for manufacturing a coreless package substrate according to claim 12, further comprising forming a conductive layer on the first resist layer, the wall surface of the first openings, and the peeling layer of the first openings, The first circuit layer is formed on the conductive layer, and the protruding members are respectively formed on the conductive layers in the first openings. 如申請專利範圍第13項所述之無核心層封裝基板之製法，復包括：形成第二阻層於該第一線路層及該些第一電性接觸墊上；依據該第二阻層移除部分該導電層以外露出部分該第一阻層；以及 移除該第二阻層以外露出該第一線路層及該些第一電性接觸墊。 The method for manufacturing a coreless package substrate according to claim 13 further comprising: forming a second resist layer on the first circuit layer and the first electrical contact pads; removing according to the second resist layer a portion of the conductive layer exposing a portion of the first resist layer; Removing the second resist layer exposes the first circuit layer and the first electrical contact pads. 如申請專利範圍第14項所述之無核心層封裝基板之製法，復包括：形成具有複數第三開孔之絕緣保護層於該第二線路層及其複數第二電性接觸墊上，並藉由該些第三開孔分別外露出該些第二電性接觸墊；以及去除該剝離層以移除該承載板。 The method for manufacturing a coreless package substrate according to claim 14, further comprising: forming an insulating protective layer having a plurality of third openings on the second circuit layer and the plurality of second electrical contact pads, and borrowing And exposing the second electrical contact pads respectively from the third openings; and removing the peeling layer to remove the carrier plate. 如申請專利範圍第10項所述之無核心層封裝基板之製法，復包括依序形成剝離層與第一導電層於該承載板之頂面與底面其中一者或二者上，該第一阻層係形成於該第一導電層上，且該些第一開孔係外露出部分該第一導電層。 The method for manufacturing a coreless package substrate according to claim 10, comprising: sequentially forming a peeling layer and a first conductive layer on one or both of a top surface and a bottom surface of the carrier board, the first A resist layer is formed on the first conductive layer, and the first openings expose a portion of the first conductive layer. 如申請專利範圍第16項所述之無核心層封裝基板之製法，復包括形成第二導電層於該第一阻層及該些突出構件上，該第一線路層與該些第一電性接觸墊係形成於該第二導電層上。 The method for manufacturing a coreless package substrate according to claim 16, further comprising forming a second conductive layer on the first resist layer and the protruding members, the first circuit layer and the first electrical properties. A contact pad is formed on the second conductive layer. 如申請專利範圍第17項所述之無核心層封裝基板之製法，復包括：去除該剝離層以移除該承載板；移除該第一導電層與該第一阻層以外露出該些突出構件之接觸面；形成第二阻層於該些突出構件上；依據該第二阻層移除部分該第二導電層以外露出 部分該介電層；以及移除該第二阻層以外露出該些突出構件之接觸面。 The method for manufacturing a coreless package substrate according to claim 17, further comprising: removing the peeling layer to remove the carrier plate; removing the first conductive layer and the first resist layer to expose the protrusions a contact surface of the member; forming a second resist layer on the protruding members; and exposing the second conductive layer according to the second resist layer removing portion a portion of the dielectric layer; and removing a contact surface of the protruding members outside the second resist layer. 如申請專利範圍第10項所述之無核心層封裝基板之製法，其中，該承載板係為不鏽鋼板。 The method for manufacturing a coreless package substrate according to claim 10, wherein the carrier plate is a stainless steel plate.
TW103124499A 2014-07-17 2014-07-17 Coreless package substrate and fabrication method thereof TWI533771B (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
TW103124499A TWI533771B (en) 2014-07-17 2014-07-17 Coreless package substrate and fabrication method thereof
CN201410368060.9A CN105261606B (en) 2014-07-17 2014-07-30 Method for manufacturing coreless packaging substrate
US14/583,317 US9510463B2 (en) 2014-07-17 2014-12-26 Coreless packaging substrate and fabrication method thereof
US15/334,569 US9899249B2 (en) 2014-07-17 2016-10-26 Fabrication method of coreless packaging substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW103124499A TWI533771B (en) 2014-07-17 2014-07-17 Coreless package substrate and fabrication method thereof

Publications (2)

Publication Number Publication Date
TW201605309A TW201605309A (en) 2016-02-01
TWI533771B true TWI533771B (en) 2016-05-11

Family

ID=55075817

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103124499A TWI533771B (en) 2014-07-17 2014-07-17 Coreless package substrate and fabrication method thereof

Country Status (3)

Country Link
US (2) US9510463B2 (en)
CN (1) CN105261606B (en)
TW (1) TWI533771B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI607676B (en) * 2016-06-08 2017-12-01 矽品精密工業股份有限公司 Package substrate and its electronic package and the manufacture thereof

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101672640B1 (en) * 2015-06-23 2016-11-03 앰코 테크놀로지 코리아 주식회사 Semiconductor device
US10276402B2 (en) 2016-03-21 2019-04-30 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor package and manufacturing process thereof
CN107241876B (en) * 2016-03-28 2019-05-07 上海美维科技有限公司 A kind of no core plate single side is sunken cord the processing method of printed circuit board
JP6723389B2 (en) * 2016-05-06 2020-07-15 華為技術有限公司Ｈｕａｗｅｉ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ｃｏ．，Ｌｔｄ． Packaging structure with solder balls and method of manufacturing packaging structure
CN107424973B (en) * 2016-05-23 2020-01-21 凤凰先驱股份有限公司 Package substrate and method for fabricating the same
CN108022896A (en) 2016-11-01 2018-05-11 财团法人工业技术研究院 Chip packaging structure and manufacturing method thereof
CN108022897A (en) 2016-11-01 2018-05-11 财团法人工业技术研究院 Packaging structure and manufacturing method thereof
US10419225B2 (en) 2017-01-30 2019-09-17 Factom, Inc. Validating documents via blockchain
US10446515B2 (en) * 2017-03-06 2019-10-15 Advanced Semiconductor Engineering, Inc. Semiconductor substrate and semiconductor packaging device, and method for forming the same
US10817873B2 (en) 2017-03-22 2020-10-27 Factom, Inc. Auditing of electronic documents
US10270599B2 (en) 2017-04-27 2019-04-23 Factom, Inc. Data reproducibility using blockchains
TWI643532B (en) * 2017-05-04 2018-12-01 南亞電路板股份有限公司 Circuit board structure and method for fabricating the same
US11494402B1 (en) 2017-09-13 2022-11-08 Inveniam Capital Partners, Inc. Apparatus and methods for producing data structures having internal self-references suitable for immutably representing and verifying data
US10783164B2 (en) 2018-05-18 2020-09-22 Factom, Inc. Import and export in blockchain environments
US11134120B2 (en) 2018-05-18 2021-09-28 Inveniam Capital Partners, Inc. Load balancing in blockchain environments
US11170366B2 (en) 2018-05-18 2021-11-09 Inveniam Capital Partners, Inc. Private blockchain services
US20200006273A1 (en) * 2018-06-28 2020-01-02 Intel Corporation Microelectronic device interconnect structure
US11989208B2 (en) 2018-08-06 2024-05-21 Inveniam Capital Partners, Inc. Transactional sharding of blockchain transactions
US11348097B2 (en) 2018-08-06 2022-05-31 Inveniam Capital Partners, Inc. Digital contracts in blockchain environments
CN109729639B (en) 2018-12-24 2020-11-20 奥特斯科技(重庆)有限公司 Component carrier comprising columns on coreless substrate
US11343075B2 (en) 2020-01-17 2022-05-24 Inveniam Capital Partners, Inc. RAM hashing in blockchain environments
US12008526B2 (en) 2021-03-26 2024-06-11 Inveniam Capital Partners, Inc. Computer system and method for programmatic collateralization services
CN113130336A (en) * 2021-04-16 2021-07-16 中国电子科技集团公司第二十四研究所 Flip-chip welding process method for pre-implanting Au salient points on substrate
CN117461125A (en) * 2021-04-26 2024-01-26 上海虹感微电子科技有限公司 Method for manufacturing block-based interconnection structure between microcircuits
US12137179B2 (en) 2021-06-19 2024-11-05 Inveniam Capital Partners, Inc. Systems and methods for processing blockchain transactions
US12007972B2 (en) 2021-06-19 2024-06-11 Inveniam Capital Partners, Inc. Systems and methods for processing blockchain transactions
CN113286439A (en) * 2021-07-22 2021-08-20 深圳市志金电子有限公司 Method for manufacturing electroplated circuit board with built-in lead
US20230070275A1 (en) * 2021-09-09 2023-03-09 Qualcomm Incorporated Package comprising a substrate with a pad interconnect comprising a protrusion
CN118538679A (en) * 2023-11-10 2024-08-23 芯爱科技(南京)有限公司 Package substrate and method for fabricating the same

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006078065A1 (en) * 2005-01-21 2006-07-27 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP4897281B2 (en) * 2005-12-07 2012-03-14 新光電気工業株式会社 Wiring board manufacturing method and electronic component mounting structure manufacturing method
WO2007069606A1 (en) * 2005-12-14 2007-06-21 Shinko Electric Industries Co., Ltd. Substrate with built-in chip and method for manufacturing substrate with built-in chip
JP5113346B2 (en) * 2006-05-22 2013-01-09 日立電線株式会社 Electronic device substrate and manufacturing method thereof, and electronic device and manufacturing method thereof
CN101290917B (en) * 2007-04-17 2011-08-31 南亚电路板股份有限公司 Solder Pad Structure
TWI387064B (en) * 2007-05-03 2013-02-21 Unimicron Technology Corp Semiconductor package substrate structure and manufacturing method thereof
US8779300B2 (en) * 2007-07-19 2014-07-15 Unimicron Technology Corp. Packaging substrate with conductive structure
TWI378544B (en) * 2007-07-19 2012-12-01 Unimicron Technology Corp Package substrate with electrically connecting structure
US8299626B2 (en) * 2007-08-16 2012-10-30 Tessera, Inc. Microelectronic package
US7888184B2 (en) * 2008-06-20 2011-02-15 Stats Chippac Ltd. Integrated circuit packaging system with embedded circuitry and post, and method of manufacture thereof
JP5296590B2 (en) * 2009-03-30 2013-09-25 新光電気工業株式会社 Manufacturing method of semiconductor package
TWI388018B (en) * 2009-10-22 2013-03-01 Unimicron Technology Corp Method of forming package structure
JP5249173B2 (en) * 2009-10-30 2013-07-31 新光電気工業株式会社 Semiconductor device mounting wiring board and method for manufacturing the same
JP5543754B2 (en) * 2009-11-04 2014-07-09 新光電気工業株式会社 Semiconductor package and manufacturing method thereof
CN102054714B (en) * 2009-11-06 2012-10-03 欣兴电子股份有限公司 Manufacturing method of packaging structure
US8330272B2 (en) * 2010-07-08 2012-12-11 Tessera, Inc. Microelectronic packages with dual or multiple-etched flip-chip connectors
US20130249076A1 (en) * 2012-03-20 2013-09-26 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Duplex Plated Bump-On-Lead Pad Over Substrate for Finer Pitch Between Adjacent Traces
US9553070B2 (en) * 2013-04-30 2017-01-24 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9159670B2 (en) * 2013-08-29 2015-10-13 Qualcomm Incorporated Ultra fine pitch and spacing interconnects for substrate
TWI549201B (en) * 2014-04-08 2016-09-11 矽品精密工業股份有限公司 Package structure and manufacturing method thereof
TWI555101B (en) * 2014-05-27 2016-10-21 矽品精密工業股份有限公司 Package structure and method of manufacture
CN105722299B (en) * 2014-12-03 2018-08-31 恒劲科技股份有限公司 Intermediary substrate and its manufacturing method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI607676B (en) * 2016-06-08 2017-12-01 矽品精密工業股份有限公司 Package substrate and its electronic package and the manufacture thereof

Also Published As

Publication number Publication date
US20170047240A1 (en) 2017-02-16
CN105261606A (en) 2016-01-20
US9899249B2 (en) 2018-02-20
CN105261606B (en) 2019-02-15
US20160021743A1 (en) 2016-01-21
US9510463B2 (en) 2016-11-29
TW201605309A (en) 2016-02-01

Similar Documents

Publication Publication Date Title
TWI533771B (en) Coreless package substrate and fabrication method thereof
US11791256B2 (en) Package substrate and method of fabricating the same
TWI548043B (en) Package structure and method of manufacture
TWI497645B (en) Semiconductor package and method for forming the same
TWI529883B (en) Package on package structures, coreless packaging substrates and methods for fabricating the same
TWI525769B (en) Package substrate and manufacturing method thereof
TWI485815B (en) Semiconductor package and method of fabricating the same
TWI582861B (en) Structure of embedded component and manufacturing method thereof
TW201517240A (en) Package structure and manufacturing method thereof
TW201603215A (en) Package structure and method of manufacture
TWI611523B (en) Method for fabricating semiconductor package
TWI594382B (en) Electronic package and method of manufacture
TWI587463B (en) Semiconductor package structure and fabrication method thereof
CN105722299B (en) Intermediary substrate and its manufacturing method
TWI567888B (en) Package structure and method of manufacture
TWI491017B (en) Semiconductor package and method of manufacture
TWI566348B (en) Package structure and method of manufacture
CN113496983A (en) Semiconductor package carrier, method for fabricating the same and semiconductor package process
TWI438880B (en) Package structure having (tsv) through-silicon-vias chip embedded therein and fabrication method thereof
TWI566330B (en) Method of fabricating an electronic package structure
TWI612627B (en) Electronic package and method for fabricating the same
TWI541952B (en) Semiconductor package and manufacturing method thereof
TW201330729A (en) Package structure having embedded electronic element and method of forming same
TWI554170B (en) Interposer substrate and method of fabricating the same
CN108666255A (en) Package stack structure and method for fabricating the same