TWI643532B - Circuit board structure and method for fabricating the same - Google Patents

Abstract

Embodiments of the present invention relate to a circuit board structure, which includes a carrier board, a first circuit layer disposed on the carrier board, a dielectric layer disposed on the first circuit layer, and a first layer buried in the dielectric layer. Two line layers. The second circuit layer is exposed from an upper surface of the dielectric layer. The circuit board structure also includes a via hole buried in the dielectric layer and electrically connecting the first circuit layer and the second circuit layer, and a metal pillar provided on the second circuit layer exposed on the upper surface of the dielectric layer. .

Description

Circuit board structure and manufacturing method thereof

Embodiments of the present invention relate to a circuit board structure, and more particularly, to a circuit board structure with a carrier board and a manufacturing method thereof.

Printed circuit boards (PCBs) are widely used in various electronic devices. The printed circuit board can not only fix various electronic parts, but also provide electrical connection between the electronic parts.

In order to prevent the printed circuit board from being deformed (such as warpage) in related processes (such as packaging process), it is sometimes necessary to form a solder resist paint (such as a solder resist green paint) in the printed circuit board. Lacquer is not easily removed, so it usually stays in the printed circuit board and increases the overall thickness of the printed circuit board. However, the above-mentioned increase in thickness is not conducive to the reduction of the printed circuit board.

Therefore, a new printed circuit board structure and a method for manufacturing the same are needed to improve the above problems.

An embodiment of the present invention provides a circuit board structure including a carrier board, a first circuit layer disposed on the carrier board, a dielectric layer disposed on the first circuit layer, and a second circuit layer buried in the above. In the dielectric layer, and the second circuit layer is exposed from the upper surface of the dielectric layer; a via is buried in the dielectric layer And electrically connecting the first circuit layer and the second circuit layer; and a metal pillar disposed on the second circuit layer exposed on the upper surface of the dielectric layer.

An embodiment of the present invention also provides a method for manufacturing a circuit board structure, including: providing a substrate; forming a patterned conductive layer on the substrate, wherein the patterned conductive layer has a metal pillar groove; and forming a metal pillar on the metal pillar groove And forming a first circuit layer on the metal pillar; forming a via hole on the first circuit layer; forming a dielectric layer on the patterned conductive layer and surrounding the via hole and the first circuit layer; forming a second circuit Layer on the dielectric layer; and bonding the carrier board to the dielectric layer and the second circuit layer.

10, 20, 30‧‧‧ circuit board structure

100‧‧‧ substrate

102‧‧‧ floor

104‧‧‧first metal layer

202‧‧‧patterned cover layer

302‧‧‧ patterned conductive layer

304‧‧‧ metal pillar trench

402‧‧‧metal pillar

404‧‧‧line layer

406‧‧‧metal pad

502‧‧‧ guide hole

602‧‧‧ Dielectric layer

W‧‧‧Width

T ₁ ‧‧‧ thickness

702‧‧‧line layer

802‧‧‧ Carrier Board

804‧‧‧Joint layer

T ₂ ‧‧‧ thickness

1002‧‧‧Chip

1004‧‧‧Packaging material

1006‧‧‧Joint material

1008‧‧‧Joint pad

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale and are for illustration purposes only. In fact, it is possible to arbitrarily enlarge or reduce the size of the element to clearly show the characteristics of the embodiment of the present invention.

Figures 1-9 are a series of cross-sectional views illustrating a method for manufacturing a circuit board structure according to some embodiments of the present invention, and Figure 9 is a cross-sectional view illustrating a circuit board structure 10 according to an embodiment of the present invention .

FIG. 10 is a cross-sectional view of a circuit board structure 20 according to an embodiment of the present invention.

FIG. 11 is a cross-sectional view showing a circuit board structure 30 according to an embodiment of the present invention.

Many different implementation methods or examples are disclosed below to implement the different features of the embodiments of the present invention. The following describes the implementation of specific elements and their arrangements. The examples illustrate the invention. Of course, these embodiments are only for illustration, and the scope of the embodiments of the present invention should not be limited by this. For example, in the description, it is mentioned that the first element is formed on the second element, which includes an embodiment in which the first element and the second element are in direct contact, and also includes the other between the first element and the second element. An embodiment of the element, that is, the first element is not in direct contact with the second element. In addition, repeated reference numerals or signs may be used in different embodiments. These repetitions are only for simply and clearly describing the embodiments of the present invention, and do not represent a specific relationship between the different embodiments and / or structures discussed.

In addition, space-related terms such as "below", "below", "lower", "above", "higher" and similar terms may be used. These space-related terms Words are used to facilitate the description of the relationship between one or more elements or features and other elements or features in the illustration. These spatially related terms include different positions of the device in use or operation, and The described orientation. The device may be turned to different orientations (rotated 90 degrees or other orientations), and the spatially related adjectives used therein can be interpreted the same way.

The manufacturing method of the circuit board structure according to the embodiment of the present invention is to form a carrier board in the circuit board structure, so that the circuit board structure can be prevented from being deformed such as warping during the manufacturing process. In addition, the carrier board can be removed from the circuit board structure at a proper timing to reduce the overall thickness of the circuit board structure.

FIG. 1 illustrates the initial steps of a method for manufacturing a circuit board structure according to an embodiment of the present invention. First, a substrate 100 is provided. In some embodiments, the substrate 100 may include a metal-clad laminate (for example, a copper foil substrate), which may include a base plate 102 and first metal layers 104 disposed on opposite sides of the base plate 102. For example, the bottom plate 102 may include paper phenolic resin (paper phenolic resin, composite epoxy, polyimide resin, glass fiber, other appropriate insulating materials, or a combination thereof, and the thickness thereof may be 100 μm to 300 μm. The first metal layer 104 may include copper, silver, other suitable metals, an alloy thereof, or a combination thereof, and the thickness thereof may be 5 μm to 30 μm. The first metal layer 104 may be formed on the base plate 102 by using an appropriate method, such as sputtering, laminating, coating, or a combination thereof. It should be noted that, in some other embodiments of the present invention, the substrate 100 is not limited to a metal-clad laminated board, and may also include a single-layer board, a high-density connection board, or other appropriate substrates.

Next, referring to FIG. 2, a patterned mask layer 202 is formed on the first metal layer 104. For example, the patterned mask layer 202 may include a dry film, a liquid photoresist, other suitable materials, or a combination thereof. In some embodiments, an unpatterned mask layer 202 may be formed on the first metal layer 104 by printing, spin coating, lamination, other suitable methods, or a combination of the above, and then subjected to processes such as exposure and development to A patterned mask layer 202 is formed.

Next, as shown in FIG. 3, a patterned conductive layer 302 is formed on the first metal layer 104 exposed by the patterned mask layer 202, and then the patterned mask layer 202 is removed to form the patterned conductive layer 302. Corresponding to the trenches 304 of the patterned mask layer 202, the above trenches 304 will be subsequently filled with metal pillars, and thus are also referred to as metal pillar trenches 304. For example, the patterned conductive layer 302 may include copper, tungsten, silver, tin, nickel, cobalt, chromium, titanium, lead, gold, bismuth, antimony, zinc, zirconium, magnesium, indium, tellurium, gallium, other suitable Metal materials, alloys thereof, or combinations thereof. In some embodiments, the first metal layer 104 can be used as a conductive path for a plating process to form a patterned conductive layer 302, and then an appropriate process (for example, a peeling process) is performed to The patterned mask layer 202 is removed to form a metal pillar trench 304.

Next, as shown in FIG. 4, a metal pillar 402 is formed in the metal pillar trench 304, and a circuit layer 404 is formed on the metal pillar 402 and the patterned conductive layer 302. For example, the metal pillar 402 and the circuit layer 404 may include copper, tungsten, silver, tin, nickel, cobalt, chromium, titanium, lead, gold, bismuth, antimony, zinc, zirconium, magnesium, indium, tellurium, gallium, others Appropriate metallic materials, alloys or combinations thereof. As shown in FIG. 4, the circuit layer 404 may include a metal pad 406 in direct contact with the metal pillar 402. In some embodiments, printing, spin coating, lamination, exposure, development, other suitable methods, or a combination of the foregoing can be used to form, for example, a dry film, a liquid photoresist, or a combination of the foregoing on the patterned conductive layer 302. A patterned mask layer (not shown), the patterned mask layer has a circuit layer groove corresponding to the circuit layer 404, and then a patterned conductive layer 302 is used as a conductive path for a plating process to form a metal pillar 402 on The metal pillar trench 304 and the circuit layer 404 are formed in the above-mentioned circuit layer trench, and then an appropriate process (for example, a film peeling process) is performed to remove the patterned mask layer. In some embodiments, since the patterned conductive layer 302 can serve as a conductive path, the metal pillar 402 and the circuit layer 404 can be formed simultaneously in a single electroplating process, so that both the metal pillar 402 and the circuit layer 404 include the same metal (for example, : Both include copper) and are integrally formed (for example, the metal pad 406 and the metal pillar 402 of the circuit layer 404 are integrally formed) to obtain better mechanical properties.

In some embodiments, the patterned conductive layer 302 includes a metal different from the metal pillar 402 and the circuit layer 404 (for example, the patterned conductive layer 302 includes nickel, cobalt, or a combination thereof, and the metal pillar 402 and the circuit layer 404 include copper ), An appropriate process (eg, a selective etching process) can be subsequently performed to remove the patterned conductive layer 302 without substantially removing the metal pillars 402 and the circuit layer 404, which will be changed later Add details.

It should be noted that although the cross-sectional profile of the metal pillar 402 is rectangular in the embodiment shown in FIG. 4, the embodiment of the present invention is not limited thereto, and the cross-sectional profile of the metal pillar 402 may be inverted according to requirements. Trapezoidal, T-shaped, inverted L-shaped, zigzag, other suitable shapes, or a combination of the above.

Next, as shown in FIG. 5, a via hole 502 is formed on the wiring layer 404. In some embodiments, the via 502 can be electrically connected to the circuit layer 404 and another circuit layer formed subsequently. For example, the via 502 may include copper, tungsten, silver, tin, nickel, cobalt, chromium, titanium, lead, gold, bismuth, antimony, zinc, zirconium, magnesium, indium, tellurium, gallium, other suitable metal materials , An alloy thereof, or a combination thereof, and the width W thereof may be 10 μm to 65 μm and have substantially straight sidewalls. In some embodiments, printing, spin coating, lamination, exposure, development, other suitable methods, or a combination of the foregoing may be used to form, for example, a dry film, a liquid photoresist on the patterned conductive layer 302 and the circuit layer 404. Or the combined patterned masking layer (not shown), the patterned masking layer has a via hole groove corresponding to the via hole 502, and then a conductive material is filled in the aforementioned via hole groove to form a guide hole. The holes 502 are then subjected to a suitable process (eg, a film peeling process) to remove the patterned mask layer. In some embodiments, the via layer 404 can be used as a conductive path for a plating process to fill the above-mentioned via trench with a conductive material to form the via 502.

Next, a dielectric layer 602 is formed on the patterned conductive layer 302. As shown in FIG. 6, the dielectric layer 602 may surround the via hole 502 and the circuit layer 404, and the upper surface of the dielectric layer 602 may be coplanar with the upper surface of the via hole 502. For example, the thickness T _{1 of the} dielectric layer 602 may be 15 to 100 μm. In some embodiments, paper phenolic resin, composite epoxy, polyimide resin, glass fiber, and ABF film (Ajinomoto Build- up Film). Other appropriate dielectric materials or combinations of the above are pressed onto the patterned conductive layer 302, so that the vias 502 and the circuit layer 404 are buried in the above-mentioned dielectric material, and then a leveling process is performed to remove a portion of the above-mentioned dielectric material. , So that the upper surface of the unremoved dielectric material (ie, the dielectric layer 602) is coplanar with the upper surface of the via 502.

It should be noted that, in the foregoing embodiment, the via hole is formed before the step of forming the dielectric layer, so that the method of the foregoing embodiment does not need to be compared with the case where the dielectric layer is formed first and then the via hole is formed therein. Via holes corresponding to the via holes are formed in the dielectric layer. Due to process capacity limitations, the via hole formed in the dielectric layer usually has a larger width than the via hole formed in the mask layer (such as dry film, liquid photoresist, or a combination of the above). , So that the formed guide hole also has a larger width, which is not conducive to the reduction of the circuit board structure. In contrast, the method of forming a via hole by using the patterned mask layer in the foregoing embodiment can avoid this problem and can have a smaller via hole width (eg, 10 μm to 65 μm).

Next, as shown in FIG. 7, a circuit layer 702 is formed on the dielectric layer 602. For example, the circuit layer 702 may include copper, tungsten, silver, tin, nickel, cobalt, chromium, titanium, lead, gold, bismuth, antimony, zinc, zirconium, magnesium, indium, tellurium, gallium, other suitable metal materials , An alloy thereof, or a combination thereof. In some embodiments, the metal blanket layer (not shown) may be first formed by an appropriate method (for example, physical vapor deposition (e.g., evaporation or sputtering), atomic layer deposition (ALD), electroplating, or a combination thereof). (Illustrated) on the dielectric layer 602, and then a lithography and etching process is performed to form a circuit layer 702. In other embodiments, a seed layer (not shown) may be formed on the dielectric layer 602, and then printing, spin coating, lamination, exposure, development, and other appropriate The method or the combination described above forms, on the seed layer, a patterned mask layer (not shown), such as a dry film, a liquid photoresist, or a combination thereof. The patterned mask layer has a layer corresponding to the circuit layer 702. The circuit layer trench is then subjected to a plating process using the seed layer as a conductive path to fill a conductive material in the circuit layer trench to form a circuit layer 702, and then an appropriate process (eg, a peeling process) is performed to remove The patterned mask layer.

Next, as shown in FIG. 8, the carrier board 802 is bonded to the dielectric layer 602 and the wiring layer 702. In some embodiments, the carrier board 802 can prevent harmful deformation (such as warping) of the circuit board structure. For example, the carrier plate 802 may include resin, epoxy resin, glass fiber, other suitable materials, or a combination thereof, and the thickness T _{2 thereof} may be 100 μm to 300 μm. For example, the thickness of the dielectric layer ₂ of 602 T T ratio of ₁ if the thickness 802 of the carrier plate (T ₂ / T ₁₎ is too low, the circuit board may be unable to effectively avoid deformation of the structure, however, if the thickness of the carrier plate 802 T ₂ and the thickness of the dielectric layer 602 of the ratio T ₁ (T ₂ / T ₁₎ is too high, it may increase the production cost. In some embodiments, the carrier 802 of the plate thickness T ₂ and the thickness of the dielectric layer 602 may have a T ₁ of the appropriate ratio (T ₂ / T _1), for example: 1-2.

As shown in FIG. 8, in some embodiments, the carrier board 802 may be bonded to the dielectric layer 602 and the circuit layer 702 via a bonding layer 804. For example, the bonding layer 804 may include a peelable adhesive (eg, UV peelable adhesive), which can be easily peeled from the dielectric layer 602 and the circuit layer 702. In some embodiments, the bonding layer 804 can be peeled from the dielectric layer 602 and the circuit layer 702 and the carrier board 802 can be removed from the circuit board structure at an appropriate timing (for example, after the packaging process) to reduce the circuit board structure. The overall thickness will be described in more detail later.

Next, as shown in FIG. 9, the substrate 100 and the patterned conductive layer are removed. Layer 302 to form the circuit board structure 10. For example, the substrate 100 may be physically removed by applying an appropriate peeling force, and then selectively etched with an appropriate etchant (eg, nitric acid) to remove the patterned conductive layer 302 to expose the circuit layer 404 and the substrate. The metal layer 402 protrudes from the dielectric layer 602. As mentioned above, in some embodiments, the patterned conductive layer 302 includes a metal different from the metal pillar 402 and the circuit layer 404 (for example, the patterned conductive layer 302 includes nickel, cobalt, or a combination thereof, and the metal pillars 402 and The circuit layer 404 includes copper), so the above-mentioned etching process can remove the patterned conductive layer 302 without substantially removing the metal pillars 402 and the circuit layer 404.

As shown in FIG. 9, the circuit board structure 10 includes a carrier board 802, a circuit layer 702 disposed on the carrier board, a dielectric layer 602 disposed on the circuit layer 702, and a self-dielectric layer buried in the dielectric layer 602. A circuit layer 404 exposed on the upper surface of 602, a via hole 502 buried in the dielectric layer 602 and electrically connected to the circuit layer 702 and the circuit layer 404, and a metal pillar 402 disposed on the circuit layer 404. As described above, the circuit board structure 10 includes a carrier board 802, which can avoid harmful deformation in subsequent processes (for example, a packaging process).

Then, a conformal protection layer (not shown) is formed on the metal pillars 402 and the circuit layer 404 according to requirements, so as to prevent the metal pillars 402 and the circuit layer 404 from rusting. For example, the above-mentioned conformal protective layer may include Organic Solderability Preservative (OSP), other suitable materials, or a combination thereof. In some embodiments, the conformal protective layer may be subsequently removed as required, for example, the conformal protective layer may be removed before the packaging process.

Next, as shown in FIG. 10, a packaging process is performed to bond the wafer 1002 to the metal pillar 402 to form a circuit board structure 20. In some embodiments, the bonding of the wafer 1002 may be performed via solder bumps or other suitable bonding materials 1006. The pad 1008 is bonded to the metal post 402. In some other embodiments, the bonding pad 1008 can also be directly bonded to the metal pillar 402 by using eutectic bonding, so that the bonding pad 1008 is in direct contact with the metal pillar 402. For example, the bonding pad 1008 may include copper, aluminum, an alloy thereof, other suitable conductive materials, or a combination thereof. In some embodiments, the above packaging process may be performed at a high temperature (for example, 150 to 300 ° C.), which may cause harmful deformation of the circuit board structure. However, the circuit board structure 10 of the embodiment of the present invention has a carrier board 802 and may Avoid this problem. In addition, as shown in FIG. 10, the above packaging process can also form a packaging material 1004 surrounding the metal pillars 402 to protect the circuit board structure.

Next, as shown in FIG. 11, after the above packaging process, the carrier board 802 is removed to form a circuit board structure 30. As described above, the bonding layer 804 can be peeled from the dielectric layer 602 and the circuit layer 702 and the carrier board 802 can be removed from the circuit board structure 20, so that the formed circuit board structure 30 has a smaller thickness.

It should be noted that although the circuit board structure is formed on one side of the substrate 100 in the embodiment shown in FIGS. 1-11, in some other embodiments, the circuit board may be formed on both sides of the substrate 100. Structure and increase production efficiency. In some embodiments, the circuit board structures formed on both sides of the substrate 100 may include different circuit designs to increase the flexibility of the process.

To sum up, the manufacturing method of the circuit board structure according to the embodiment of the present invention is to form a carrier board in the circuit board structure, thereby avoiding harmful deformation of the circuit board structure in a process that is prone to deformation (for example, a packaging process). In addition, after the purpose of avoiding the deformation of the circuit board structure is achieved, the carrier board can be removed from the circuit board structure at an appropriate timing to reduce the overall thickness of the circuit board structure.

Although the present invention has been disclosed as above with several preferred embodiments, It is not intended to limit the present invention. Any person with ordinary knowledge in the technical field can make any changes and modifications without departing from the spirit and scope of the embodiments of the present invention. The ones defined in the scope of patent application shall prevail.

Claims (18)

A circuit board structure includes: a carrier board; a first circuit layer disposed on the carrier board; a dielectric layer disposed on the first circuit layer; and a bonding layer disposed on the carrier board and Between the dielectric layers; a second circuit layer buried in the dielectric layer, and the second circuit layer is exposed from an upper surface of one of the dielectric layers; a via is buried in the dielectric And the first circuit layer and the second circuit layer are electrically connected in a layer; and a metal pillar is disposed on the second circuit layer exposed on the upper surface of the dielectric layer. The circuit board structure according to item 1 of the scope of patent application, wherein the ratio of the thickness of the carrier board to the thickness of the dielectric layer is 1 to 2. The circuit board structure according to item 1 of the patent application scope, wherein the guide hole has a substantially straight side wall. The circuit board structure according to item 3 of the scope of the patent application, wherein the width of the guide hole is 10 μm to 65 μm. According to the circuit board structure described in item 1 of the patent application scope, wherein the second circuit layer includes a metal pad, and the metal pillar directly contacts the metal pad. The circuit board structure described in item 5 of the scope of the patent application, wherein the metal pillar and the metal pad include the same metal and the two are integrally formed. The circuit board structure described in item 1 of the patent application scope, wherein the adhesive layer includes a peelable adhesive. A method for manufacturing a circuit board structure includes: providing a substrate; forming a patterned conductive layer on the substrate, wherein the patterned conductive layer has a metal pillar groove; forming a metal pillar in the metal pillar groove; and Forming a first circuit layer on the metal pillar; forming a via hole on the first circuit layer; forming a dielectric layer on the patterned conductive layer and surrounding the via hole and the first circuit layer; forming a A second circuit layer is on the dielectric layer; and a carrier board is bonded to the dielectric layer and the second circuit layer through an adhesive layer, so that the adhesive layer is located between the carrier board and the dielectric layer. The method for manufacturing a circuit board structure according to item 8 of the scope of patent application, wherein the patterned conductive layer includes nickel, cobalt, or a combination thereof. The method for manufacturing a circuit board structure according to item 8 of the scope of patent application, wherein the step of forming the via hole includes: forming a patterned mask layer on the patterned conductive layer and the first circuit layer, wherein the The patterned mask layer has a via hole trench; a conductive material is filled in the via hole trench to form the via hole; and the patterned mask layer is removed. The method for manufacturing a circuit board structure according to item 8 of the scope of patent application, wherein the step of forming the dielectric layer includes: pressing a dielectric material onto the patterned conductive layer, so that the via hole and the first The circuit layer is buried in the dielectric material and a leveling process is performed so that an upper surface of one of the dielectric materials and an upper surface of one of the via holes are coplanar to form the dielectric layer. The method for manufacturing a circuit board structure according to item 8 of the scope of patent application, further comprising: removing the substrate and the patterned conductive layer to expose the metal pillar and the exposed metal pillar protruding from the dielectric layer. According to the method for manufacturing a circuit board structure described in item 12 of the patent application scope, the method further includes: after the step of removing the substrate and the patterned conductive layer, forming a conformal protective layer on the exposed metal pillar. The method for manufacturing a circuit board structure according to item 12 of the scope of patent application, further includes: bonding the exposed metal pillar to a wafer; and forming a packaging material surrounding the exposed metal pillar. The method for manufacturing a circuit board structure described in item 14 of the scope of patent application, further includes: removing the carrier board after the step of forming the packaging material. The method for manufacturing a circuit board structure according to item 15 of the scope of the patent application, wherein the adhesive layer includes a peelable adhesive, and the step of removing the carrier board includes removing the conductive layer from the dielectric layer and the second circuit layer. Peel off. The method for manufacturing a circuit board structure according to item 8 of the scope of the patent application, wherein the substrate includes a metal-clad laminate. The method for manufacturing a circuit board structure according to item 8 of the scope of patent application, wherein a plating process is performed through the patterned conductive layer to form the metal pillar and the first circuit layer.