CN107481991A - Package substrate, electronic package and manufacturing method thereof - Google Patents
Package substrate, electronic package and manufacturing method thereof Download PDFInfo
- Publication number
- CN107481991A CN107481991A CN201610504135.0A CN201610504135A CN107481991A CN 107481991 A CN107481991 A CN 107481991A CN 201610504135 A CN201610504135 A CN 201610504135A CN 107481991 A CN107481991 A CN 107481991A
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- protective layer
- insulating protective
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- 239000000758 substrate Substances 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title abstract description 5
- 239000010410 layer Substances 0.000 claims abstract description 63
- 239000011241 protective layer Substances 0.000 claims abstract description 55
- 238000012856 packing Methods 0.000 claims description 39
- 238000002360 preparation method Methods 0.000 claims description 37
- 238000003466 welding Methods 0.000 claims description 7
- 238000009413 insulation Methods 0.000 claims description 5
- 230000005611 electricity Effects 0.000 claims description 4
- 239000012792 core layer Substances 0.000 abstract description 17
- 238000004806 packaging method and process Methods 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 5
- 230000000149 penetrating effect Effects 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 description 11
- 238000005538 encapsulation Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 230000004888 barrier function Effects 0.000 description 4
- 239000011230 binding agent Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000004220 aggregation Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Wire Bonding (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A package substrate, an electronic package and a fabrication method thereof are provided, the package substrate includes: the packaging substrate comprises an insulating protective layer, a circuit layer embedded in the insulating protective layer and not penetrating through the insulating protective layer, and a conductive column penetrating through the insulating protective layer and electrically connected with the circuit layer, so that the packaging substrate only comprises one circuit layer without using a core layer, and the thickness of the packaging substrate can be greatly reduced.
Description
Technical field
A kind of relevant package substrate of the present invention, the package substrate and its electronic packing piece and system of espespecially a kind of seedless central layer
Method.
Background technology
With flourishing for electronic industry, many high-order electronic products are all gradually toward light, thin, short, small contour aggregation degree
Direction is developed, and with the evolution of encapsulation technology, the encapsulation technology of chip is also more and more diversified, the size of semiconductor package part
Or volume also constantly reduces therewith, uses the purpose for making the semiconductor package part reach compact
Fig. 1 is the schematic cross-sectional view of existing flip-chip type semiconductor packaging part 1.As shown in figure 1, the semiconductor package part 1 wraps
Include a package substrate 1a and semiconductor element 9.
Described package substrate 1a is included：Core layer 10；It is formed at the first line layer 12a and second on the surface of core layer 10
Line layer 12b；Conductive hole 13, it runs through the core layer 10, to be electrically connected with the first line layer 12a and the second line layer 12b；
First insulating barrier 11a and the second insulating barrier 11b, it is respectively formed on the first line layer 12a and the second line layer 12b, and
Expose outside part first line layer 12a and the second line layer 12b.
Described semiconductor element 9 has multiple electrode pads 90, to combine multiple conductive projections 91, is bound in order to for flip
First line layer 12a.
In existing package substrate 1a, it has at least two layers of line layer (first line layer 12a and the second line layer
12b), and by the conductive hole 13 it is electrically connected with the first line layer 12a and the second line layer 12b.
However, the conductive hole 13 need to pass through machine drilling or Laser drill forms in the core layer 10 and runs through the core layer
After 10 through hole 100, electro-coppering in the through hole 100 run through then at this, thus increase the complexity of processing procedure.
In addition, existing package substrate 1a is because having core layer 10 and at least two layers of line layer, and it is difficult to reduce the encapsulation
Substrate 1a thickness, therefore in the case where package substrate 1a thickness is difficult to reduce, the thickness of overall semiconductor packaging part 1
It is difficult to effectively reduce.
Therefore, the variety of problems of above-mentioned prior art how is overcome, it is real into the problem for desiring most ardently solution at present.
The content of the invention
In view of the disadvantages of above-mentioned prior art, the present invention provides a kind of package substrate and its electronic packing piece and system
Method, its thickness can be greatly reduced.
The package substrate of the present invention, including：One insulating protective layer, it has relative first surface and second surface；One
Line layer, it is embedded into the first surface of the insulating protective layer and exposes to the first surface and do not expose to second table
Face；And conductive pole, it is penetratingly formed in the insulating protective layer and exposes to the first surface and second surface and electrical
Connect the line layer.
The present invention also provides a kind of preparation method of package substrate, including：There is provided one has relative first surface and the second table
The insulating protective layer in face, wherein, the insulating protective layer formed with multiple perforates and an at least through hole, the perforate be formed at this first
The second surface is not connected on surface, and the through hole connects the first surface and second surface；And line layer is formed in this
In perforate, and conductive pole is formed in the through hole, and the conductive pole is electrically connected with the line layer.
In foregoing preparation method, in addition to first the insulating protective layer is bound on a bearing part with its second surface, then shape
Into the perforate and the through hole.It is included in form the line layer with after the conductive pole, removing the bearing part again.
In foregoing package substrate and its preparation method, the insulating protective layer is welding resisting layer.
In foregoing package substrate and its preparation method, the surface of the line layer flushes the first surface of the insulating protective layer.
In foregoing package substrate and its preparation method, the conductive pole has relative first end face and second end face, make this
End face exposes to the first surface, and the second end face exposes to the second surface.For example, the first end face flush this first
Surface and/or the second end face flush the second surface.
The present invention also provides a kind of electronic packing piece, including：Foregoing package substrate；And electronic component, it is located at should
On the first surface of insulating protective layer and it is electrically connected with the conductive pole.
The present invention separately provides a kind of preparation method of electronic packing piece, including：One foregoing package substrate is provided；And electricity is set
Subcomponent makes the electronic component be electrically connected with the conductive pole on the first surface of the insulating protective layer.
In foregoing electronic packing piece and its preparation method, the first end face of the conductive pole is electrically connected with the electronic component.
In foregoing electronic packing piece and its preparation method, in addition to encapsulated layer is formed on the first surface of the insulating protective layer
To coat the electronic component.
In addition, in foregoing electronic packing piece and its preparation method, in addition to multiple conducting elements are set in the insulating protective layer
Second surface on, and the conducting element is electrically connected with the conductive pole.
From the foregoing, it will be observed that the package substrate and its electronic packing piece and preparation method of the present invention, release uses core layer, therefore without system
Make the existing conductive hole through core layer, thus compared to prior art, reach simple fabrication steps and reduce the purpose of cost.
In addition, it is of the invention because not having existing core layer, and the thickness of the package substrate can be greatly reduced, therefore in the encapsulation
In the case that the thickness of substrate is minimized, the integral thickness of the electronic packing piece can also effectively reduce.
Brief description of the drawings
Fig. 1 is the schematic cross-sectional view of existing flip-chip type semiconductor packaging part；
Fig. 2A to Fig. 2 E is the schematic cross-sectional view of the preparation method of the package substrate of the present invention；And
Fig. 3 A and Fig. 3 B are the schematic cross-sectional view of the preparation method of the electronic packing piece of the present invention；Wherein, Fig. 3 A ' and Fig. 3 B ' are
Fig. 3 A and Fig. 3 B another embodiment.
Symbol description：
1 semiconductor package part
1a, 2 package substrates
10 core layers
100,211 through holes
The insulating barriers of 11a first
The insulating barriers of 11b second
12a first line layers
The line layers of 12b second
13 conductive holes
20 bearing parts
200 binder courses
21 insulating protective layers
21a first surfaces
21b second surfaces
210 perforates
211 ' shrinkage pools
22 line layers
22a surfaces
23 conductive poles
23a first end faces
23b second end faces
3,3 ' electronic packing pieces
30 electronic components
30a acting surfaces
The non-active faces of 30b
300,90 electronic padses
31,91 conductive projections
31 ' bonding wires
32 conducting elements
33 encapsulated layers
9 semiconductor elements.
Embodiment
Illustrate embodiments of the present invention below by way of particular specific embodiment, those skilled in the art can be by this explanation
Content disclosed in book understands other advantages and effect of the present invention easily.
It should be clear that structure, ratio, size depicted in this specification institute accompanying drawings etc., only coordinating specification to be taken off
The content shown, for the understanding and reading of those skilled in the art, the enforceable qualifications of the present invention are not limited to, therefore
Do not have technical essential meaning, the modification of any structure, the change of proportionate relationship or the adjustment of size, do not influenceing the present invention
Under the effect of can be generated and the purpose that can reach, it all should still fall and obtain the model that can cover in disclosed technology contents
In enclosing.Meanwhile in this specification cited such as " on ", " under ", " first ", " second " and " one " term, be also only just
In understanding for narration, and it is not used to limit the enforceable scope of the present invention, its relativeness is altered or modified, without substantive change
Under more technology contents, when being also considered as the enforceable category of the present invention.
Fig. 2A to Fig. 2 E is the schematic cross-sectional view of the preparation method of the package substrate 2 of the present invention.
As shown in Fig. 2A to Fig. 2 B, there is provided a bearing part 20, and the upper and lower both sides of the bearing part 20 are equipped with insulation guarantor
Sheath 21, and the insulating protective layer 21 has relative first surface 21a and second surface 21b, and tied with its second surface 21b
It is bonded on the bearing part 20.Then, in formed on the first surface 21a of the insulating protective layer 21 multiple perforates 210 with it is multiple logical
Hole 211.
In the present embodiment, the bearing part 20 combines the insulation with binder course 200 (such as mould release membrance, metal level or adhesion layer)
Protective layer 21.
In addition, the insulating protective layer 21 is welding resisting layer, and those perforates 210 do not connect second surface 21b, and those are logical
Hole 211 connects first surface 21a and second surface 21b.
Also, the processing procedure of the through hole 211 is as shown in Figure 2 A, multiple shrinkage pool 211' are formed in the lump when those perforates 210 are formed,
Again as shown in Figure 2 B, the through hole 211 is formed at shrinkage pool 211'.
As shown in Figure 2 C, a line layer 22 is formed in those perforates 210, and forms multiple conductive poles 23 in those through holes
In 211, and those conductive poles 23 are made to be electrically connected with the line layer 22.
In the present embodiment, the line layer 22 is embedded into the first surface 21a of the insulating protective layer 21, and the line layer
22 surface 22a flushes the first surface 21a of the insulating protective layer 21.
In addition, the conductive pole 23 have to should first surface 21a first end face 23a and to should second surface 21b
Second end face 23b, first end face 23a is exposed to first surface 21a, and second end face 23b expose to this second
Surface 21b.For example, first surface 21a flushes first end face 23a, and second surface 21b flushes second end face 23b.
As shown in Fig. 2 D to Fig. 2 E, the bearing part 20 is removed, to obtain multiple package substrates 2.
In the present embodiment, the bearing part 20 and the respectively package substrate 2 are separated by binder course 200.
The preparation method of the package substrate of the present invention is mainly used as main body by the insulating protective layer 21, avoids using core layer,
It is therefore not necessary to make the existing conductive hole through core layer, therefore fabrication steps and cost can be simplified.
In addition, the present invention only has a sandwich circuit layer, and existing core layer is not used, thus the encapsulation base can be greatly reduced
The thickness of plate 2.
As shown in Fig. 3 A and Fig. 3 B, in the subsequent applications of the package substrate 2, set an at least electronic component 30 exhausted in this
On the first surface 21a of edge protective layer 21, and the encapsulated layer 33 just like packing colloid (molding compound) is formed in this
To coat the electronic component 30 on the first surface 21a of insulating protective layer 21, and form multiple conducting elements 32 such as solder ball
In on the second surface 21b of the insulating protective layer 21, to form the electronic packing piece 3 of the present invention.
In the present embodiment, those conducting elements 32 are corresponding to be bound on the second end face 23b of the respectively conductive pole 23, with order
The conducting element 32 is electrically connected with the conductive pole 23.
In addition, the electronic component 30 is active member, passive device or combination both it, wherein, the active member is for example
Semiconductor chip, and the passive device such as resistance, electric capacity and inductance.For example, the electronic component 30 has relative acting surface
30a and non-active face 30b, and acting surface 30a has multiple electrode pads 300, and the electronic component 30 is with its electricity of electronic pads 300
Property connects those conductive poles 23.
Specifically, as shown in Figure 3A, the electronic pads 300 of the electronic component 30 is bound to by multiple flips of conductive projection 31
On the first end face 23a of the conductive pole 23, to make the electronic component 30 be electrically connected with those conductive poles 23.Or such as Fig. 3 A ' and
Electronic packing piece 3 ' shown in Fig. 3 B ', the electronic component 30 are located at the first surface of the insulating protective layer 21 with non-active face 30b
On 21a, and the first end face 23a of those electronic padses 300 and the conductive pole 23 is electrically connected with multiple bonding wires 31 ', to make the electricity
Subcomponent 30 is electrically connected with those conductive poles 23.
The electronic packing piece 3,3 ' of the present invention is in the case where the thickness of the package substrate 2 is minimized, its integral thickness
Also can effectively reduce.
The present invention provides a kind of package substrate 2, including：One insulating protective layer 21, a line layer 22 and multiple conductive poles
23。
Described insulating protective layer 21 has relative first surface 21a and second surface 21b, and the insulating protective layer 21
For welding resisting layer.
Described line layer 22 is embedded into the first surface 21a of the insulating protective layer 21 and exposes to the first surface
21a and second surface 21b is not exposed to.
Described conductive pole 23 is penetratingly formed in the insulating protective layer 21 and exposes to first surface 21a and second
Surface 21b is simultaneously electrically connected with the line layer 22.
In an embodiment, the surface 22a of the line layer 22 flushes the first surface 21a of the insulating protective layer 21.
In an embodiment, the conductive pole 23 has relative first end face 23a and second end face 23b, makes the first end
Face 23a exposes to first surface 21a, and second end face 23b exposes to second surface 21b.For example, the first surface
21a flushes first end face 23a, and second surface 21b flushes second end face 23b.
The present invention also provides a kind of electronic packing piece 3, and 3 ', including：Above-mentioned package substrate 2 and electronic component 30.
Described electronic component 30 is located on the first surface 21a of the insulating protective layer 21 and is electrically connected with the conductive pole
23。
In an embodiment, the first end face 23a of the conductive pole 23 is electrically connected with the electronic component 30.
In an embodiment, the electronic packing piece 3,3 ' also includes multiple conducting elements 32, located at the insulating protective layer 21
Second surface 21b on and be electrically connected with the conductive pole 23.
In summary, package substrate of the invention and its electronic packing piece and preparation method, master is used as by the insulating protective layer
Body, avoid using core layer, thus the existing conductive hole through core layer need not be made, can simple fabrication steps and reduce into
This.
In addition, it is of the invention because not having existing core layer, and the thickness of the package substrate can be greatly reduced, therefore in the encapsulation
In the case that the thickness of substrate is minimized, the thickness of overall electronic packing piece can also effectively reduce.
Above-described embodiment is only to the principle and its effect of the illustrative present invention, not for the limitation present invention.Appoint
What those skilled in the art can modify under the spirit and scope without prejudice to the present invention to above-described embodiment.Therefore originally
The rights protection scope of invention, should be as listed by claims.
Claims (28)
1. a kind of package substrate, it is characterised in that the package substrate includes：
Insulating protective layer, it has relative first surface and second surface；
Line layer, its be embedded into the first surface of the insulating protective layer and expose to the first surface and do not expose to this second
Surface；And
Conductive pole, it is penetratingly formed in the insulating protective layer and exposes to the first surface and second surface and be electrically connected with
The line layer.
2. package substrate as claimed in claim 1, it is characterised in that the insulating protective layer is welding resisting layer.
3. package substrate as claimed in claim 1, it is characterised in that the surface of the line layer flushes the of the insulating protective layer
One surface.
4. package substrate as claimed in claim 1, it is characterised in that the conductive pole has relative first end face and the second end
Face, the first end face is set to expose to the first surface, and the second end face exposes to the second surface.
5. package substrate as claimed in claim 4, it is characterised in that the first end face flush the first surface and/or this
Biend flushes the second surface.
6. a kind of preparation method of package substrate, it is characterised in that the preparation method includes：
There is provided one has the insulating protective layer of relative first surface and second surface, wherein, the insulating protective layer is formed with more
Individual perforate and an at least through hole, the perforate are formed on the first surface and do not connect the second surface, and through hole connection should
First surface and second surface；And line layer is formed in the perforate, and conductive pole is formed in the through hole, and make the conduction
Post is electrically connected with the line layer.
7. the preparation method of package substrate as claimed in claim 6, it is characterised in that the insulating protective layer is welding resisting layer.
8. the preparation method of package substrate as claimed in claim 6, it is characterised in that the surface of the line layer flushes the insulation protection
The first surface of layer.
9. the preparation method of package substrate as claimed in claim 6, it is characterised in that the conductive pole have relative first end face and
Second end face, the first end face is set to expose to the first surface, and the second end face exposes to the second surface.
10. the preparation method of package substrate as claimed in claim 9, it is characterised in that the first end face flush the first surface and/
Or the second end face flushes the second surface.
11. the preparation method of package substrate as claimed in claim 6, it is characterised in that the preparation method also includes first by the insulation protection
Layer is bound on a bearing part with its second surface, re-forms the perforate and the through hole.
12. the preparation method of package substrate as claimed in claim 11, it is characterised in that the preparation method is also included in form the line layer
After the conductive pole, the bearing part is removed.
13. a kind of electronic packing piece, it is characterised in that the electronic packing piece includes：
Package substrate as claimed in claim 1；And
Electronic component, it is located on the first surface of the insulating protective layer and is electrically connected with the conductive pole.
14. electronic packing piece as claimed in claim 13, it is characterised in that the insulating protective layer is welding resisting layer.
15. electronic packing piece as claimed in claim 13, it is characterised in that the surface of the line layer flushes the insulating protective layer
First surface.
16. electronic packing piece as claimed in claim 13, it is characterised in that the conductive pole has relative first end face and
Biend, the first end face is set to expose to the first surface, and the second end face exposes to the second surface.
17. electronic packing piece as claimed in claim 16, it is characterised in that the first end face flush the first surface and/or
The second end face flushes the second surface.
18. electronic packing piece as claimed in claim 16, it is characterised in that the first end face of the conductive pole is electrically connected with the electricity
Subcomponent.
19. electronic packing piece as claimed in claim 13, it is characterised in that the electronic packing piece also includes multiple conductive elements
Part, it is located on the second surface of the insulating protective layer and is electrically connected with the conductive pole.
20. electronic packing piece as claimed in claim 13, it is characterised in that the electronic packing piece also includes encapsulated layer, its shape
Into on the first surface of the insulating protective layer to coat the electronic component.
21. a kind of preparation method of electronic packing piece, it is characterised in that the preparation method includes：
One package substrate as claimed in claim 1 is provided；And
Electronic component is set on the first surface of the insulating protective layer, and the electronic component is electrically connected with the conductive pole.
22. the preparation method of electronic packing piece as claimed in claim 21, it is characterised in that the insulating protective layer is welding resisting layer.
23. the preparation method of electronic packing piece as claimed in claim 21, it is characterised in that the surface of the line layer flushes the insulation
The first surface of protective layer.
24. the preparation method of electronic packing piece as claimed in claim 21, it is characterised in that the conductive pole has relative first end
Face and second end face, the first end face is set to expose to the first surface, and the second end face exposes to the second surface.
25. the preparation method of electronic packing piece as claimed in claim 24, it is characterised in that the first end face flushes the first surface
And/or the second end face flushes the second surface.
26. the preparation method of electronic packing piece as claimed in claim 24, it is characterised in that the first end face of the conductive pole electrically connects
Connect the electronic component.
27. the preparation method of electronic packing piece as claimed in claim 21, it is characterised in that the preparation method also includes connecing putting multiple conductions
Element makes the conducting element be electrically connected with the conductive pole on the second surface of the insulating protective layer.
28. the preparation method of electronic packing piece as claimed in claim 21, it is characterised in that the preparation method also include formed encapsulated layer in
To coat the electronic component on the first surface of the insulating protective layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW105118131A TWI607676B (en) | 2016-06-08 | 2016-06-08 | Package substrate and its electronic package and the manufacture thereof |
| TW105118131 | 2016-06-08 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107481991A true CN107481991A (en) | 2017-12-15 |
| CN107481991B CN107481991B (en) | 2020-04-07 |
Family
ID=60594036
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610504135.0A Active CN107481991B (en) | 2016-06-08 | 2016-06-30 | Package substrate, electronic package and manufacturing method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN107481991B (en) |
| TW (1) | TWI607676B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101399246A (en) * | 2007-09-29 | 2009-04-01 | 全懋精密科技股份有限公司 | Package substrate structure and production method thereof |
| KR20090065117A (en) * | 2007-12-17 | 2009-06-22 | 주식회사 심텍 | Ultra-thin semiconductor package substrate, method for manufacturing semiconductor package substrate, and method for manufacturing semiconductor device using same |
| CN101826469A (en) * | 2009-03-04 | 2010-09-08 | 日月光半导体制造股份有限公司 | Coreless packaging substrate and manufacturing method thereof |
| TW201248814A (en) * | 2011-05-24 | 2012-12-01 | Unimicron Technology Corp | Coreless package substrate and method of making same |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| SG46955A1 (en) * | 1995-10-28 | 1998-03-20 | Inst Of Microelectronics | Ic packaging lead frame for reducing chip stress and deformation |
| US20060065958A1 (en) * | 2004-09-29 | 2006-03-30 | Pei-Haw Tsao | Three dimensional package and packaging method for integrated circuits |
| TWI512922B (en) * | 2012-09-26 | 2015-12-11 | Unimicron Technology Corp | Package substrate and method of forming the same |
| TWI533771B (en) * | 2014-07-17 | 2016-05-11 | 矽品精密工業股份有限公司 | Coreless package substrate and fabrication method thereof |
-
2016
- 2016-06-08 TW TW105118131A patent/TWI607676B/en active
- 2016-06-30 CN CN201610504135.0A patent/CN107481991B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101399246A (en) * | 2007-09-29 | 2009-04-01 | 全懋精密科技股份有限公司 | Package substrate structure and production method thereof |
| KR20090065117A (en) * | 2007-12-17 | 2009-06-22 | 주식회사 심텍 | Ultra-thin semiconductor package substrate, method for manufacturing semiconductor package substrate, and method for manufacturing semiconductor device using same |
| CN101826469A (en) * | 2009-03-04 | 2010-09-08 | 日月光半导体制造股份有限公司 | Coreless packaging substrate and manufacturing method thereof |
| TW201248814A (en) * | 2011-05-24 | 2012-12-01 | Unimicron Technology Corp | Coreless package substrate and method of making same |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI607676B (en) | 2017-12-01 |
| TW201743665A (en) | 2017-12-16 |
| CN107481991B (en) | 2020-04-07 |
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