CN107331421A - A kind of SD card test system and method based on FPGA - Google Patents

Abstract

The present invention proposes a FPGA-based SD card testing system. The FPGA internal control circuit includes a clock generation and management module, a PRBS graphic generation module, a sending module, a receiving module, a command control module, a data processing module, a sequence synchronization module and an interface control module. module; the FPGA receives commands from the host computer through the interface control module, and sends the commands or data to the data processing module; the data processing module proceeds to the next step after judging the commands. The sequence synchronization module is not enabled, and the received data is directly sent from the receiving module to the data processing module; when the host computer selects the bit error test, the PRBS pattern generation module and the sequence synchronization module are enabled. The test system and method of the present invention can perform a single command test on the SD card, has high flexibility, and meets the long-time high-speed test requirements.

Description

A FPGA-based SD card testing system and method

technical field

The invention relates to the technical field of testing, in particular to an FPGA-based SD card testing system, and also relates to an FPGA-based SD card testing method.

Background technique

With the advent of the information age, smart phones have become a tool for people to work, communicate, and entertain, accompanied by the emergence of a large number of mobile phone software, which requires higher storage for various mobile devices, and SD (SecUre Digital Memory) Card) cards have been used more and more widely as mass storage.

The performance of the SD card is directly related to the safety and reliability of the ongoing work in people's production and life. On the other hand, due to the thin profit of mobile storage products, manufacturers of authentic products have reduced investment in anti-counterfeiting. These subjective and objective factors have caused the proliferation of fake and inferior flash memory cards and U disks. Therefore, the performance verification and testing of SD cards is particularly important.

At present, there are two main ways to test the SD card, one is to use the circuit module of the SD card controller or the corresponding chip, such as an SD card reader; the second is to directly connect the I/O port to the SD card interface , so as to use software to simulate the timing of the SD card to control its reading and writing. For example, some single-chip microcomputers have a special SD card interface.

The method of using a dedicated SD card control chip increases the complexity of the circuit and increases the design cost. Although direct software testing reduces the cost and complexity, the transmission rate is not high enough to meet high-speed continuous testing.

Contents of the invention

In order to solve the above-mentioned deficiencies in the prior art, the present invention proposes a FPGA-based SD card testing system and method, which can not only test the SD card for reading and writing, but also perform single instruction testing and bit error testing on the SD card.

Technical scheme of the present invention is realized like this:

A FPGA-based SD card testing system, the FPGA internal control circuit includes a clock generation and management module, a PRBS graphic generation module, a sending module, a receiving module, a command control module, a data processing module, a sequence synchronization module and an interface control module;

The FPGA receives commands from the host computer through the interface control module, and sends the commands or data to the data processing module;

The data processing module proceeds to the next step after judging the command. When the normal sending and receiving test and command test are performed, the PRBS graphic generation module and the sequence synchronization module are not enabled, and the received data is directly sent from the receiving module to the data processing module; During the code test, the PRBS pattern generation module and the sequence synchronization module are enabled.

Optionally, the single instruction test of the SD card is divided into two stages: the first stage is an initialization stage, and the second stage is a data transmission stage.

Optionally, the specific process of the initialization phase is as follows:

Step 1: FPGA sends CMD0 command first;

Step 2: FPGA sends CMD8 command and waits for SD card response; if there is no response after timeout, FPGA returns status word 0x01, and proceeds to step 3; if the response is correct, FPGA proceeds to step 3; if the response is wrong, FPGA returns status word 0x02 , to stop the test;

Step 3: The FPGA sends the CMD55+ACMD41 command and waits for the SD card to respond; if there is no response, the FPGA returns the status word 0x03 and stops the test; if the response is busy, the FPGA repeats step 3; if the response is ready, proceed to step 4, and Judge the type of the SD card according to the state word in the state memory;

Step 4: The FPGA sends the CMD2 command and waits for a response; if there is no response, the FPGA returns the status word 0x04 and stops the test; if there is a response, the FPGA stores the response value, which is the CID information of the SD card, and then enters step 5;

Step 5: FPGA sends the CMD3 command and waits for a response; if there is no response, the FPGA returns the status word 0x05 and stops the test; if there is a response, the FPGA stores the response value, which is the relative address of the card, which is needed in the transmission phase. Then go to step 6;

Step 6: After the initialization phase is completed, enter the data transmission phase and wait for the instructions from the host computer.

Optionally, in the data transmission stage, the host computer sends operation instructions completely, and the FPGA control realizes the SD card test;

The host computer operation includes transmission rate selection, SD card mode selection, bit error test and PRBS pattern selection;

The data processing module in the FPGA performs data transmission and state judgment, and the host computer displays the state according to the state word.

Optionally, the clock generation and management module tests the performance of the SD card at different transfer rates;

After setting the transmission rate, the upper computer sends the control word to the lower computer, and the clock generation and management module generates the required clock according to the control word and sends it to the clock pin of the SD card; select the same PRBS sequence at different rates, and go through the same period After a period of time, the transmission performance is judged according to the bit error rate.

The present invention also proposes a method for testing SD cards based on FPGA. The FPGA internal control circuit includes a clock generation and management module, a PRBS graphic generation module, a sending module, a receiving module, a command control module, a data processing module, a sequence synchronization module and an interface. control module;

The FPGA receives commands from the host computer through the interface control module, and sends the commands or data to the data processing module;

The data processing module proceeds to the next step after judging the command. When the normal sending and receiving test and command test are performed, the PRBS graphic generation module and the sequence synchronization module are not enabled, and the received data is directly sent from the receiving module to the data processing module; During the code test, the PRBS pattern generation module and the sequence synchronization module are enabled.

Optionally, the single instruction test of the SD card is divided into two stages: the first stage is an initialization stage, and the second stage is a data transmission stage.

Optionally, the specific process of the initialization phase is as follows:

Step 1: FPGA sends CMD0 command first;

Step 2: FPGA sends CMD8 command and waits for SD card response; if there is no response after timeout, FPGA returns status word 0x01, and proceeds to step 3; if the response is correct, FPGA proceeds to step 3; if the response is wrong, FPGA returns status word 0x02 , to stop the test;

Step 3: The FPGA sends the CMD55+ACMD41 command and waits for the SD card to respond; if there is no response, the FPGA returns the status word 0x03 and stops the test; if the response is busy, the FPGA repeats step 3; if the response is ready, proceed to step 4, and Judge the type of the SD card according to the state word in the state memory;

Step 4: The FPGA sends the CMD2 command and waits for a response; if there is no response, the FPGA returns the status word 0x04 and stops the test; if there is a response, the FPGA stores the response value, which is the CID information of the SD card, and then enters step 5;

Step 5: FPGA sends the CMD3 command and waits for a response; if there is no response, the FPGA returns the status word 0x05 and stops the test; if there is a response, the FPGA stores the response value, which is the relative address of the card, which is needed in the transmission phase. Then go to step 6;

Step 6: After the initialization phase is completed, enter the data transmission phase and wait for the instructions from the host computer.

Optionally, in the data transmission stage, the host computer sends operation instructions completely, and the FPGA control realizes the SD card test;

The host computer operation includes transmission rate selection, SD card mode selection, bit error test and PRBS pattern selection;

The data processing module in the FPGA performs data transmission and state judgment, and the host computer displays the state according to the state word.

Optionally, test the performance of the SD card at different transmission rates through the clock generation and management module; the upper computer sends the control word to the lower computer after setting the transmission rate, and the clock generation and management module generates the required clock according to the control word. To the clock pin of the SD card; select the same PRBS sequence at different rates, and judge the transmission performance according to the bit error rate after the same period of time.

The beneficial effects of the present invention are:

(1) A single instruction test can be performed on the SD card;

(2) The flexibility is high, the SD card can be tested one by one, and it can meet the long-term high-speed test requirements.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is the functional block diagram of a kind of SD card testing system based on FPGA of the present invention;

Fig. 2 is the FPGA internal control circuit structural diagram of the present invention.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The invention relates to a testing system and a testing method of an SD card, which can not only test the reading and writing of the SD card, but also perform a single instruction test and a code error test on the SD card. The present invention uses FPGA instead of special-purpose chip, has high flexibility, satisfies high-speed test, and can carry out single command test on SD card, can also insert pseudo-random sequence during read-write test, and test the bit error rate of the system.

As shown in Figure 1, the SD card testing system of the present invention sends control commands to the SD card through the FPGA, and uploads the received command responses or data to the upper computer for display after analysis. Among them, the hardware part adopts a 3U PCI board structure, and the upper computer operating system is WIN7.

As shown in Figure 2, the FPGA internal control circuit of the present invention mainly includes clock generation and management module, PRBS pattern generation module, sending module, receiving module, command control module, data analysis module, sequence synchronization module and PCI9054 interface control module.

The FPGA receives commands from the host computer through the interface control module, and sends commands or data to the data processing module.

The data processing module proceeds to the next step after judging the command. When the receiving test and command test are sent normally, the PRBS module and the sequence synchronization module are not enabled, and the received data is directly sent from the receiving module to the data processing module; when the upper computer checks the error code When testing the function, the PRBS module and the sequence synchronization module are enabled.

The SD card single command test is mainly divided into two stages: the first stage is the initialization stage, and the second stage is the data transmission stage.

The initialization phase needs to be operated in order, and the specific process is as follows:

Step 1: FPGA sends CMD0 command first.

Step 2: FPGA sends CMD8 command and waits for card response; if there is no response after timeout, return status word 0x01 (if there is no response after timeout, FPGA returns status word 0x01), and proceed to step 3; if the response is correct, proceed to step 3; if response If there is an error, the FPGA will return the status word 0x02 and stop the test;

Step 3: FPGA sends CMD55+ACMD41 command and waits for card response; if there is no response, FPGA returns status word 0x03 and stops testing; if the response is busy, repeat step 3; if the response is ready, proceed to step 4, and The status word judges the type of the card.

Step 4: The FPGA sends the CMD2 command and waits for a response; if there is no response, the FPGA returns the status word 0x04, and the test is stopped; if there is a response, the FPGA stores the response value, which is the CID information of the card, and then enters step 5;

Step 5: FPGA sends CMD3 command and waits for response. If there is no response, the FPGA returns the status word 0x05, and the test is stopped; if there is a response, the FPGA stores the response value, which is the relative address of the card, which is needed in the transmission phase. Then go to step 6.

Step 6: After the initialization phase is completed, enter the data transmission phase and wait for the instructions from the host computer.

In the data transmission stage, the upper computer sends operation instructions completely, and the FPGA controls to realize the SD card test. The host computer operation includes transmission rate selection, SD card mode selection, bit error test and PRBS pattern selection, etc. The FPGA data processing module mainly performs data transmission and state judgment. The host computer displays the state according to the state word, and the corresponding state of the state word is shown in Table 1.

Table 1

The performance of the SD card under different transmission rates is mainly tested through the clock generation and management module. After setting the transmission rate, the upper computer sends the control word to the lower computer, and the clock generation and management module generates the required clock according to the control word and sends it to the clock pin of the SD card. After selecting the same PRBS sequence at different rates for the same period of time, the transmission performance is judged according to the bit error rate.

The concrete steps that test system of the present invention carries out PRBS bit error test are as follows:

Step 1: After the bit error test is enabled, when the FPGA sends the command to write to the SD card, the PRBS sequencer is enabled, and the bit counter and the byte counter work at the same time, and the data is sent to the FIFO for each byte counted;

Step 2: According to the selected SD card mode (single-wire or four-wire), determine the way to send data, and select different parallel-to-serial conversions. The single line is implemented with 8-to-1 FIFO, and the four-line is implemented with 8-to-4 FIFO.

Step 3: Stop the PRBS sequence generator when the byte count reaches 512 (that is, the number of bytes in one BLOCK of the SD card).

Step 4: The FPGA sends the command to read the SD card (the address must be the same as that in the write command), and at the same time start PRBS reception.

Step 5: Send the PRBS reception comparison result (number of bits, number of bit errors) to the host computer through a timing interrupt, and the calculation result of the host computer is displayed.

Note: The above is the bit error test of reading and writing of a single SD card, and the FPGA can send continuous read and write commands during the continuous test.

The present invention also proposes a method for testing an SD card based on FPGA, the working principle of which is the same as that of the above-mentioned testing system, and will not be repeated here.

The invention can perform a single instruction test on the SD card, and can insert a pseudo-random sequence to perform a code error test when sending and receiving data; and can manually control the reading and writing rate of the SD card.

The invention has high flexibility, can test the SD card one by one, and meets the long-time high-speed test requirement; the pseudo-random sequence can be inserted in the data transmission process for error code testing.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included in the scope of the present invention. within the scope of protection.

Claims (10)

1. a kind of SD card test system based on FPGA, it is characterised in that FPGA internal control circuits, which include clock, to be occurred with managing Manage module, PRBS figures and occur module, sending module, receiving module, command control module, data processing module, sequence synchronization Module and interface control module；

FPGA receives the order of host computer by interface control module, and order or data are delivered into data processing module；

Data processing module judges to carry out next step operation after order, when normal transmission receives test and order test, PRBS Module occurs for figure and sequence synchronization module is not enabled, and receives data and is directly sent by receiving module to data processing module； When upper computer selecting error code testing, PRBS figures occur module and enabled with sequence synchronization module.

2. a kind of SD card test system based on FPGA as claimed in claim 1, it is characterised in that

Two stages are divided into the test of SD card individual instructions：First stage is initial phase, and second stage passes for data The defeated stage.

3. a kind of SD card test system based on FPGA as claimed in claim 2, it is characterised in that

The initial phase detailed process is as follows：

Step 1：FPGA first sends CMD0 orders；

Step 2：FPGA sends CMD8 orders, waits SD card response；If without response after time-out, FPGA returns to status word 0x01, and Carry out step 3；If response is correct, FPGA carries out step 3；If responding mistake, FPGA returns to status word 0x02, stops surveying Examination；

Step 3：FPGA sends CMD55+ACMD41 orders and waits SD card response；If without response, FPGA returns to status word 0x03, stops test；If response is busy, FPGA repeat steps 3；If response is ready, step 4, and root are carried out The type of SD card is judged according to status word in status register；

Step 4：FPGA sends CMD2 order wait-for-responses；Without response, then FPGA returns status word 0x04, stops test；There is sound Answer, then FPGA memory responses value, the response is the cid information of SD card, subsequently into step 5；

Step 5：FPGA sends CMD3 order wait-for-responses；Without response, then FPGA returns status word 0x05, stops test；There is phase Answer, then FPGA memory responses value, the response is the relative address of card, needs to use the value in the transmission stage, subsequently into step Rapid 6；

Step 6：Initial phase completes to enter data transfer phase, waits host computer instruction.

4. a kind of SD card test system based on FPGA as claimed in claim 2, it is characterised in that

The data transfer phase sends operational order by host computer completely, and FPGA controls realize that SD card is tested；

Host computer operation includes transmission rate selection, SD card model selection, error code testing and PRBS code selections；

Data processing module in FPGA carries out transmission and the condition adjudgement of data, and host computer is according to status word dispaly state.

5. a kind of SD card test system based on FPGA as claimed in claim 1, it is characterised in that

The clock occurs to test performance of the SD card under different transmission rates with management module；

Host computer sets after transmission rate and to send control word to slave computer, and clock occurs to be produced according to control word with management module Clock required for raw is sent to the clock pins of SD card；Identical PRBS Sequence is selected at different rates, by mutually same Transmission performance is judged according to the bit error rate after the section time.

6. a kind of SD card method of testing based on FPGA, it is characterised in that FPGA internal control circuits, which include clock, to be occurred with managing Manage module, PRBS figures and occur module, sending module, receiving module, command control module, data processing module, sequence synchronization Module and interface control module；

FPGA receives the order of host computer by interface control module, and order or data are delivered into data processing module；

Data processing module judges to carry out next step operation after order, when normal transmission receives test and order test, PRBS Module occurs for figure and sequence synchronization module is not enabled, and receives data and is directly sent by receiving module to data processing module； When upper computer selecting error code testing, PRBS figures occur module and enabled with sequence synchronization module.

7. a kind of SD card method of testing based on FPGA as claimed in claim 6, it is characterised in that

Two stages are divided into the test of SD card individual instructions：First stage is initial phase, and second stage passes for data The defeated stage.

8. a kind of SD card method of testing based on FPGA as claimed in claim 7, it is characterised in that

The initial phase detailed process is as follows：

Step 1：FPGA first sends CMD0 orders；

Step 2：FPGA sends CMD8 orders, waits SD card response；If without response after time-out, FPGA returns to status word 0x01, and Carry out step 3；If response is correct, FPGA carries out step 3；If responding mistake, FPGA returns to status word 0x02, stops surveying Examination；

Step 3：FPGA sends CMD55+ACMD41 orders and waits SD card response；If without response, FPGA returns to status word 0x03, stops test；If response is busy, FPGA repeat steps 3；If response is ready, step 4, and root are carried out The type of SD card is judged according to status word in status register；

Step 4：FPGA sends CMD2 order wait-for-responses；Without response, then FPGA returns status word 0x04, stops test；There is sound Answer, then FPGA memory responses value, the response is the cid information of SD card, subsequently into step 5；

Step 5：FPGA sends CMD3 order wait-for-responses；Without response, then FPGA returns status word 0x05, stops test；There is phase Answer, then FPGA memory responses value, the response is the relative address of card, needs to use the value in the transmission stage, subsequently into step Rapid 6；

Step 6：Initial phase completes to enter data transfer phase, waits host computer instruction.

9. a kind of SD card method of testing based on FPGA as claimed in claim 7, it is characterised in that

The data transfer phase sends operational order by host computer completely, and FPGA controls realize that SD card is tested；

Host computer operation includes transmission rate selection, SD card model selection, error code testing and PRBS code selections；

Data processing module in FPGA carries out transmission and the condition adjudgement of data, and host computer is according to status word dispaly state.

10. a kind of SD card method of testing based on FPGA as claimed in claim 6, it is characterised in that

Occur to test performance of the SD card under different transmission rates with management module by clock；Host computer sets transmission rate Control word is sent to slave computer afterwards, the clock that clock occurs with management module according to required for being produced control word is sent to SD card Clock pins；Identical PRBS Sequence is selected at different rates, and biography is judged according to the bit error rate after phase same amount of time Defeated performance.