CN113434442A - A switch and data access method - Google Patents
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Abstract
本发明实施例提供了一种交换机及数据访问方法,涉及通信技术领域,可以提高CPU访问I2C器件的效率,减少访问I2C器件对CPU的占用。本发明实施例的交换机包括:中央处理器CPU、复杂可编程逻辑器件CPLD芯片和多个集成电路总线I2C器件。CPU通过串行外设接口SPI与CPLD芯片连接;CPLD芯片包括多个I2C模拟接口,每个I2C模拟接口通过两个I/O管脚模拟实现;CPLD芯片包括的每个I2C模拟接口与不同的I2C器件连接。CPU用于通过SPI向CPLD芯片发送访问指令;CPLD芯片用于基于访问指令通过I2C模拟接口对I2C器件进行读写操作。
Embodiments of the present invention provide a switch and a data access method, which relate to the technical field of communications, and can improve the efficiency of CPU accessing I2C devices and reduce the occupation of CPU by accessing I2C devices. The switch in the embodiment of the present invention includes: a central processing unit CPU, a complex programmable logic device CPLD chip, and a plurality of integrated circuit bus I2C devices. The CPU is connected to the CPLD chip through the serial peripheral interface SPI; the CPLD chip includes multiple I2C analog interfaces, and each I2C analog interface is simulated by two I/O pins; each I2C analog interface included in the CPLD chip is different from the I2C device connection. The CPU is used to send an access command to the CPLD chip through the SPI; the CPLD chip is used to read and write the I2C device through the I2C analog interface based on the access command.
Description
技术领域technical field
本发明涉及通信技术领域,特别是涉及一种交换机及数据访问方法。The present invention relates to the technical field of communication, in particular to a switch and a data access method.
背景技术Background technique
交换机单板上的中央处理器(central processing unit,CPU)可以通过集成电路之间(Inter-Integrated Circuit,I2C)总线对单板上包括的带电可擦可编程只读存储器(Electrically Erasable Programmable read only memory,EEPROM)、温感、实时时钟(Real_Time Clock,RTC)、光模块等I2C器件进行访问。I2C是一种低速串行总线,由串行时钟线(Serial Clock line,SCL)和串行数据线(Serial Data,SDA)两根线组成。The central processing unit (CPU) on the single board of the switch can communicate with the electrically erasable programmable read only memory (Electrically Erasable Programmable read only memory) included on the single board through the Inter-Integrated Circuit (I2C) bus. memory, EEPROM), temperature sensor, real-time clock (Real_Time Clock, RTC), optical module and other I2C devices to access. I2C is a low-speed serial bus composed of two lines, a serial clock line (Serial Clock line, SCL) and a serial data line (Serial Data, SDA).
如图1所示,交换机单板上的不同类型的I2C器件可以连接到CPU的不同I2C接口,比如图1中的温感芯片、RTC芯片和EEPROM连接到CPU的I2C1接口;电源和风扇连接到CPU的I2C2接口;模拟开关一端连接业务接口模块0~N,另一端连接到CPU的I2C3接口,其余I2C器件连接到CPU的I2C4接口。As shown in Figure 1, different types of I2C devices on the switch board can be connected to different I2C interfaces of the CPU. For example, the temperature sensor chip, RTC chip and EEPROM in Figure 1 are connected to the I2C1 interface of the CPU; the power supply and fan are connected to The I2C2 interface of the CPU; one end of the analog switch is connected to the service interface modules 0~N, the other end is connected to the I2C3 interface of the CPU, and the other I2C devices are connected to the I2C4 interface of the CPU.
交换机单板上的I2C器件较多,CPU需要每隔一段时间通过I2C总线对这些I2C器件进行一轮访问,因I2C总线的速率较低,CPU访问大量的I2C器件将会占用CPU大量的时间,访问效率较低,且CPU在访问I2C器件时无法进行其他业务。There are many I2C devices on the switch board. The CPU needs to access these I2C devices through the I2C bus every once in a while. Because the speed of the I2C bus is low, the CPU access to a large number of I2C devices will take up a lot of CPU time. The access efficiency is low, and the CPU cannot perform other operations when accessing the I2C device.
发明内容SUMMARY OF THE INVENTION
本发明实施例的目的在于提供一种交换机及数据访问方法,以提高CPU访问I2C器件的效率,减少访问I2C器件对CPU的占用。具体技术方案如下:The purpose of the embodiments of the present invention is to provide a switch and a data access method, so as to improve the efficiency of the CPU accessing the I2C device and reduce the occupation of the CPU by the accessing the I2C device. The specific technical solutions are as follows:
第一方面,本发明实施例提供了一种交换机,包括:中央处理器CPU、复杂可编程逻辑器件CPLD芯片和多个集成电路总线I2C器件;In a first aspect, an embodiment of the present invention provides a switch, including: a central processing unit (CPU), a complex programmable logic device (CPLD) chip, and a plurality of integrated circuit bus I2C devices;
所述CPU通过串行外设接口SPI与所述CPLD芯片连接;所述CPLD芯片包括多个I2C模拟接口,每个I2C模拟接口通过两个I/O管脚模拟实现;所述CPLD芯片包括的每个I2C模拟接口与不同的I2C器件连接;The CPU is connected to the CPLD chip through the serial peripheral interface SPI; the CPLD chip includes a plurality of I2C analog interfaces, and each I2C analog interface is simulated by two I/O pins; the CPLD chip includes Each I2C analog interface is connected to a different I2C device;
所述CPU用于通过所述SPI向所述CPLD芯片发送访问指令;The CPU is used to send an access instruction to the CPLD chip through the SPI;
所述CPLD芯片用于基于所述访问指令通过I2C模拟接口对I2C器件进行读写操作。The CPLD chip is used to perform read and write operations on the I2C device through the I2C analog interface based on the access command.
可选的,所述CPLD芯片的第一I2C模拟接口连接于多个物理地址不同的I2C器件;和/或,Optionally, the first I2C analog interface of the CPLD chip is connected to a plurality of I2C devices with different physical addresses; and/or,
所述CPLD芯片的第二I2C模拟接口连接于模拟开关,所述模拟开关连接于多个物理地址相同的I2C器件,所述模拟开关用于选择开启或关闭与所述模拟开关连接的各I2C器件的访问通道。The second I2C analog interface of the CPLD chip is connected to an analog switch, and the analog switch is connected to a plurality of I2C devices with the same physical address, and the analog switch is used to selectively turn on or off each I2C device connected to the analog switch. access channel.
可选的,所述CPU包括I2C接口,所述CPU通过I2C接口与指定I2C器件连接;或者,Optionally, the CPU includes an I2C interface, and the CPU is connected to a designated I2C device through the I2C interface; or,
所述CPLD芯片的其中一个I2C模拟接口与所述指定I2C器件相连。One of the I2C analog interfaces of the CPLD chip is connected to the designated I2C device.
可选的,所述指定I2C器件包括电源和风扇。Optionally, the designated I2C device includes a power supply and a fan.
第二方面,本发明实施例提供了一种数据访问方法,应用于CPU,所述CPU位于第一方面任一项所述的交换机中,所述方法包括:In a second aspect, an embodiment of the present invention provides a data access method, which is applied to a CPU, where the CPU is located in the switch according to any one of the first aspects, and the method includes:
所述CPU通过SPI向CPLD芯片发送访问指令,所述访问指令包括待访问I2C器件的物理地址和寄存器地址,以使得所述CPLD芯片基于所述访问指令通过I2C模拟接口,对所述待访问I2C器件进行读写操作,得到读写结果;The CPU sends an access instruction to the CPLD chip through the SPI, and the access instruction includes the physical address and the register address of the I2C device to be accessed, so that the CPLD chip uses the I2C analog interface based on the access instruction to access the I2C device to be accessed. The device performs read and write operations to obtain read and write results;
所述CPU通过所述SPI获取所述CPLD芯片对所述待访问I2C器件的读写结果。The CPU obtains, through the SPI, the read and write results of the CPLD chip to the I2C device to be accessed.
可选的,所述访问指令为写入指令,所述写入指令携带待写入数据;Optionally, the access instruction is a write instruction, and the write instruction carries the data to be written;
所述CPU通过所述SPI获取所述CPLD芯片对所述待访问I2C器件的读写结果,包括:The CPU obtains the read and write results of the I2C device to be accessed by the CPLD chip through the SPI, including:
所述CPU通过所述SPI从所述CPLD芯片中获取对所述待写入数据的写入结果,所述写入结果用于表示写入成功或写入失败。The CPU obtains a writing result of the data to be written from the CPLD chip through the SPI, and the writing result is used to indicate that the writing succeeds or the writing fails.
可选的,所述访问指令为读取指令;所述CPU通过所述SPI获取所述CPLD芯片对所述待访问I2C器件的读写结果,包括:Optionally, the access instruction is a read instruction; the CPU obtains, through the SPI, the read and write results of the CPLD chip to the I2C device to be accessed, including:
所述CPU通过所述SPI从所述CPLD芯片中获取待读取数据,所述待读取数据为所述CPLD芯片通过I2C模拟接口从所述待访问I2C器件中,所述寄存器地址对应的寄存器中读取的数据。The CPU obtains the data to be read from the CPLD chip through the SPI, and the data to be read is the register corresponding to the register address from the I2C device to be accessed by the CPLD chip through the I2C analog interface. data read in.
第三方面,本发明实施例提供了一种数据访问方法,应用于CPLD芯片,所述CPLD芯片位于第一方面任一项所述的交换机中,所述方法包括:In a third aspect, an embodiment of the present invention provides a data access method, which is applied to a CPLD chip, where the CPLD chip is located in the switch described in any one of the first aspect, and the method includes:
通过SPI接收CPU发送的访问指令,所述访问指令包括待访问I2C器件的物理地址和寄存器地址;Receive the access instruction sent by the CPU through the SPI, and the access instruction includes the physical address and the register address of the I2C device to be accessed;
基于所述访问指令通过I2C模拟接口,对所述待访问I2C器件进行读写操作,并存储读写结果,以便所述CPU通过所述SPI获取所述CPLD芯片对所述待访问I2C器件的读写结果。Based on the access instruction through the I2C analog interface, read and write operations are performed on the I2C device to be accessed, and the read and write results are stored, so that the CPU can obtain the reading of the I2C device to be accessed by the CPLD chip through the SPI Write the result.
可选的,所述访问指令为写入指令,所述写入指令携带待写入数据;Optionally, the access instruction is a write instruction, and the write instruction carries the data to be written;
所述基于所述访问指令通过I2C模拟接口,对所述待访问I2C器件进行读写操作,并存储读写结果,包括:The read and write operations are performed on the I2C device to be accessed through the I2C analog interface based on the access instruction, and the read and write results are stored, including:
通过所述CPLD芯片的I2C模拟接口,向所述CPLD芯片连接的各I2C器件发送地址信号,所述地址信号包括所述待访问I2C器件的物理地址;Send an address signal to each I2C device connected to the CPLD chip through the I2C analog interface of the CPLD chip, where the address signal includes the physical address of the I2C device to be accessed;
接收待访问I2C器件通过I2C模拟接口向所述CPLD发送的确认消息,所述确认消息为所述待访问I2C器件接收到所述地址信号后,在确认所述地址信号中的物理地址与自身的物理地址相同的情况下发送的;Receive the confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface. The confirmation message is that after the I2C device to be accessed receives the address signal, it confirms the physical address in the address signal and its own address. Sent with the same physical address;
通过与所述待访问I2C器件之间的I2C模拟接口,将所述待写入数据写入所述待访问I2C器件中所述寄存器地址对应的寄存器;Write the data to be written into the register corresponding to the register address in the I2C device to be accessed through the I2C analog interface with the I2C device to be accessed;
通过与所述待访问I2C器件之间的I2C模拟接口,接收所述待访问I2C器件发送的写入响应,并基于所述写入响应存储对所述待写入数据的写入结果,所述写入结果用于表示写入成功或写入失败。Through the I2C analog interface with the I2C device to be accessed, a write response sent by the I2C device to be accessed is received, and the write result of the data to be written is stored based on the write response, and the The write result is used to indicate whether the write succeeded or the write failed.
可选的,所述访问指令为读取指令;所述基于所述访问指令通过I2C模拟接口,对所述待访问I2C器件进行读写操作,并存储读写结果,包括:Optionally, the access instruction is a read instruction; the read and write operations are performed on the I2C device to be accessed through an I2C analog interface based on the access instruction, and the read and write results are stored, including:
通过所述CPLD芯片的I2C模拟接口,向所述CPLD芯片连接的各I2C器件发送地址信号,所述地址信号包括所述待访问I2C器件的物理地址;Send an address signal to each I2C device connected to the CPLD chip through the I2C analog interface of the CPLD chip, where the address signal includes the physical address of the I2C device to be accessed;
接收待访问I2C器件通过I2C模拟接口向所述CPLD发送的确认消息,所述确认消息为所述待访问I2C器件接收到所述地址信号后,在确认所述地址信号中的物理地址与自身的物理地址相同的情况下发送的;Receive the confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface. The confirmation message is that after the I2C device to be accessed receives the address signal, it confirms the physical address in the address signal and its own address. Sent with the same physical address;
通过与所述待访问I2C器件之间的I2C模拟接口,从所述待访问I2C器件中,所述寄存器地址对应的寄存器中读取待读取数据;Through the I2C analog interface with the I2C device to be accessed, the data to be read is read from the register corresponding to the register address of the I2C device to be accessed;
存储所述待读取数据,以便所述CPU通过所述SPI从所述CPLD芯片中获取所述待读取数据。The data to be read is stored, so that the CPU obtains the data to be read from the CPLD chip through the SPI.
可选的,所述方法还包括:Optionally, the method further includes:
若通过SPI总线接收到所述CPU对指定I2C模拟接口的恢复命令,则将所述指定I2C模拟接口的SCL时钟信号连续拉低9次。If a recovery command of the CPU to the designated I2C analog interface is received through the SPI bus, the SCL clock signal of the designated I2C analog interface is continuously pulled down 9 times.
第四方面,本发明实施例提供了一种数据访问装置,应用于CPU,所述CPU位于第一方面所述的交换机中,所述装置包括:In a fourth aspect, an embodiment of the present invention provides a data access device, which is applied to a CPU, where the CPU is located in the switch of the first aspect, and the device includes:
写入模块,用于通过SPI向CPLD芯片发送访问指令,所述访问指令包括待访问I2C器件的物理地址和寄存器地址,以使得所述CPLD芯片基于所述访问指令通过I2C模拟接口,对所述待访问I2C器件进行读写操作,得到读写结果;The writing module is used to send an access instruction to the CPLD chip through the SPI, and the access instruction includes the physical address and the register address of the I2C device to be accessed, so that the CPLD chip is based on the access instruction through the I2C analog interface, to the described access instruction. To access the I2C device to perform read and write operations, and get the read and write results;
获取模块,用于通过所述SPI获取所述CPLD芯片对所述待访问I2C器件的读写结果。an obtaining module, configured to obtain the read and write results of the CPLD chip on the to-be-accessed I2C device through the SPI.
可选的,所述访问指令为写入指令,所述写入指令携带待写入数据;所述获取模块,具体用于:Optionally, the access instruction is a write instruction, and the write instruction carries data to be written; the acquisition module is specifically used for:
通过所述SPI从所述CPLD芯片中获取对所述待写入数据的写入结果,所述写入结果用于表示写入成功或写入失败。The writing result of the data to be written is obtained from the CPLD chip through the SPI, and the writing result is used to indicate that the writing succeeds or the writing fails.
可选的,所述访问指令为读取指令;所述获取模块,具体用于:Optionally, the access instruction is a read instruction; the acquisition module is specifically used for:
通过所述SPI从所述CPLD芯片中获取待读取数据,所述待读取数据为所述CPLD芯片通过I2C模拟接口从所述待访问I2C器件中,所述寄存器地址对应的寄存器中读取的数据。The data to be read is obtained from the CPLD chip through the SPI, and the data to be read is read by the CPLD chip from the I2C device to be accessed through the I2C analog interface, and from the register corresponding to the register address The data.
第五方面,本发明实施例提供了一种数据访问装置,应用于CPLD芯片,所述CPLD芯片位于第一方面所述的交换机中,所述装置包括:In a fifth aspect, an embodiment of the present invention provides a data access device, which is applied to a CPLD chip, where the CPLD chip is located in the switch described in the first aspect, and the device includes:
接收模块,用于通过SPI接收CPU发送的访问指令,所述访问指令包括待访问I2C器件的物理地址和寄存器地址;The receiving module is used to receive the access instruction sent by the CPU through the SPI, and the access instruction includes the physical address and the register address of the I2C device to be accessed;
访问模块,用于基于所述访问指令通过I2C模拟接口,对所述待访问I2C器件进行读写操作,并存储读写结果,以便所述CPU通过所述SPI获取所述CPLD芯片对所述待访问I2C器件的读写结果。The access module is used to perform read and write operations on the I2C device to be accessed through the I2C analog interface based on the access instruction, and store the read and write results, so that the CPU obtains the information on the to-be-accessed I2C device through the SPI. Access the read and write results of the I2C device.
可选的,所述访问指令为写入指令,所述写入指令携带待写入数据;Optionally, the access instruction is a write instruction, and the write instruction carries the data to be written;
所述访问模块,具体用于:The access module is specifically used for:
通过所述CPLD芯片的I2C模拟接口,向所述CPLD芯片连接的各I2C器件发送地址信号,所述地址信号包括所述待访问I2C器件的物理地址;Send an address signal to each I2C device connected to the CPLD chip through the I2C analog interface of the CPLD chip, where the address signal includes the physical address of the I2C device to be accessed;
接收待访问I2C器件通过I2C模拟接口向所述CPLD发送的确认消息,所述确认消息为所述待访问I2C器件接收到所述地址信号后,在确认所述地址信号中的物理地址与自身的物理地址相同的情况下发送的;Receive the confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface. The confirmation message is that after the I2C device to be accessed receives the address signal, it confirms the physical address in the address signal and its own address. Sent with the same physical address;
通过与所述待访问I2C器件之间的I2C模拟接口,将所述待写入数据写入所述待访问I2C器件中所述寄存器地址对应的寄存器;Write the data to be written into the register corresponding to the register address in the I2C device to be accessed through the I2C analog interface with the I2C device to be accessed;
通过与所述待访问I2C器件之间的I2C模拟接口,接收所述待访问I2C器件发送的写入响应,并基于所述写入响应存储对所述待写入数据的写入结果,所述写入结果用于表示写入成功或写入失败。Through the I2C analog interface with the I2C device to be accessed, a write response sent by the I2C device to be accessed is received, and the write result of the data to be written is stored based on the write response, and the The write result is used to indicate whether the write succeeded or the write failed.
可选的,所述访问指令为读取指令;Optionally, the access instruction is a read instruction;
所述访问模块,具体用于:The access module is specifically used for:
通过所述CPLD芯片的I2C模拟接口,向所述CPLD芯片连接的各I2C器件发送地址信号,所述地址信号包括所述待访问I2C器件的物理地址;Send an address signal to each I2C device connected to the CPLD chip through the I2C analog interface of the CPLD chip, where the address signal includes the physical address of the I2C device to be accessed;
接收待访问I2C器件通过I2C模拟接口向所述CPLD发送的确认消息,所述确认消息为所述待访问I2C器件接收到所述地址信号后,在确认所述地址信号中的物理地址与自身的物理地址相同的情况下发送的;Receive the confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface. The confirmation message is that after the I2C device to be accessed receives the address signal, it confirms the physical address in the address signal and its own address. Sent with the same physical address;
通过与所述待访问I2C器件之间的I2C模拟接口,从所述待访问I2C器件中,所述寄存器地址对应的寄存器中读取待读取数据;Through the I2C analog interface with the I2C device to be accessed, the data to be read is read from the register corresponding to the register address of the I2C device to be accessed;
存储所述待读取数据,以便所述CPU通过所述SPI从所述CPLD芯片中获取所述待读取数据。The data to be read is stored, so that the CPU obtains the data to be read from the CPLD chip through the SPI.
可选的,所述装置还包括:拉低模块;Optionally, the device further includes: a pull-down module;
所述拉低模块,用于若通过SPI总线接收到所述CPU对指定I2C模拟接口的恢复命令,则将所述指定I2C模拟接口的SCL时钟信号连续拉低9次。The pull-down module is configured to continuously pull down the SCL clock signal of the designated I2C analog interface 9 times if the CPU receives a recovery command of the designated I2C analog interface through the SPI bus.
本发明实施例提供的交换机及数据访问方法,CPU与CPLD芯片通过SPI连接,CPLD芯片能够通过I2C模拟接口连接I2C器件。CPU在需要访问I2C器件时,通过SPI向CPLD芯片发送访问指令,由CPLD芯片基于访问指令对I2C器件进行读写操作。由于访问I2C器件的过程由CPLD执行,CPU只需要通过SPI向CPLD芯片发送访问指令,同时SPI的速率比I2C总线速率高,因此减少了访问I2C器件对CPU的占用,提高了访问效率。In the switch and the data access method provided by the embodiments of the present invention, the CPU and the CPLD chip are connected through SPI, and the CPLD chip can be connected to the I2C device through the I2C analog interface. When the CPU needs to access the I2C device, it sends an access command to the CPLD chip through the SPI, and the CPLD chip reads and writes the I2C device based on the access command. Since the process of accessing the I2C device is performed by the CPLD, the CPU only needs to send the access command to the CPLD chip through the SPI, and the speed of the SPI is higher than the speed of the I2C bus, thus reducing the occupation of the CPU when accessing the I2C device and improving the access efficiency.
当然,实施本发明的任一产品或方法并不一定需要同时达到以上所述的所有优点。Of course, it is not necessary for any product or method of the present invention to achieve all of the advantages described above at the same time.
附图说明Description of drawings
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,还可以根据这些附图获得其他的实施例。In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention, and for those of ordinary skill in the art, other embodiments can also be obtained according to these drawings.
图1为相关技术中的交换机的结构示意图;1 is a schematic structural diagram of a switch in the related art;
图2为本发明实施例提供的一种交换机的结构示意图;FIG. 2 is a schematic structural diagram of a switch according to an embodiment of the present invention;
图3为本发明实施例提供的一种数据访问方法流程图;3 is a flowchart of a data access method provided by an embodiment of the present invention;
图4为本发明实施例提供的另一种数据访问方法流程图;4 is a flowchart of another data access method provided by an embodiment of the present invention;
图5为本发明实施例提供的一种数据写入方法流程图;5 is a flowchart of a data writing method provided by an embodiment of the present invention;
图6为本发明实施例提供的一种数据读取方法流程图;6 is a flowchart of a data reading method provided by an embodiment of the present invention;
图7为本发明实施例提供的一种数据访问装置的结构示意图;7 is a schematic structural diagram of a data access device according to an embodiment of the present invention;
图8为本发明实施例提供的另一种数据访问装置的结构示意图。FIG. 8 is a schematic structural diagram of another data access apparatus according to an embodiment of the present invention.
具体实施方式Detailed ways
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员基于本申请所获得的所有其他实施例,都属于本发明保护的范围。The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art based on the present application fall within the protection scope of the present invention.
为了提高中央处理器(central processing unit,CPU)访问集成电路总线(Inter-Integrated Circuit,I2C)器件的效率,减少访问I2C器件对CPU的占用,本发明实施例提供了一种交换机,其中,交换机可以是盒式交换机或者框式交换机等,本发明实施例对此不作具体限定。In order to improve the efficiency of a central processing unit (CPU) accessing an integrated circuit bus (Inter-Integrated Circuit, I2C) device and reduce the occupation of the CPU by accessing the I2C device, an embodiment of the present invention provides a switch, wherein the switch It may be a box-type switch or a frame-type switch, etc., which is not specifically limited in this embodiment of the present invention.
如图2所示,本发明实施例提供的交换机包括:CPU 201、CPLD(ComplexProgrammable logic device,复杂可编程逻辑器件)芯片202和多个I2C器件。As shown in FIG. 2 , the switch provided by the embodiment of the present invention includes: a
CPU 201通过串行外设接口(Serial Peripheral Interface,SPI)与CPLD芯片202连接;CPLD芯片202包括多个I2C模拟接口,每个I2C模拟接口通过两个输入/输出(Input/Output,I/O)管脚模拟实现;CPLD芯片202包括的每个I2C模拟接口与不同的I2C器件连接。其中,CPLD芯片202包括一定的存储空间,可以将CPLD芯片202的部分存储空间用作CPLD芯片202的逻辑寄存器,逻辑寄存器能够存储CPU201发送的访问指令,还能够存储对待访问I2C器件的读写结果。The
CPU 201用于通过SPI向CPLD芯片202发送访问指令;CPLD芯片202用于基于访问指令通过I2C模拟接口对I2C器件进行读写操作。The
在本发明实施例中,可以根据实际需求设置CPLD芯片202的I2C模拟接口与I2C器件之间的连接关系。In the embodiment of the present invention, the connection relationship between the I2C analog interface of the
例如,在I2C器件较少的情况下,CPLD芯片202的每个I2C模拟接口可以连接一个I2C器件。For example, in the case of few I2C devices, each I2C analog interface of the
在I2C器件较多的情况下,CPLD芯片202的每个I2C模拟接口可以连接多个I2C器件。一种实施方式中,可以对I2C器件进行分类,分类依据可以为I2C器件的重要程度,比如,可以将交换机内部的I2C器件分为两类,一类为重要I2C器件,另一类为非重要I2C器件,然后将交换机外接的I2C器件(比如业务口光模块)作为一类。相应地,CPLD芯片202的一个I2C模拟接口连接重要I2C器件,另一个I2C模拟接口连接非重要I2C器件,又一个I2C模拟接口通过模拟开关连接多个业务口光模块。或者,将交换机内部的I2C器件作为一类I2C器件,将交换机外接的I2C器件作为另一类I2C器件。相应地,CPLD芯片202的一个I2C模拟接口连接交换机内部的I2C器件,另一个I2C模拟接口通过模拟开关连接交换机外接的I2C器件。本申请实施例对I2C器件的分类方式不作限定,可以根据实际需求设置每个I2C模拟接口连接的I2C器件。When there are many I2C devices, each I2C analog interface of the
例如,图2中的温感芯片、RTC芯片和EEPROM为一类I2C器件,共同连接CPLD芯片202的I2C2模拟接口。图2中的业务口光模块0~N为外接模块,业务口光模块0~N为一类I2C器件,共同通过模拟开关连接CPLD芯片202的I2C3模拟接口。For example, the temperature sensing chip, the RTC chip and the EEPROM in FIG. 2 are a type of I2C device, and are jointly connected to the I2C2 analog interface of the
CPLD芯片202包括多个I/O管脚,对于CPLD芯片202的部分I/O管脚,可以通过逻辑代码在CPLD芯片202的两个I/O管脚分别模拟I2C接口传输的SCL信号和SDA信号,从而将两个I/O管脚模拟为一个I2C接口。本发明实施例通过CPLD芯片的部分I/O管脚实现模拟I2C接口的功能,由于CPLD芯片本身具有多个I/O管脚,因此本发明实施例未增加CPLD芯片的硬件成本。The
本发明实施例提供的交换机,CPU与CPLD芯片通过SPI连接,CPLD芯片能够通过I2C模拟接口连接I2C器件。CPU在需要访问I2C器件时,通过SPI向CPLD芯片发送访问指令,由CPLD芯片基于访问指令对I2C器件进行读写操作。由于访问I2C器件的过程由CPLD执行,CPU只需要通过SPI向CPLD芯片发送访问指令,同时SPI的速率比I2C总线速率高,因此减少了访问I2C器件对CPU的占用,提高了访问效率。In the switch provided by the embodiment of the present invention, the CPU and the CPLD chip are connected through SPI, and the CPLD chip can be connected to the I2C device through the I2C analog interface. When the CPU needs to access the I2C device, it sends an access command to the CPLD chip through the SPI, and the CPLD chip reads and writes the I2C device based on the access command. Since the process of accessing the I2C device is performed by the CPLD, the CPU only needs to send the access command to the CPLD chip through the SPI, and the speed of the SPI is higher than the speed of the I2C bus, thus reducing the occupation of the CPU when accessing the I2C device and improving the access efficiency.
示例性的,在I2C接口之间传输数据的I2C总线的速率一般在100千赫兹(kiloHertz,kHz)以下,而在SPI接口之间传输数据的SPI总线的速率一般在2兆赫兹(MegaHertz,MHz)以上,因此SPI的速率远高于I2C总线的速率。Exemplarily, the rate of the I2C bus that transmits data between the I2C interfaces is generally below 100 kilohertz (kiloHertz, kHz), while the rate of the SPI bus that transmits data between the SPI interfaces is generally 2 megahertz (MegaHertz, MHz). ) above, so the rate of SPI is much higher than that of the I2C bus.
在本发明实施例中,CPLD芯片202的第一I2C模拟接口连接于多个物理地址不同的I2C器件;和/或,CPLD芯片202的第二I2C模拟接口连接于模拟开关,模拟开关连接于多个物理地址相同的I2C器件。其中,模拟开关用于选择开启或关闭与模拟开关连接的各I2C器件的访问通道。In this embodiment of the present invention, the first I2C analog interface of the
可选的,CPLD芯片202的第一I2C模拟接口可以连接一个I2C器件。Optionally, the first I2C analog interface of the
其中,第一I2C模拟接口中的“第一”和第二I2C模拟接口中的“第二”,仅用于区分连接不同器件的I2C模拟接口,不用于限制I2C模拟接口本身的性质。Among them, the "first" in the first I2C analog interface and the "second" in the second I2C analog interface are only used to distinguish the I2C analog interfaces connecting different devices, and are not used to limit the nature of the I2C analog interface itself.
例如,如图2所示,CPLD芯片202的I2C2模拟接口与温感芯片、EEPROM和RTC芯片相连。其中,温感芯片、EEPROM、RTC芯片为一类I2C器件,且物理地址互不相同。For example, as shown in FIG. 2 , the I2C2 analog interface of the
可选的,因业务口光模块的物理地址通常相同,可以将每个业务口光模块连接于CPLD芯片202的一个I2C模拟接口。或者,如图2所示,可以将业务口光模块0~N通过模拟开关与CPLD芯片202的I2C3模拟接口连接。通过模拟开关选择不同访问通道使得CPLD芯片202访问不同的业务口光模块。其中,模拟开关基于CPLD芯片202的控制信号选择不同的访问通道。Optionally, because the physical addresses of the service port optical modules are generally the same, each service port optical module may be connected to an I2C analog interface of the
在本发明实施例中,CPU 201包括I2C接口,CPU 201通过I2C接口与指定I2C器件连接;或者,CPLD芯片202的其中一个I2C模拟接口与指定I2C器件相连。In the embodiment of the present invention, the
可选的,指定I2C器件包括电源和风扇。Optionally, specified I2C devices include power supplies and fans.
例如,如图2所示,电源和风扇连接到CPU 201的I2C1接口。For example, as shown in Figure 2, the power supply and fan are connected to the I2C1 interface of
由于CPU一般带有I2C接口,因此将较为重要的I2C器件直接与CPU的I2C接口连接,可以提高CPU访问这些较为重要的I2C器件的可靠性。Since the CPU generally has an I2C interface, directly connecting the more important I2C devices to the I2C interface of the CPU can improve the reliability of the CPU accessing these more important I2C devices.
可选的,除了电源、风扇、温感芯片、EEPROM、RTC芯片和业务口光模块以外,还可能存在其他I2C器件,比如电源监控模块、时钟锁相环等。Optionally, in addition to the power supply, fan, temperature sensor chip, EEPROM, RTC chip, and service port optical module, there may also be other I2C devices, such as a power monitoring module, a clock phase-locked loop, and so on.
例如,如图2所示,其他I2C器件可以与CPLD芯片202的I2C4模拟接口连接。For example, as shown in FIG. 2, other I2C devices may be connected to the I2C4 analog interface of
本发明实施例可以将交换机中所有的I2C器件连接于CPLD芯片,以尽可能减少访问I2C器件对于CPU资源的占用,以防止CPU因被I2C接口占用而无法进行其他操作。In the embodiment of the present invention, all I2C devices in the switch can be connected to the CPLD chip, so as to reduce the occupation of CPU resources by accessing the I2C devices as much as possible, so as to prevent the CPU from being unable to perform other operations due to being occupied by the I2C interface.
同时,由于相关技术中,所有的I2C器件直接连接CPU的I2C接口,为了对I2C器件进行分类管理,将每一类I2C器件连接一个I2C接口,使得CPU需要具备大量的I2C接口,这对于交换机中CPU的选型具有一定的限制,增加了CPU的成本。At the same time, in the related art, all I2C devices are directly connected to the I2C interface of the CPU. In order to classify and manage the I2C devices, each type of I2C device is connected to an I2C interface, so that the CPU needs to have a large number of I2C interfaces. The selection of the CPU has certain restrictions, which increases the cost of the CPU.
而本发明实施例可以选择部分I2C器件直接连接CPU的I2C接口,或者设置交换机中所有的I2C器件连接CPLD芯片而不连接CPU,如此,就可以选用I2C接口较少的CPU,因此减少了对于交换机中CPU选型的限制,降低了CPU的成本。In the embodiment of the present invention, some I2C devices can be directly connected to the I2C interface of the CPU, or all I2C devices in the switch can be set to be connected to the CPLD chip instead of the CPU. In this way, the CPU with fewer I2C interfaces can be selected, thus reducing the need for the switch. The CPU selection limit reduces the cost of the CPU.
另外,相关技术中,通过高速串行计算机扩展总线标准(Peripheral ComponentInterconnect Express,PCIE)接口或者通用串行总线(Universal Serial Bus,USB)接口模拟I2C接口,这些方案均需要在CPU和I2C器件所在的交换机单板中增加额外的芯片,增加了交换机的硬件成本。In addition, in the related art, the I2C interface is simulated through a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) interface or a Universal Serial Bus (Universal Serial Bus, USB) interface, and these solutions all need to be in the CPU and the I2C device. Additional chips are added to the switch board, which increases the hardware cost of the switch.
而CPU和I2C器件所在的交换机单板中一般包含了CPLD芯片,本发明实施例利用交换机单板自带的CPLD芯片实现SPI协议转I2C协议的功能,同时交换机单板自带的CPLD芯片一般都能实现该功能,因此本发明实施例对交换机单板上的CPLD芯片的选型没有额外的限制,没有增加额外的硬件成本。The switch board where the CPU and I2C devices are located generally includes a CPLD chip. In the embodiment of the present invention, the CPLD chip provided on the switch board is used to realize the function of converting the SPI protocol to the I2C protocol. This function can be implemented, so the embodiment of the present invention has no additional restrictions on the selection of the CPLD chip on the switch board, and does not increase additional hardware costs.
常规的交换机结构如图1所示,温感芯片、RTC芯片和EEPROM连接到CPU的I2C1接口;电源和风扇连接到CPU的I2C2接口;模拟开关一端连接业务接口模块0~N,另一端连接到CPU的I2C3接口,其他I2C器件连接到CPU的I2C4接口。其中,连接同一个I2C接口的I2C器件通过不同的物理地址区分,若连接同一个I2C接口的I2C器件的物理地址相同,则由模拟开关选通不同的通道进行区分。The conventional switch structure is shown in Figure 1. The temperature sensor chip, RTC chip and EEPROM are connected to the I2C1 interface of the CPU; the power supply and fan are connected to the I2C2 interface of the CPU; one end of the analog switch is connected to the service interface modules 0~N, and the other end is connected to the I2C2 interface of the CPU. The I2C3 interface of the CPU, other I2C devices are connected to the I2C4 interface of the CPU. Among them, the I2C devices connected to the same I2C interface are distinguished by different physical addresses. If the physical addresses of the I2C devices connected to the same I2C interface are the same, different channels are selected by the analog switch to distinguish.
CPU需要访问一个I2C器件时,CPU通过各I2C接口向CPU连接的所有I2C器件发送地址信号,其中地址信号包括需要访问的I2C器件的物理地址。每个I2C器件接收到地址信号后,如果地址信号包括的物理地址与自身物理地址相同,则向CPU反馈确认字符(Acknowledge character,ACK)信号,以告知CPU可以进行进一步操作。CPU接收到ACK信号后,从发送ACK信号的I2C器件中读取数据,或者向发送ACK信号的I2C器件写入数据。When the CPU needs to access an I2C device, the CPU sends an address signal to all the I2C devices connected to the CPU through each I2C interface, where the address signal includes the physical address of the I2C device to be accessed. After each I2C device receives the address signal, if the physical address included in the address signal is the same as its own physical address, it feeds back an Acknowledge character (ACK) signal to the CPU to inform the CPU that further operations can be performed. After the CPU receives the ACK signal, it reads data from the I2C device that sends the ACK signal, or writes data to the I2C device that sends the ACK signal.
其中,如果CPU的一个I2C接口上连接了多个物理地址相同的I2C器件,或者CPU的一个I2C接口上连接的I2C器件的负载电容超过I2C协议支持的最高电容(400pF,其中pF表示皮法),则通过CPLD芯片控制模拟开关打开相应的通道,从而使得CPU访问相应的I2C器件。Among them, if multiple I2C devices with the same physical address are connected to one I2C interface of the CPU, or the load capacitance of the I2C device connected to one I2C interface of the CPU exceeds the maximum capacitance supported by the I2C protocol (400pF, where pF means picofarads) , then control the analog switch to open the corresponding channel through the CPLD chip, so that the CPU can access the corresponding I2C device.
CPU除了常规的访问I2C器件以外,还需要每隔一段时间在一些I2C器件中完成一次读写操作,即轮询一些I2C器件。由于CPU通过I2C接口访问I2C器件,而I2C接口的速率低,即CPU发送地址信号、接收ACK消息以及向I2C器件读取或写入数据的速度慢,大量地占用CPU的时间和资源,导致CPU难以处理其他业务。In addition to regular access to I2C devices, the CPU also needs to complete a read and write operation in some I2C devices at regular intervals, that is, poll some I2C devices. Because the CPU accesses the I2C device through the I2C interface, and the rate of the I2C interface is low, that is, the CPU sends address signals, receives ACK messages, and reads or writes data to the I2C device. Difficulty handling other business.
为了提高CPU的访问效率,减少访问I2C器件对CPU资源的占用。本发明实施例提供了一种数据访问方法,应用于CPU,该CPU位于上述图2所示的交换机中,如图3所示,该方法包括如下步骤:In order to improve the access efficiency of the CPU, reduce the occupation of CPU resources by accessing the I2C device. An embodiment of the present invention provides a data access method, which is applied to a CPU, where the CPU is located in the switch shown in FIG. 2 . As shown in FIG. 3 , the method includes the following steps:
S301,CPU通过SPI向CPLD芯片发送访问指令。S301, the CPU sends an access instruction to the CPLD chip through the SPI.
其中,访问指令包括待访问I2C器件的物理地址和寄存器地址,以使得CPLD芯片基于访问指令通过I2C模拟接口,对待访问I2C器件进行读写操作,得到读写结果。The access instruction includes the physical address and register address of the I2C device to be accessed, so that the CPLD chip can read and write the I2C device to be accessed through the I2C analog interface based on the access instruction, and obtain the read and write results.
在本发明实施例中,CPLD芯片具有一定的存储空间,可以将CPLD芯片的部分存储空间用作CPLD芯片的逻辑寄存器。CPU可通过CPLD芯片的内部逻辑代码的状态机,访问CPLD芯片的逻辑寄存器,以向CPLD芯片发送访问指令。In the embodiment of the present invention, the CPLD chip has a certain storage space, and part of the storage space of the CPLD chip can be used as a logic register of the CPLD chip. The CPU can access the logic registers of the CPLD chip through the state machine of the internal logic code of the CPLD chip, so as to send an access instruction to the CPLD chip.
S302,CPU通过SPI获取CPLD芯片对待访问I2C器件的读写结果。S302, the CPU obtains the read and write results of the CPLD chip to be accessed to the I2C device through the SPI.
本发明实施例提供的数据访问方法,CPU与CPLD芯片通过SPI连接,CPLD芯片通过I2C模拟接口连接I2C器件。CPU在需要访问I2C器件时,通过SPI向CPLD芯片发送访问指令,由CPLD芯片基于访问指令对I2C器件进行读写操作。由于访问I2C器件的过程由CPLD芯片执行,CPU只需要向CPLD芯片发送访问指令,在CPLD芯片对I2C器件进行读写操作时,CPU可以处理其他业务。且因SPI的速率比I2C总线速率高,所以CPU通过SPI从CPLD芯片中获取对待访问I2C器件的读写结果,相比于现有技术中CPU通过I2C接口访问I2C器件,可以减少访问I2C器件对CPU时间的占用,提高了数据访问效率,增加了CPU用于处理其他业务的时间。In the data access method provided by the embodiment of the present invention, the CPU and the CPLD chip are connected through SPI, and the CPLD chip is connected to the I2C device through an I2C analog interface. When the CPU needs to access the I2C device, it sends an access command to the CPLD chip through the SPI, and the CPLD chip reads and writes the I2C device based on the access command. Since the process of accessing the I2C device is performed by the CPLD chip, the CPU only needs to send an access command to the CPLD chip. When the CPLD chip reads and writes the I2C device, the CPU can process other services. And because the speed of SPI is higher than the speed of I2C bus, the CPU obtains the read and write results of the I2C device to be accessed from the CPLD chip through SPI. Compared with the prior art, the CPU accesses the I2C device through the I2C interface, which can reduce the access to the I2C device. The occupation of CPU time improves the data access efficiency and increases the CPU time for processing other services.
在本发明实施例中,CPU可以通过CPLD芯片向I2C器件写入数据,此时上述访问指令为写入指令,写入指令携带待写入数据。In the embodiment of the present invention, the CPU can write data to the I2C device through the CPLD chip, and at this time, the above-mentioned access command is a write command, and the write command carries the data to be written.
基于此,上述S302中CPU通过SPI获取CPLD芯片对待访问I2C器件的读写结果的方式可以实现为:CPU通过SPI从CPLD芯片中获取对待写入数据的写入结果。其中,写入结果用于表示写入成功或写入失败。可选地,当写入结果为写入失败时,写入结果还可以包括写入失败的原因。Based on this, the manner in which the CPU obtains the read and write results of the I2C device to be accessed by the CPLD chip through the SPI in the above S302 can be implemented as follows: the CPU obtains the write result of the data to be written from the CPLD chip through the SPI. Among them, the writing result is used to indicate that the writing succeeds or the writing fails. Optionally, when the writing result is a writing failure, the writing result may further include a reason for the writing failure.
本发明实施例中,CPLD芯片向I2C器件写入待写入数据后,如果在指定时长内接收到I2C器件反馈的ACK消息,则确定写入成功;或者,如果CPLD芯片在向I2C器件写入待写入数据后的指定时长内,未收到I2C器件反馈的ACK消息,则确定写入失败。In the embodiment of the present invention, after the CPLD chip writes the data to be written to the I2C device, if the ACK message fed back by the I2C device is received within a specified time period, it is determined that the writing is successful; or, if the CPLD chip is writing to the I2C device If no ACK message is received from the I2C device within a specified period of time after the data is to be written, it is determined that the write fails.
CPLD芯片在接收到用于表示写入成功的ACK消息后,存储用于表示写入成功的写入结果。CPLD芯片在向I2C器件写入待写入数据后的指定时长内,如果没有接收到用于表示写入成功的ACK消息,则存储用于表示写入失败的写入结果。以便CPU从CPLD芯片中获取写入结果,提高数据写入的可靠性。After the CPLD chip receives the ACK message indicating that the writing is successful, it stores the writing result indicating that the writing is successful. If the CPLD chip does not receive an ACK message indicating that the writing is successful within a specified period of time after writing the data to be written to the I2C device, it will store the writing result indicating that the writing has failed. In order for the CPU to obtain the writing result from the CPLD chip, the reliability of data writing is improved.
本发明实施例中的CPU需要向I2C器件的寄存器中写入数据时,可以向CPLD芯片发送写入指令,由CPLD芯片完成数据写入工作,在CPLD进行数据写入的过程中,CPU可以处理其他业务。因CPU与CPLD芯片之间通过SPI通信,SPI的数据传输速度远高于I2C的传输速度,相比于CPU直接通过I2C接口向I2C器件写入数据,本发明实施例可以提高CPU的数据写入速度,避免CPU因为向I2C器件写入数据而无法处理其他业务的情况。When the CPU in the embodiment of the present invention needs to write data into the register of the I2C device, it can send a write instruction to the CPLD chip, and the CPLD chip completes the data writing work. During the data writing process of the CPLD, the CPU can process Other business. Because the communication between the CPU and the CPLD chip is through SPI, the data transmission speed of SPI is much higher than the transmission speed of I2C. Compared with the CPU directly writing data to the I2C device through the I2C interface, the embodiment of the present invention can improve the data writing of the CPU. speed, to avoid the situation that the CPU cannot process other services because of writing data to the I2C device.
在本发明实施例中,CPU可以通过CPLD芯片从I2C器件读取数据,此时上述访问指令为读取指令,上述S302中CPU通过SPI获取CPLD芯片对待访问I2C器件的读写结果的方式可以实现为:CPU通过SPI从CPLD芯片中获取待读取数据。其中,待读取数据为CPLD芯片通过I2C模拟接口从待访问I2C器件中,寄存器地址对应的寄存器中读取的数据。In the embodiment of the present invention, the CPU can read data from the I2C device through the CPLD chip. At this time, the above access command is a read command. In the above S302, the CPU obtains the read and write results of the CPLD chip to be accessed from the I2C device through the SPI. It is: the CPU obtains the data to be read from the CPLD chip through SPI. The data to be read is the data read by the CPLD chip from the register corresponding to the register address of the I2C device to be accessed through the I2C analog interface.
待读取数据属于CPLD芯片对待访问I2C器件的读取结果。读取结果用于表示读取成功或读取失败,当读取结果为读取成功时,该读取结果中包括CPLD芯片读取出的待读取数据。当读取结果为读取失败时,该读取结果还包括失败原因。The data to be read belongs to the read result of the CPLD chip to be accessed to the I2C device. The read result is used to indicate that the read is successful or the read fails. When the read result is that the read is successful, the read result includes the data to be read read by the CPLD chip. When the read result is a read failure, the read result further includes a failure reason.
本发明实施例中,如果CPLD芯片能够从I2C器件中读取到待读取数据,则确定读取成功,CPLD芯片可以存储读取结果,此时该读取结果用于表示读取成功,且该读取结果包括待读取数据。或者,如果CPLD芯片无法从I2C器件中读取到待读取数据数据,即在向I2C器件发送读取信号后,若指定时长内未接收到I2C信号反馈的ACK消息,则确定读取失败,CPLD芯片可以存储读取结果,此时该读取结果用于表示读取失败。In the embodiment of the present invention, if the CPLD chip can read the data to be read from the I2C device, it is determined that the reading is successful, and the CPLD chip can store the reading result. At this time, the reading result is used to indicate that the reading is successful, and The read result includes data to be read. Or, if the CPLD chip cannot read the data to be read from the I2C device, that is, after sending the read signal to the I2C device, if the ACK message fed back by the I2C signal is not received within the specified time period, it is determined that the reading fails. The CPLD chip can store the read result, and at this time, the read result is used to indicate that the read fails.
相应地,CPU可以通过SPI从CLPD芯片中获取读取结果。Correspondingly, the CPU can obtain the read result from the CLPD chip through SPI.
本发明实施例中的CPU需要从I2C器件的寄存器中读取数据时,可以向CPLD芯片发送读取指令,由CPLD芯片完成数据读取工作,此时CPU可以处理其他业务。因CPU与CPLD芯片之间通过SPI通信,SPI的数据传输速度远高于I2C的传输速度,相比于CPU直接通过I2C接口读取数据,本发明实施例可以提高读取速度,避免CPU因为读取I2C器件中的数据而无法处理其他业务的情况。When the CPU in the embodiment of the present invention needs to read data from the register of the I2C device, it can send a read instruction to the CPLD chip, and the CPLD chip completes the data read work, and the CPU can process other services at this time. Because the communication between the CPU and the CPLD chip is through SPI, the data transmission speed of SPI is much higher than the transmission speed of I2C. Compared with the CPU directly reading data through the I2C interface, the embodiment of the present invention can improve the reading speed and avoid the CPU from reading data. Fetching data from an I2C device and unable to process other services.
在本发明另一实施例中,当访问指令存在多个时,CPU可以通过SPI向CPLD芯片发送多个访问指令,以使得CPLD芯片通过I2C模拟接口,分别对每个访问指令所针对的I2C器件进行读写操作,并存储各读写操作的读写结果。In another embodiment of the present invention, when there are multiple access instructions, the CPU can send multiple access instructions to the CPLD chip through the SPI, so that the CPLD chip can use the I2C analog interface to separately access the I2C device targeted by each access instruction. Perform read and write operations, and store the read and write results of each read and write operation.
相应地,上述S302中CPU通过SPI获取CPLD芯片对待访问I2C器件的读写结果可以实现为:Correspondingly, in the above S302, the CPU obtains the read and write results of the I2C device to be accessed by the CPLD chip through SPI, which can be implemented as:
CPU通过SPI获取CPLD芯片分别对每个访问指令所针对的I2C器件的读写结果。The CPU obtains the read and write results of the I2C device targeted by each access instruction by the CPLD chip through the SPI.
可见,CPU向CPLD芯片发送多个访问指令后,可以继续处理其他业务,在CPLD芯片完成对多个访问指令所针对的I2C器件的读写操作后,CPU可一次性从CPLD芯片中读取多个读写结果,相比于CPU通过各I2C接口访问各I2C器件,本发明实施例可以减少对CPU资源的占用,相当于提高了CPU的数据访问效率。It can be seen that after the CPU sends multiple access commands to the CPLD chip, it can continue to process other services. After the CPLD chip completes the read and write operations on the I2C devices targeted by the multiple access commands, the CPU can read multiple access commands from the CPLD chip at one time. Compared with the CPU accessing each I2C device through each I2C interface, the embodiment of the present invention can reduce the occupation of CPU resources, which is equivalent to improving the data access efficiency of the CPU.
本发明实施例还提供了一种数据访问方法,该方法应用于CPLD芯片,其中CPLD芯片位于上述图2所示的交换机中。如图4所示,该方法包括如下步骤:An embodiment of the present invention further provides a data access method, which is applied to a CPLD chip, where the CPLD chip is located in the switch shown in FIG. 2 above. As shown in Figure 4, the method includes the following steps:
S401,通过SPI接收CPU发送的访问指令。其中,访问指令包括待访问I2C器件的物理地址和寄存器地址。S401, an access instruction sent by the CPU is received through the SPI. Wherein, the access instruction includes the physical address and register address of the I2C device to be accessed.
CPLD芯片具有一定的存储空间,可以将CPLD芯片的部分存储空间用作CPLD芯片的逻辑寄存器。CPU可通过CPLD芯片的内部逻辑代码的状态机,访问CPLD芯片的逻辑寄存器,以向CPLD芯片发送访问指令。The CPLD chip has a certain storage space, and part of the storage space of the CPLD chip can be used as the logic register of the CPLD chip. The CPU can access the logic registers of the CPLD chip through the state machine of the internal logic code of the CPLD chip, so as to send an access instruction to the CPLD chip.
S402,基于访问指令通过I2C模拟接口,对待访问I2C器件进行读写操作,并存储读写结果,以便CPU通过SPI获取CPLD芯片对待访问I2C器件的读写结果。S402 , based on the access instruction, through the I2C analog interface, perform read and write operations on the I2C device to be accessed, and store the read and write results, so that the CPU can obtain the read and write results of the I2C device to be accessed by the CPLD chip through the SPI.
CPLD芯片202包括多个I/O管脚,对于CPLD芯片202的部分I/O管脚,可以通过逻辑代码,在CPLD芯片的两个I/O管脚分别模拟I2C接口传输的SCL信号和SDA信号,从而将两个I/O管脚模拟为一个I2C接口。The
本发明实施例提供的数据访问方法,CPU与CPLD芯片通过SPI连接,CPLD芯片通过I2C模拟接口连接I2C器件。CPU在需要访问I2C器件时,通过SPI向CPLD芯片发送访问指令,由CPLD芯片基于访问指令对I2C器件进行读写操作。由于访问I2C器件的过程由CPLD芯片执行,CPU只需要通过SPI向CPLD芯片发送访问指令,在CPLD芯片对I2C器件进行读写操作时,CPU可以处理其他业务。且因SPI的速率比I2C总线速率高,所以CPU通过SPI从CPLD芯片中获取读写结果,相比于现有技术中CPU通过I2C接口访问I2C器件,可以减少访问I2C器件对CPU时间的占用,提高了数据访问效率,增加了CPU用于处理其他业务的时间。In the data access method provided by the embodiment of the present invention, the CPU and the CPLD chip are connected through SPI, and the CPLD chip is connected to the I2C device through an I2C analog interface. When the CPU needs to access the I2C device, it sends an access command to the CPLD chip through the SPI, and the CPLD chip reads and writes the I2C device based on the access command. Since the process of accessing the I2C device is performed by the CPLD chip, the CPU only needs to send an access command to the CPLD chip through the SPI. When the CPLD chip reads and writes the I2C device, the CPU can process other services. And because the speed of SPI is higher than the speed of I2C bus, the CPU obtains the read and write results from the CPLD chip through SPI. Compared with the prior art, the CPU accesses the I2C device through the I2C interface, which can reduce the occupation of the CPU time when accessing the I2C device. The data access efficiency is improved, and the CPU time for processing other services is increased.
本发明实施例中,CPU需要向I2C器件写入数据时,上述访问指令为写入指令,上述访问指令携带待写入数据。参见图5,上述S402中CPLD芯片基于访问指令通过I2C模拟接口,对待访问I2C器件进行读写操作,并存储读写结果可以通过以下步骤实现:In the embodiment of the present invention, when the CPU needs to write data to the I2C device, the above access command is a write command, and the above access command carries the data to be written. Referring to Figure 5, the CPLD chip in the above S402 can perform read and write operations on the I2C device to be accessed through the I2C analog interface based on the access command, and store the read and write results through the following steps:
S501,通过CPLD芯片的I2C模拟接口,向CPLD芯片连接的各I2C器件发送地址信号。其中,地址信号包括待访问I2C器件的物理地址。S501, send an address signal to each I2C device connected to the CPLD chip through the I2C analog interface of the CPLD chip. Wherein, the address signal includes the physical address of the I2C device to be accessed.
S502,接收待访问I2C器件通过I2C模拟接口向CPLD发送的确认消息。S502: Receive a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface.
其中,确认消息为待访问I2C器件接收到地址信号后,在确认地址信号中的物理地址与自身的物理地址相同的情况下发送的。确认消息可以为ACK消息。The confirmation message is sent under the condition that the physical address in the confirmation address signal is the same as its own physical address after the I2C device to be accessed receives the address signal. The acknowledgment message may be an ACK message.
S503,通过与待访问I2C器件之间的I2C模拟接口,将待写入数据写入待访问I2C器件中寄存器地址对应的寄存器。S503: Write the data to be written into the register corresponding to the register address in the I2C device to be accessed through the I2C analog interface with the I2C device to be accessed.
S504,通过与待访问I2C器件之间的I2C模拟接口,接收待访问I2C器件发送的写入响应,并基于写入响应存储对待写入数据的写入结果。S504, receive a write response sent by the I2C device to be accessed through an I2C analog interface with the I2C device to be accessed, and store the write result of the data to be written based on the write response.
其中,写入结果用于表示写入成功或写入失败。Among them, the writing result is used to indicate that the writing succeeds or the writing fails.
在本发明实施例中,CPLD芯片向I2C器件写入待写入数据后,如果在指定时长内接收到I2C器件反馈的ACK消息,则确定写入成功;或者,如果CPLD芯片在向I2C器件写入待写入数据后的指定时长内,未收到I2C器件反馈的ACK消息,则确定写入失败。CPLD芯片在接收到用于表示写入成功的ACK消息后,存储用于表示写入成功的写入结果。CPLD芯片在向I2C器件写入待写入数据后的指定时长内,如果没有接收到用于表示写入成功的ACK消息,则存储用于表示写入失败的写入结果。In the embodiment of the present invention, after the CPLD chip writes the data to be written to the I2C device, if the ACK message fed back by the I2C device is received within the specified time period, it is determined that the writing is successful; or, if the CPLD chip is writing to the I2C device. If no ACK message is received from the I2C device within a specified period of time after the data to be written is entered, it is determined that the write fails. After the CPLD chip receives the ACK message indicating that the writing is successful, it stores the writing result indicating that the writing is successful. If the CPLD chip does not receive an ACK message indicating that the writing is successful within a specified period of time after writing the data to be written to the I2C device, it will store the writing result indicating that the writing has failed.
本发明实施例中的CPU需要向I2C器件的寄存器中写入数据时,可以向CPLD芯片发送写入指令,由CPLD芯片完成数据写入工作,在CPLD进行数据写入的过程中,CPU可以处理其他业务。因CPU与CPLD芯片之间通过SPI通信,SPI的数据传输速度远高于I2C的传输速度,相比于CPU直接通过I2C接口向I2C器件写入数据,本发明实施例可以提高CPU的数据写入速度,避免CPU因为向I2C器件写入数据而无法处理其他业务的情况。When the CPU in the embodiment of the present invention needs to write data into the register of the I2C device, it can send a write instruction to the CPLD chip, and the CPLD chip completes the data writing work. During the data writing process of the CPLD, the CPU can process Other business. Because the communication between the CPU and the CPLD chip is through SPI, the data transmission speed of SPI is much higher than the transmission speed of I2C. Compared with the CPU directly writing data to the I2C device through the I2C interface, the embodiment of the present invention can improve the data writing of the CPU. speed, to avoid the situation that the CPU cannot process other services because of writing data to the I2C device.
在本发明实施例中,CPU需要从I2C器件读取数据时,上述访问指令为读取指令。参见图6,上述S402中CPLD芯片基于访问指令通过I2C模拟接口,对待访问I2C器件进行读写操作,并存储读写结果可以通过以下步骤实现:In this embodiment of the present invention, when the CPU needs to read data from the I2C device, the above-mentioned access instruction is a read instruction. Referring to Figure 6, the CPLD chip in the above S402 performs read and write operations on the I2C device to be accessed through the I2C analog interface based on the access command, and stores the read and write results through the following steps:
S601,通过CPLD芯片的I2C模拟接口,向CPLD芯片连接的各I2C器件发送地址信号。其中,地址信号包括待访问I2C器件的物理地址。S601, send an address signal to each I2C device connected to the CPLD chip through the I2C analog interface of the CPLD chip. Wherein, the address signal includes the physical address of the I2C device to be accessed.
S602,接收待访问I2C器件通过I2C模拟接口向CPLD发送的确认消息。S602: Receive a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface.
其中,确认消息为所述待访问I2C器件接收到所述地址信号后,在确认地址信号中的物理地址与自身的物理地址相同的情况下发送的。确认消息可以是ACK信号。The confirmation message is sent after the I2C device to be accessed receives the address signal and confirms that the physical address in the address signal is the same as its own physical address. The acknowledgement message may be an ACK signal.
S603,通过与待访问I2C器件之间的I2C模拟接口,从待访问I2C器件中,寄存器地址对应的寄存器中读取待读取数据。S603, through the I2C analog interface with the I2C device to be accessed, read the data to be read from the register corresponding to the register address in the I2C device to be accessed.
S604,存储待读取数据,以便CPU通过SPI从CPLD芯片中获取待读取数据。S604, store the data to be read, so that the CPU obtains the data to be read from the CPLD chip through the SPI.
本发明实施例中,CPU可以每间隔一段时间,从CPLD芯片中读取一次待读取数据,减少CPU多次读取待读取数据的情况,减少对CPU资源的占用,同时提高了I2C总线的管理效率,从而提高了交换机的运行效率。In the embodiment of the present invention, the CPU can read the data to be read from the CPLD chip once at regular intervals, which reduces the situation that the CPU reads the data to be read multiple times, reduces the occupation of CPU resources, and improves the I2C bus. management efficiency, thereby improving the operating efficiency of the switch.
在交换机中,如果CPU的I2C总线在进行数据访问时出现错误(例如CPU在从I2C器件中读取数据,或者向I2C器件写入数据的过程中,没有接收到I2C器件的响应),则导致I2C总线挂死,对I2C总线恢复后,CPU才能继续访问I2C器件。In the switch, if the I2C bus of the CPU has an error during data access (for example, the CPU does not receive a response from the I2C device while reading data from the I2C device, or writing data to the I2C device), it will cause The I2C bus hangs up, and the CPU can continue to access the I2C device after the I2C bus is restored.
恢复I2C总线的常规方法为:CPU通过GPIO管脚连续发送9个高电平信号,即CPU将GPIO管脚连续置为高电平9次。CPU所在的单板上的特殊电路监测到GPIO管脚发送的连续9个高电平信号时,将I2C总线的SCL时钟信号连续拉低9次,以恢复I2C总线。The conventional method to restore the I2C bus is: the CPU sends 9 high level signals continuously through the GPIO pin, that is, the CPU sets the GPIO pin to the high level 9 times continuously. When the special circuit on the single board where the CPU is located detects 9 consecutive high-level signals sent by the GPIO pin, it pulls down the SCL clock signal of the I2C bus continuously for 9 times to restore the I2C bus.
这种恢复I2C总线的方式需要在单板上增加额外的特殊电路,既增加了恢复I2C总线的复杂度,又增加了交换机的硬件成本。This method of restoring the I2C bus needs to add an extra special circuit on the single board, which not only increases the complexity of restoring the I2C bus, but also increases the hardware cost of the switch.
而本发明实施例中,恢复连接CPLD芯片的I2C总线的方式包括:若通过SPI总线接收到CPU对指定I2C模拟接口的恢复命令,则将指定I2C模拟接口的SCL时钟信号连续拉低9次。其中,指定I2C模拟接口为出现错误的I2C模拟接口。In the embodiment of the present invention, the method of restoring the I2C bus connected to the CPLD chip includes: if the CPU receives a restoration command for the designated I2C analog interface through the SPI bus, then continuously pulls down the SCL clock signal of the designated I2C analog interface 9 times. Among them, the specified I2C analog interface is the I2C analog interface with an error.
CPU从CPLD芯片中获取读写结果,如果读写结果用于表示读取/写入失败,则CPU通过SPI向CPLD芯片发送恢复命令,CPLD在接收到恢复命令后,通过内部逻辑代码模拟I2C总线,将指定I2C模拟接口的SCL时钟信号连续拉低9次,以恢复I2C总线。The CPU obtains the read and write results from the CPLD chip. If the read and write results are used to indicate that the read/write fails, the CPU sends a recovery command to the CPLD chip through SPI. After receiving the recovery command, the CPLD simulates the I2C bus through the internal logic code. , pull down the SCL clock signal of the specified I2C analog interface continuously 9 times to restore the I2C bus.
可见,本发明实施例直接利用CPLD芯片恢复I2C总线,由于交换机单板中自带有CPLD芯片,因此本发明实施例恢复I2C总线不需要在交换机中增加额外的硬件,减少了交换机的硬件成本。It can be seen that the embodiment of the present invention directly uses the CPLD chip to restore the I2C bus. Since the switch board has its own CPLD chip, the embodiment of the present invention does not need to add additional hardware in the switch to restore the I2C bus, which reduces the hardware cost of the switch.
基于相同的发明构思,对应于上述方法实施例,本发明实施例提供了,本发明实施例提供了一种数据访问装置,应用于CPU,CPU位于上述图2所示的交换机中,如图7所示,该装置包括:写入模块701和获取模块702;Based on the same inventive concept, corresponding to the above method embodiments, the embodiments of the present invention provide, and the embodiments of the present invention provide a data access device, which is applied to a CPU, and the CPU is located in the switch shown in FIG. 2 , as shown in FIG. 7 . As shown, the device includes: a
写入模块701,用于通过SPI向CPLD芯片发送访问指令,访问指令包括待访问I2C器件的物理地址和寄存器地址,以使得CPLD芯片基于访问指令通过I2C模拟接口,对待访问I2C器件进行读写操作,得到读写结果;The
获取模块702,用于通过SPI获取CPLD芯片对待访问I2C器件的读写结果。The obtaining
可选的,访问指令为写入指令,写入指令携带待写入数据;获取模块702,具体用于:Optionally, the access instruction is a write instruction, and the write instruction carries data to be written; the acquiring
通过SPI从CPLD芯片中获取对待写入数据的写入结果,写入结果用于表示写入成功或写入失败。The writing result of the data to be written is obtained from the CPLD chip through SPI, and the writing result is used to indicate that the writing is successful or the writing fails.
可选的,访问指令为读取指令;获取模块702,具体用于:Optionally, the access instruction is a read instruction; the acquiring
通过SPI从CPLD芯片中获取待读取数据,待读取数据为CPLD芯片通过I2C模拟接口从待访问I2C器件中,寄存器地址对应的寄存器中读取的数据。The data to be read is obtained from the CPLD chip through SPI, and the data to be read is the data read by the CPLD chip from the register corresponding to the register address of the I2C device to be accessed through the I2C analog interface.
基于相同的发明构思,对应于上述方法实施例,本发明实施例提供了一种数据访问装置,应用于CPLD芯片,CPLD芯片位于上述实施例的交换机中。如图8所示,该装置包括:接收模块801和访问模块802;Based on the same inventive concept, and corresponding to the foregoing method embodiments, the embodiments of the present invention provide a data access device, which is applied to a CPLD chip, and the CPLD chip is located in the switches of the foregoing embodiments. As shown in FIG. 8 , the apparatus includes: a receiving
接收模块801,用于通过SPI接收CPU发送的访问指令,访问指令包括待访问I2C器件的物理地址和寄存器地址;The receiving
访问模块802,用于基于访问指令通过I2C模拟接口,对待访问I2C器件进行读写操作,并存储读写结果,以便CPU通过SPI获取CPLD芯片对待访问I2C器件的读写结果。The
可选的,访问指令为写入指令,写入指令携带待写入数据;访问模块802,具体用于:Optionally, the access instruction is a write instruction, and the write instruction carries data to be written; the
通过CPLD芯片的I2C模拟接口,向CPLD芯片连接的各I2C器件发送地址信号,地址信号包括待访问I2C器件的物理地址;Send an address signal to each I2C device connected to the CPLD chip through the I2C analog interface of the CPLD chip, and the address signal includes the physical address of the I2C device to be accessed;
接收待访问I2C器件通过I2C模拟接口向CPLD发送的确认消息,确认消息为待访问I2C器件接收到地址信号后,在确认地址信号中的物理地址与自身的物理地址相同的情况下发送的;Receive the confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, and the confirmation message is sent when the physical address in the confirmation address signal is the same as its own physical address after the I2C device to be accessed receives the address signal;
通过与待访问I2C器件之间的I2C模拟接口,将待写入数据写入待访问I2C器件中寄存器地址对应的寄存器;Write the data to be written into the register corresponding to the register address in the I2C device to be accessed through the I2C analog interface with the I2C device to be accessed;
通过与待访问I2C器件之间的I2C模拟接口,接收待访问I2C器件发送的写入响应,并基于写入响应存储对待写入数据的写入结果,写入结果用于表示写入成功或写入失败。Through the I2C analog interface with the I2C device to be accessed, the write response sent by the I2C device to be accessed is received, and the write result of the data to be written is stored based on the write response, and the write result is used to indicate that the write is successful or Entry failed.
可选的,访问指令为读取指令;Optionally, the access instruction is a read instruction;
访问模块802,具体用于:The
通过CPLD芯片的I2C模拟接口,向CPLD芯片连接的各I2C器件发送地址信号,地址信号包括待访问I2C器件的物理地址;Send an address signal to each I2C device connected to the CPLD chip through the I2C analog interface of the CPLD chip, and the address signal includes the physical address of the I2C device to be accessed;
接收待访问I2C器件通过I2C模拟接口向CPLD发送的确认消息,确认消息为待访问I2C器件接收到地址信号后,在确认地址信号中的物理地址与自身的物理地址相同的情况下发送的;Receive the confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, and the confirmation message is sent when the physical address in the confirmation address signal is the same as its own physical address after the I2C device to be accessed receives the address signal;
通过与待访问I2C器件之间的I2C模拟接口,从待访问I2C器件中,寄存器地址对应的寄存器中读取待读取数据;Through the I2C analog interface with the I2C device to be accessed, the data to be read is read from the register corresponding to the register address of the I2C device to be accessed;
存储待读取数据,以便CPU通过SPI从CPLD芯片中获取待读取数据。Store the data to be read so that the CPU can obtain the data to be read from the CPLD chip through SPI.
可选的,装置还包括:拉低模块;Optionally, the device further includes: a pull-down module;
拉低模块,用于若通过SPI总线接收到CPU对指定I2C模拟接口的恢复命令,则将指定I2C模拟接口的SCL时钟信号连续拉低9次。The pull-down module is used to pull down the SCL clock signal of the designated I2C analog interface continuously for 9 times if the CPU's recovery command to the designated I2C analog interface is received through the SPI bus.
需要说明的是,在本文中,诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来,而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且,术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下,由语句“包括一个……”限定的要素,并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。It should be noted that, in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any relationship between these entities or operations. any such actual relationship or sequence exists. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device that includes a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.
本说明书中的各个实施例均采用相关的方式描述,各个实施例之间相同相似的部分互相参见即可,每个实施例重点说明的都是与其他实施例的不同之处。尤其,对于装置实施例而言,由于其基本相似于方法实施例,所以描述的比较简单,相关之处参见方法实施例的部分说明即可。Each embodiment in this specification is described in a related manner, and the same and similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the apparatus embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and reference may be made to some descriptions of the method embodiments for related parts.
以上所述仅为本发明的较佳实施例,并非用于限定本发明的保护范围。凡在本发明的精神和原则之内所作的任何修改、等同替换、改进等,均包含在本发明的保护范围内。The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
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