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CN113434442B - A switch and data access method - Google Patents

A switch and data access method Download PDF

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Publication number
CN113434442B
CN113434442B CN202110738248.8A CN202110738248A CN113434442B CN 113434442 B CN113434442 B CN 113434442B CN 202110738248 A CN202110738248 A CN 202110738248A CN 113434442 B CN113434442 B CN 113434442B
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cpld chip
cpu
accessed
read
write
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CN113434442A (en
Inventor
商轲
雷雄
孙东
卢杰
薛建军
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New H3C Security Technologies Co Ltd
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New H3C Security Technologies Co Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/36Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/362Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4022Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/42Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)

Abstract

本发明实施例提供了一种交换机及数据访问方法,涉及通信技术领域,可以提高CPU访问I2C器件的效率,减少访问I2C器件对CPU的占用。本发明实施例的交换机包括:中央处理器CPU、复杂可编程逻辑器件CPLD芯片和多个集成电路总线I2C器件。CPU通过串行外设接口SPI与CPLD芯片连接;CPLD芯片包括多个I2C模拟接口,每个I2C模拟接口通过两个I/O管脚模拟实现;CPLD芯片包括的每个I2C模拟接口与不同的I2C器件连接。CPU用于通过SPI向CPLD芯片发送访问指令;CPLD芯片用于基于访问指令通过I2C模拟接口对I2C器件进行读写操作。

The embodiment of the present invention provides a switch and a data access method, which relates to the field of communication technology, and can improve the efficiency of CPU access to I2C devices and reduce the occupancy of CPU by accessing I2C devices. The switch of the embodiment of the present invention includes: a central processing unit CPU, a complex programmable logic device CPLD chip and multiple integrated circuit bus I2C devices. The CPU is connected to the CPLD chip through a serial peripheral interface SPI; the CPLD chip includes multiple I2C analog interfaces, each of which is implemented by two I/O pins; each I2C analog interface included in the CPLD chip is connected to a different I2C device. The CPU is used to send an access instruction to the CPLD chip through the SPI; the CPLD chip is used to perform read and write operations on the I2C device through the I2C analog interface based on the access instruction.

Description

Switch and data access method
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a switch and a data access method.
Background
A central processing unit (central processing unit, CPU) on the switch board can access an I2C device such as a charged erasable programmable read-only memory (ELECTRICALLY ERASABLE PROGRAMMABLE READ ONLY MEMORY, EEPROM), a temperature sensor, a Real Time Clock (RTC), an optical module, etc. included on the board through an Inter-integrated circuit (Inter-INTEGRATED CIRCUIT, I2C) bus. I2C is a low-speed serial bus, consisting of two lines, a serial clock line (Serial Clock line, SCL) and a serial data line (SERIAL DATA, SDA).
As shown in FIG. 1, different types of I2C devices on a switch board can be connected to different I2C interfaces of a CPU, such as a temperature sensing chip, an RTC chip and an EEPROM in FIG. 1 are connected to the I2C1 interface of the CPU, a power supply and a fan are connected to the I2C2 interface of the CPU, one end of an analog switch is connected with a service interface module 0-N, the other end of the analog switch is connected to the I2C3 interface of the CPU, and the other I2C devices are connected to the I2C4 interface of the CPU.
The number of I2C devices on the switch board is large, the CPU needs to access the I2C devices through the I2C bus at intervals, because the speed of the I2C bus is low, the CPU accesses a large number of I2C devices to occupy a large amount of time of the CPU, the access efficiency is low, and other services cannot be carried out by the CPU when the CPU accesses the I2C devices.
Disclosure of Invention
The embodiment of the invention aims to provide a switch and a data access method, which are used for improving the efficiency of accessing an I2C device by a CPU and reducing the occupation of the CPU by the I2C device. The specific technical scheme is as follows:
In a first aspect, an embodiment of the present invention provides a switch, including a central processing unit CPU, a complex programmable logic device CPLD chip, and a plurality of integrated circuit bus I2C devices;
The CPU is connected with the CPLD chip through a serial peripheral interface SPI; the CPLD chip comprises a plurality of I2C analog interfaces, wherein each I2C analog interface is realized through two I/O pin simulations, and each I2C analog interface included in the CPLD chip is connected with different I2C devices;
The CPU is used for sending an access instruction to the CPLD chip through the SPI;
And the CPLD chip is used for performing read-write operation on the I2C device through the I2C analog interface based on the access instruction.
Optionally, the first I2C analog interface of the CPLD chip is connected to a plurality of I2C devices having different physical addresses, and/or,
The second I2C analog interface of the CPLD chip is connected with an analog switch, the analog switch is connected with a plurality of I2C devices with the same physical address, and the analog switch is used for selectively opening or closing the access channels of the I2C devices connected with the analog switch.
Optionally, the CPU comprises an I2C interface, and the CPU is connected with a designated I2C device through the I2C interface, or
One of the I2C analog interfaces of the CPLD chip is connected with the appointed I2C device.
Optionally, the designated I2C device includes a power source and a fan.
In a second aspect, an embodiment of the present invention provides a data access method, applied to a CPU, where the CPU is located in the switch in any one of the first aspect, where the method includes:
The CPU sends an access instruction to a CPLD chip through an SPI, wherein the access instruction comprises a physical address and a register address of an I2C device to be accessed, so that the CPLD chip performs read-write operation on the I2C device to be accessed through an I2C simulation interface based on the access instruction to obtain a read-write result;
And the CPU acquires a read-write result of the CPLD chip on the I2C device to be accessed through the SPI.
Optionally, the access instruction is a write instruction, where the write instruction carries data to be written;
the CPU obtains the read-write result of the CPLD chip to the I2C device to be accessed through the SPI, and the read-write result comprises the following steps:
and the CPU acquires a writing result of the data to be written from the CPLD chip through the SPI, wherein the writing result is used for indicating that the writing is successful or the writing fails.
Optionally, the access instruction is a read instruction, and the CPU obtains a read-write result of the CPLD chip on the I2C device to be accessed through the SPI, including:
The CPU acquires data to be read from the CPLD chip through the SPI, wherein the data to be read is the data read from the register corresponding to the register address in the I2C device to be accessed through an I2C analog interface by the CPLD chip.
In a third aspect, an embodiment of the present invention provides a data access method, applied to a CPLD chip, where the CPLD chip is located in the switch in any one of the first aspects, where the method includes:
receiving an access instruction sent by a CPU through an SPI, wherein the access instruction comprises a physical address and a register address of an I2C device to be accessed;
And performing read-write operation on the I2C device to be accessed through an I2C analog interface based on the access instruction, and storing a read-write result, so that the CPU obtains the read-write result of the CPLD chip on the I2C device to be accessed through the SPI.
Optionally, the access instruction is a write instruction, where the write instruction carries data to be written;
the step of performing read-write operation on the I2C device to be accessed through an I2C simulation interface based on the access instruction and storing a read-write result comprises the following steps:
Transmitting address signals to each I2C device connected with the CPLD chip through an I2C analog interface of the CPLD chip, wherein the address signals comprise physical addresses of the I2C devices to be accessed;
receiving a confirmation message sent by an I2C device to be accessed to the CPLD through an I2C analog interface, wherein the confirmation message is sent under the condition that the physical address in the address signal is confirmed to be the same as the physical address of the device after the I2C device to be accessed receives the address signal;
writing the data to be written into a register corresponding to the register address in the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and the I2C device to be accessed;
and receiving a writing response sent by the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and the I2C device to be accessed, and storing a writing result of the data to be written based on the writing response, wherein the writing result is used for indicating that writing is successful or writing fails.
Optionally, the access instruction is a read instruction, the read-write operation is performed on the I2C device to be accessed through an I2C simulation interface based on the access instruction, and a read-write result is stored, including:
Transmitting address signals to each I2C device connected with the CPLD chip through an I2C analog interface of the CPLD chip, wherein the address signals comprise physical addresses of the I2C devices to be accessed;
receiving a confirmation message sent by an I2C device to be accessed to the CPLD through an I2C analog interface, wherein the confirmation message is sent under the condition that the physical address in the address signal is confirmed to be the same as the physical address of the device after the I2C device to be accessed receives the address signal;
Reading data to be read from a register corresponding to the register address in the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and the register address;
and storing the data to be read so that the CPU can acquire the data to be read from the CPLD chip through the SPI.
Optionally, the method further comprises:
And if a recovery command of the CPU to the appointed I2C analog interface is received through the SPI bus, continuously pulling down the SCL clock signal of the appointed I2C analog interface for 9 times.
In a fourth aspect, an embodiment of the present invention provides a data access device, applied to a CPU, where the CPU is located in the switch in the first aspect, where the device includes:
The write-in module is used for sending an access instruction to the CPLD chip through the SPI, wherein the access instruction comprises a physical address and a register address of an I2C device to be accessed, so that the CPLD chip performs read-write operation on the I2C device to be accessed through an I2C simulation interface based on the access instruction to obtain a read-write result;
and the acquisition module is used for acquiring the read-write result of the CPLD chip to the I2C device to be accessed through the SPI.
Optionally, the access instruction is a write instruction, where the write instruction carries data to be written, and the obtaining module is specifically configured to:
and acquiring a writing result of the data to be written from the CPLD chip through the SPI, wherein the writing result is used for indicating writing success or writing failure.
Optionally, the access instruction is a read instruction, and the acquisition module is specifically configured to:
And acquiring data to be read from the CPLD chip through the SPI, wherein the data to be read is read from the register corresponding to the register address in the I2C device to be accessed through an I2C analog interface by the CPLD chip.
In a fifth aspect, an embodiment of the present invention provides a data access device applied to a CPLD chip, where the CPLD chip is located in the switch in the first aspect, where the device includes:
The receiving module is used for receiving an access instruction sent by the CPU through the SPI, wherein the access instruction comprises a physical address and a register address of an I2C device to be accessed;
and the access module is used for performing read-write operation on the I2C device to be accessed through an I2C simulation interface based on the access instruction and storing a read-write result so that the CPU can acquire the read-write result of the CPLD chip on the I2C device to be accessed through the SPI.
Optionally, the access instruction is a write instruction, where the write instruction carries data to be written;
The access module is specifically configured to:
Transmitting address signals to each I2C device connected with the CPLD chip through an I2C analog interface of the CPLD chip, wherein the address signals comprise physical addresses of the I2C devices to be accessed;
receiving a confirmation message sent by an I2C device to be accessed to the CPLD through an I2C analog interface, wherein the confirmation message is sent under the condition that the physical address in the address signal is confirmed to be the same as the physical address of the device after the I2C device to be accessed receives the address signal;
writing the data to be written into a register corresponding to the register address in the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and the I2C device to be accessed;
and receiving a writing response sent by the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and the I2C device to be accessed, and storing a writing result of the data to be written based on the writing response, wherein the writing result is used for indicating that writing is successful or writing fails.
Optionally, the access instruction is a read instruction;
The access module is specifically configured to:
Transmitting address signals to each I2C device connected with the CPLD chip through an I2C analog interface of the CPLD chip, wherein the address signals comprise physical addresses of the I2C devices to be accessed;
receiving a confirmation message sent by an I2C device to be accessed to the CPLD through an I2C analog interface, wherein the confirmation message is sent under the condition that the physical address in the address signal is confirmed to be the same as the physical address of the device after the I2C device to be accessed receives the address signal;
Reading data to be read from a register corresponding to the register address in the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and the register address;
and storing the data to be read so that the CPU can acquire the data to be read from the CPLD chip through the SPI.
Optionally, the device further comprises a pull-down module;
And the pulling-down module is used for continuously pulling down the SCL clock signal of the appointed I2C analog interface for 9 times if a recovery command of the CPU to the appointed I2C analog interface is received through the SPI bus.
According to the switch and the data access method provided by the embodiment of the invention, the CPU is connected with the CPLD chip through the SPI, and the CPLD chip can be connected with the I2C device through the I2C analog interface. When the CPU needs to access the I2C device, an access instruction is sent to the CPLD chip through the SPI, and the CPLD chip performs read-write operation on the I2C device based on the access instruction. Because the process of accessing the I2C device is executed by the CPLD, the CPU only needs to send an access instruction to the CPLD chip through the SPI, and the SPI speed is higher than the I2C bus speed, so that the occupation of the access I2C device to the CPU is reduced, and the access efficiency is improved.
Of course, it is not necessary for any one product or method of practicing the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and other embodiments may be obtained according to these drawings to those skilled in the art.
FIG. 1 is a schematic diagram of a switch in the related art;
fig. 2 is a schematic structural diagram of a switch according to an embodiment of the present invention;
FIG. 3 is a flowchart of a data access method according to an embodiment of the present invention;
FIG. 4 is a flowchart of another data access method according to an embodiment of the present invention;
FIG. 5 is a flowchart of a data writing method according to an embodiment of the present invention;
FIG. 6 is a flowchart of a data reading method according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a data access device according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of another data access device according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. Based on the embodiments of the present application, all other embodiments obtained by the person skilled in the art based on the present application are included in the scope of protection of the present application.
In order to improve the efficiency of a central processing unit (central processing unit, CPU) accessing an integrated circuit bus (Inter-INTEGRATED CIRCUIT, I2C) device and reduce the occupation of accessing the I2C device to the CPU, embodiments of the present invention provide a switch, where the switch may be a box switch or a frame switch, and the embodiments of the present invention are not limited in this respect.
As shown in fig. 2, the switch provided by the embodiment of the present invention includes a CPU 201, a CPLD (Complex Programmable logic device ) chip 202, and a plurality of I2C devices.
CPU201 is connected with CPLD chip 202 through serial peripheral interface (SERIAL PERIPHERAL INTERFACE, SPI), CPLD chip 202 comprises multiple I2C analog interfaces, each I2C analog interface is realized through two Input/Output (I/O) pin simulations, and each I2C analog interface included in CPLD chip 202 is connected with different I2C devices. The CPLD chip 202 includes a certain memory space, and a part of the memory space of the CPLD chip 202 may be used as a logic register of the CPLD chip 202, where the logic register may store an access instruction sent by the CPU201, and may also store a read-write result of an I2C device to be accessed.
The CPU 201 is used for sending an access instruction to the CPLD chip 202 through the SPI, and the CPLD chip 202 is used for performing read-write operation on the I2C device through the I2C analog interface based on the access instruction.
In the embodiment of the present invention, the connection relationship between the I2C analog interface of the CPLD chip 202 and the I2C device may be set according to actual requirements.
For example, where there are fewer I2C devices, each I2C analog interface of CPLD chip 202 may be connected to one I2C device.
In the case of more I2C devices, each I2C analog interface of CPLD chip 202 may connect multiple I2C devices. In one embodiment, the I2C devices may be classified according to the importance level of the I2C devices, for example, the I2C devices in the switch may be classified into two types, one type is an important I2C device, the other type is a non-important I2C device, and then the I2C devices (such as a service port optical module) externally connected to the switch are used as one type. Accordingly, one I2C analog interface of the CPLD chip 202 is connected to an important I2C device, another I2C analog interface is connected to a non-important I2C device, and another I2C analog interface is connected to a plurality of service port optical modules through an analog switch. Or the I2C device in the switch is used as one type of I2C device, and the I2C device externally connected with the switch is used as the other type of I2C device. Accordingly, one I2C analog interface of CPLD chip 202 connects to an I2C device inside the switch, and the other I2C analog interface connects to an I2C device external to the switch through an analog switch. The embodiment of the application does not limit the classification mode of the I2C devices, and can set each I2C device connected with the I2C analog interface according to actual requirements.
For example, the temperature sensing chip, RTC chip, and EEPROM in fig. 2 are one type of I2C device that are commonly connected to the I2C2 analog interface of the CPLD chip 202. In fig. 2, service port optical modules 0 to n are external modules, and service port optical modules 0 to n are I2C devices and are connected to an I2C3 analog interface of the CPLD chip 202 through an analog switch.
CPLD chip 202 includes a plurality of I/O pins, and for some I/O pins of CPLD chip 202, SCL signals and SDA signals transmitted by an I2C interface can be respectively simulated at two I/O pins of CPLD chip 202 through logic codes, so that the two I/O pins are simulated as one I2C interface. The embodiment of the invention realizes the function of simulating the I2C interface through part of I/O pins of the CPLD chip, and the CPLD chip is provided with a plurality of I/O pins, so that the hardware cost of the CPLD chip is not increased.
According to the switch provided by the embodiment of the invention, the CPU is connected with the CPLD chip through the SPI, and the CPLD chip can be connected with an I2C device through an I2C analog interface. When the CPU needs to access the I2C device, an access instruction is sent to the CPLD chip through the SPI, and the CPLD chip performs read-write operation on the I2C device based on the access instruction. Because the process of accessing the I2C device is executed by the CPLD, the CPU only needs to send an access instruction to the CPLD chip through the SPI, and the SPI speed is higher than the I2C bus speed, so that the occupation of the access I2C device to the CPU is reduced, and the access efficiency is improved.
Illustratively, the rate of the I2C bus that transfers data between the I2C interfaces is typically below 100 kilohertz (kHz), while the rate of the SPI bus that transfers data between the SPI interfaces is typically above 2 MegaHertz (MegaHertz, MHz), so that the rate of the SPI is much higher than the rate of the I2C bus.
In the embodiment of the present invention, the first I2C analog interface of the CPLD chip 202 is connected to a plurality of I2C devices having different physical addresses, and/or the second I2C analog interface of the CPLD chip 202 is connected to an analog switch, and the analog switch is connected to a plurality of I2C devices having the same physical address. The analog switch is used for selectively opening or closing the access channel of each I2C device connected with the analog switch.
Alternatively, the first I2C analog interface of CPLD chip 202 may be connected to an I2C device.
The "first" of the first I2C analog interfaces and the "second" of the second I2C analog interfaces are only used for distinguishing the I2C analog interfaces connected with different devices, and are not used for limiting the properties of the I2C analog interfaces.
For example, as shown in FIG. 2, the I2C2 analog interface of CPLD chip 202 is connected to a temperature sensing chip, EEPROM, and RTC chip. The temperature sensing chip, the EEPROM and the RTC chip are I2C devices, and the physical addresses are different from each other.
Alternatively, because the physical addresses of the traffic port optical modules are typically the same, each traffic port optical module may be connected to one of the I2C analog interfaces of CPLD chip 202. Or as shown in fig. 2, the service port optical modules 0 to n may be connected to the I2C3 analog interface of the CPLD chip 202 through an analog switch. The CPLD chip 202 accesses different traffic port optical modules by selecting different access channels through the analog switch. Wherein the analog switch selects different access channels based on the control signal of CPLD chip 202.
In the embodiment of the present invention, the CPU 201 includes an I2C interface, through which the CPU 201 is connected to a specified I2C device, or one of the I2C analog interfaces of the CPLD chip 202 is connected to a specified I2C device.
Optionally, the designated I2C device includes a power source and a fan.
For example, as shown in FIG. 2, a power supply and a fan are connected to the I2C1 interface of the CPU 201.
Because the CPU is generally provided with an I2C interface, the important I2C devices are directly connected with the I2C interface of the CPU, so that the reliability of the CPU for accessing the important I2C devices can be improved.
Alternatively, other I2C devices may be present in addition to the power supply, fan, temperature sensing chip, EEPROM, RTC chip, and service port optical module, such as a power supply monitor module, clock phase locked loop, etc.
For example, as shown in fig. 2, other I2C devices may be interfaced with the I2C4 analog interface of the CPLD chip 202.
According to the embodiment of the invention, all I2C devices in the switch can be connected to the CPLD chip, so that the occupation of CPU resources by the I2C devices can be reduced as much as possible, and other operations of the CPU due to the occupation of the I2C interface can be prevented.
Meanwhile, in the related art, all the I2C devices are directly connected with the I2C interface of the CPU, so that each type of I2C device is connected with one I2C interface for classifying and managing the I2C devices, so that the CPU needs to have a large number of I2C interfaces, the type selection of the CPU in the switch is limited to a certain extent, and the cost of the CPU is increased.
In the embodiment of the invention, part of I2C devices can be directly connected with the I2C interface of the CPU, or all I2C devices in the switch are arranged to be connected with the CPLD chip instead of the CPU, so that the CPU with fewer I2C interfaces can be selected, thereby reducing the limitation on the type selection of the CPU in the switch and reducing the cost of the CPU.
In addition, in the related art, the I2C interface is simulated through a high-speed serial computer expansion bus standard (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, PCIE) interface or a universal serial bus (Universal Serial Bus, USB) interface, and these schemes all require adding additional chips in a switch board where the CPU and the I2C devices are located, which increases the hardware cost of the switch.
The CPLD chip is generally contained in the switch single board where the CPU and the I2C device are located, the CPLD chip of the switch single board is utilized to realize the function of converting SPI protocol into I2C protocol, and the CPLD chip of the switch single board can generally realize the function, so that the CPLD chip on the switch single board is not additionally limited in shape selection and does not increase additional hardware cost.
A conventional switch structure is shown in fig. 1, wherein a temperature sensing chip, an RTC chip and an EEPROM are connected to an I2C1 interface of a CPU, a power supply and a fan are connected to the I2C2 interface of the CPU, one end of an analog switch is connected with a service interface module 0-N, the other end of the analog switch is connected to the I2C3 interface of the CPU, and other I2C devices are connected to the I2C4 interface of the CPU. The I2C devices connected with the same I2C interface are distinguished through different physical addresses, and if the physical addresses of the I2C devices connected with the same I2C interface are the same, different channels are gated by the analog switch for distinguishing.
When the CPU needs to access one I2C device, the CPU sends address signals to all I2C devices connected with the CPU through each I2C interface, wherein the address signals comprise the physical addresses of the I2C devices needing to be accessed. After each I2C device receives the address signal, if the address signal includes the same physical address as itself, an acknowledge character (Acknowledge character, ACK) signal is fed back to the CPU to inform the CPU that further operations can be performed. After receiving the ACK signal, the CPU reads data from the I2C device that transmitted the ACK signal or writes data to the I2C device that transmitted the ACK signal.
If a plurality of I2C devices with the same physical address are connected to one I2C interface of the CPU, or the load capacitance of the I2C devices connected to one I2C interface of the CPU exceeds the highest capacitance supported by the I2C protocol (400 pF, wherein pF represents picofarads), the CPLD chip controls the analog switch to open a corresponding channel, so that the CPU accesses the corresponding I2C devices.
In addition to conventional access to I2C devices, a CPU needs to perform a read/write operation in some I2C devices at intervals, i.e., poll some I2C devices. Since the CPU accesses the I2C device through the I2C interface, and the rate of the I2C interface is low, that is, the speed of the CPU sending an address signal, receiving an ACK message, and reading or writing data to the I2C device is slow, a great deal of time and resources of the CPU are occupied, which results in difficulty in the CPU processing other services.
In order to improve the access efficiency of the CPU, the occupation of CPU resources by the access I2C device is reduced. The embodiment of the invention provides a data access method, which is applied to a CPU, wherein the CPU is positioned in a switch shown in the figure 2, and as shown in the figure 3, the method comprises the following steps:
s301, the CPU sends an access instruction to the CPLD chip through the SPI.
The access instruction comprises a physical address and a register address of the I2C device to be accessed, so that the CPLD chip performs read-write operation on the I2C device to be accessed through the I2C analog interface based on the access instruction, and a read-write result is obtained.
In the embodiment of the invention, the CPLD chip has a certain storage space, and part of the storage space of the CPLD chip can be used as a logic register of the CPLD chip. The CPU may access a logic register of the CPLD chip through a state machine of an internal logic code of the CPLD chip to send an access instruction to the CPLD chip.
S302, the CPU obtains the read-write result of the CPLD chip to the I2C device to be accessed through the SPI.
According to the data access method provided by the embodiment of the invention, the CPU is connected with the CPLD chip through the SPI, and the CPLD chip is connected with the I2C device through the I2C analog interface. When the CPU needs to access the I2C device, an access instruction is sent to the CPLD chip through the SPI, and the CPLD chip performs read-write operation on the I2C device based on the access instruction. Because the process of accessing the I2C device is executed by the CPLD chip, the CPU only needs to send an access instruction to the CPLD chip, and when the CPLD chip performs read-write operation on the I2C device, the CPU can process other services. And because the SPI speed is higher than the I2C bus speed, the CPU obtains the read-write result of the I2C device to be accessed from the CPLD chip through the SPI, compared with the prior art that the CPU accesses the I2C device through the I2C interface, the occupation of the CPU time for accessing the I2C device can be reduced, the data access efficiency is improved, and the time of the CPU for processing other services is increased.
In the embodiment of the invention, the CPU can write data into the I2C device through the CPLD chip, and the access instruction is a writing instruction, wherein the writing instruction carries the data to be written.
Based on this, the manner that the CPU obtains the read-write result of the CPLD chip to the I2C device to be accessed through the SPI in the S302 can be realized in such a way that the CPU obtains the write result of the data to be written from the CPLD chip through the SPI. The writing result is used for indicating writing success or writing failure. Optionally, when the writing result is writing failure, the writing result may further include a cause of the writing failure.
In the embodiment of the invention, after the CPLD chip writes the data to be written into the I2C device, if the ACK message fed back by the I2C device is received within the appointed time period, the writing success is determined, or if the CPLD chip does not have the ACK message fed back by the I2C device within the appointed time period after the data to be written into the I2C device is written into the I2C device, the writing failure is determined.
After receiving the ACK message for indicating that the writing is successful, the CPLD chip stores the writing result for indicating that the writing is successful. And the CPLD chip stores a writing result for indicating writing failure if the ACK message for indicating writing success is not received within a specified time period after writing the data to be written into the I2C device. So that the CPU can acquire the writing result from the CPLD chip, and the reliability of data writing is improved.
When the CPU in the embodiment of the invention needs to write data into the register of the I2C device, a write instruction can be sent to the CPLD chip, the CPLD chip can complete the data write operation, and the CPU can process other services in the process of writing the data by the CPLD. Because the data transmission speed of SPI is far higher than that of I2C through SPI communication between CPU and CPLD chip, compared with the CPU directly writes data into I2C device through I2C interface, the embodiment of the invention can improve the data writing speed of CPU, avoid CPU unable to process other business because of writing data into I2C device.
In the embodiment of the invention, the CPU can read the data from the I2C device through the CPLD chip, and the access instruction is the read instruction at this time, and the mode that the CPU acquires the read-write result of the CPLD chip to the I2C device to be accessed through the SPI in the S302 can be realized in such a way that the CPU acquires the data to be read from the CPLD chip through the SPI. The data to be read is data read from a register corresponding to a register address in the I2C device to be accessed through the I2C analog interface by the CPLD chip.
The data to be read belongs to the read result of the CPLD chip to be accessed I2C device. The reading result is used for indicating the success or failure of reading, and when the reading result is the success of reading, the reading result comprises the data to be read out by the CPLD chip. When the reading result is the reading failure, the reading result also comprises a failure reason.
In the embodiment of the invention, if the CPLD chip can read the data to be read from the I2C device, the CPLD chip can determine that the reading is successful, and the CPLD chip can store the reading result which is used for indicating that the reading is successful at the moment, and the reading result comprises the data to be read. Or if the CPLD chip cannot read the data to be read from the I2C device, namely after the reading signal is sent to the I2C device, if the ACK message fed back by the I2C signal is not received within the appointed time period, the CPLD chip determines that the reading fails, and can store the reading result, wherein the reading result is used for indicating that the reading fails.
Accordingly, the CPU can acquire the read result from the CLPD chip through the SPI.
When the CPU in the embodiment of the invention needs to read data from the register of the I2C device, a reading instruction can be sent to the CPLD chip, and the CPLD chip finishes the data reading work, so that the CPU can process other services. Because the data transmission speed of SPI is far higher than that of I2C through SPI communication between CPU and CPLD chip, compared with CPU directly reading data through I2C interface, the embodiment of the invention can improve the reading speed, avoid CPU unable to process other business because of reading data in I2C device.
In another embodiment of the present invention, when there are multiple access instructions, the CPU may send the multiple access instructions to the CPLD chip through the SPI, so that the CPLD chip performs, through the I2C analog interface, read-write operations on the I2C device to which each access instruction is directed, and stores the read-write results of each read-write operation.
Accordingly, the step of obtaining, by the CPU in S302, the read-write result of the CPLD chip to the I2C device to be accessed through the SPI may be implemented as follows:
the CPU obtains the read-write result of the CPLD chip to the I2C device aimed at by each access instruction through SPI.
Therefore, after the CPU sends a plurality of access instructions to the CPLD chip, other services can be continuously processed, after the CPLD chip finishes the read-write operation of the I2C devices aimed at by the plurality of access instructions, the CPU can read a plurality of read-write results from the CPLD chip at one time, and compared with the CPU accessing each I2C device through each I2C interface, the embodiment of the invention can reduce the occupation of CPU resources and is equivalent to improving the data access efficiency of the CPU.
The embodiment of the invention also provides a data access method which is applied to the CPLD chip, wherein the CPLD chip is positioned in the exchanger shown in the figure 2. As shown in fig. 4, the method comprises the steps of:
S401, receiving an access instruction sent by the CPU through the SPI. Wherein the access instruction includes a physical address and a register address of the I2C device to be accessed.
The CPLD chip has a certain memory space, and part of the memory space of the CPLD chip can be used as a logic register of the CPLD chip. The CPU may access a logic register of the CPLD chip through a state machine of an internal logic code of the CPLD chip to send an access instruction to the CPLD chip.
S402, performing read-write operation on the I2C device to be accessed through the I2C analog interface based on the access instruction, and storing the read-write result so that the CPU can acquire the read-write result of the CPLD chip to be accessed through the SPI.
CPLD chip 202 includes a plurality of I/O pins, and for some of the I/O pins of CPLD chip 202, SCL signals and SDA signals transmitted by the I2C interface can be respectively simulated at two I/O pins of the CPLD chip through logic codes, so that the two I/O pins are simulated as one I2C interface.
According to the data access method provided by the embodiment of the invention, the CPU is connected with the CPLD chip through the SPI, and the CPLD chip is connected with the I2C device through the I2C analog interface. When the CPU needs to access the I2C device, an access instruction is sent to the CPLD chip through the SPI, and the CPLD chip performs read-write operation on the I2C device based on the access instruction. Because the process of accessing the I2C device is executed by the CPLD chip, the CPU only needs to send an access instruction to the CPLD chip through the SPI, and when the CPLD chip performs read-write operation on the I2C device, the CPU can process other services. And because the SPI speed is higher than the I2C bus speed, the CPU obtains the read-write result from the CPLD chip through the SPI, compared with the prior art that the CPU accesses the I2C device through the I2C interface, the occupation of the CPU time for accessing the I2C device can be reduced, the data access efficiency is improved, and the time of the CPU for processing other services is increased.
In the embodiment of the invention, when the CPU needs to write data into the I2C device, the access instruction is a write instruction, and the access instruction carries the data to be written. Referring to fig. 5, the CPLD chip in S402 performs read-write operation on the I2C device to be accessed through the I2C analog interface based on the access instruction, and stores the read-write result, which may be implemented by the following steps:
s501, address signals are sent to each I2C device connected with the CPLD chip through an I2C analog interface of the CPLD chip. Wherein the address signals comprise the physical address of the I2C device to be accessed.
S502, receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface.
The confirmation message is sent when the physical address in the confirmation address signal is the same as the physical address of the I2C device to be accessed after the address signal is received. The acknowledgement message may be an ACK message.
S503, through an I2C analog interface between the I2C devices to be accessed, writing the data to be written into a register corresponding to the register address in the I2C devices to be accessed.
S504, receiving a write response sent by the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed, and storing a write result of data to be written based on the write response.
The writing result is used for indicating writing success or writing failure.
In the embodiment of the invention, after the CPLD chip writes the data to be written into the I2C device, if the ACK message fed back by the I2C device is received within the appointed time period, the write success is determined, or if the CPLD chip does not receive the ACK message fed back by the I2C device within the appointed time period after the data to be written into the I2C device is written into the I2C device, the write failure is determined. After receiving the ACK message for indicating that the writing is successful, the CPLD chip stores the writing result for indicating that the writing is successful. And the CPLD chip stores a writing result for indicating writing failure if the ACK message for indicating writing success is not received within a specified time period after writing the data to be written into the I2C device.
When the CPU in the embodiment of the invention needs to write data into the register of the I2C device, a write instruction can be sent to the CPLD chip, the CPLD chip can complete the data write operation, and the CPU can process other services in the process of writing the data by the CPLD. Because the data transmission speed of SPI is far higher than that of I2C through SPI communication between CPU and CPLD chip, compared with the CPU directly writes data into I2C device through I2C interface, the embodiment of the invention can improve the data writing speed of CPU, avoid CPU unable to process other business because of writing data into I2C device.
In the embodiment of the invention, when the CPU needs to read data from the I2C device, the access instruction is a read instruction. Referring to fig. 6, the CPLD chip in S402 performs read-write operation on the I2C device to be accessed through the I2C analog interface based on the access instruction, and stores the read-write result, which may be implemented by the following steps:
s601, address signals are sent to all I2C devices connected with the CPLD chip through an I2C analog interface of the CPLD chip. Wherein the address signals comprise the physical address of the I2C device to be accessed.
S602, receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface.
And after the I2C device to be accessed receives the address signal, the confirmation message is sent under the condition that the physical address in the confirmation address signal is the same as the physical address of the I2C device to be accessed. The acknowledgement message may be an ACK signal.
S603, reading data to be read from a register corresponding to a register address in the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed.
S604, storing the data to be read so that the CPU can acquire the data to be read from the CPLD chip through the SPI.
In the embodiment of the invention, the CPU can read the data to be read once from the CPLD chip every a period of time, so that the condition that the CPU reads the data to be read for many times is reduced, the occupation of CPU resources is reduced, and meanwhile, the management efficiency of the I2C bus is improved, thereby improving the operation efficiency of the switch.
In the switch, if an error occurs in the I2C bus of the CPU during data access (for example, the CPU does not receive a response of the I2C device during data reading from the I2C device or data writing to the I2C device), the I2C bus is suspended, and after the I2C bus is recovered, the CPU can continue to access the I2C device.
The conventional method for recovering the I2C bus is that the CPU continuously transmits 9 high level signals through the GPIO pin, i.e., the CPU continuously sets the GPIO pin to high level 9 times. When a special circuit on a single board where the CPU is located monitors 9 continuous high-level signals sent by the GPIO pins, SCL clock signals of the I2C bus are continuously pulled down for 9 times to recover the I2C bus.
This way of recovering the I2C bus requires adding additional special circuitry on the board, which increases both the complexity of recovering the I2C bus and the hardware cost of the switch.
In the embodiment of the invention, the mode of recovering the I2C bus connected with the CPLD chip comprises continuously pulling down the SCL clock signal of the appointed I2C analog interface for 9 times if a recovery command of the CPU to the appointed I2C analog interface is received through the SPI bus. The I2C analog interface is designated as the I2C analog interface with errors.
And the CPU acquires a read-write result from the CPLD chip, if the read-write result is used for indicating the read-write failure, the CPU sends a recovery command to the CPLD chip through the SPI, and after receiving the recovery command, the CPLD simulates the I2C bus through the internal logic code and continuously pulls down an SCL clock signal of the appointed I2C simulation interface for 9 times so as to recover the I2C bus.
Therefore, the embodiment of the invention directly utilizes the CPLD chip to recover the I2C bus, and because the CPLD chip is self-contained in the switch single board, the embodiment of the invention does not need to add extra hardware in the switch to recover the I2C bus, thereby reducing the hardware cost of the switch.
Based on the same inventive concept, corresponding to the above method embodiment, the embodiment of the present invention provides a data access device, which is applied to a CPU, where the CPU is located in the switch shown in fig. 2, as shown in fig. 7, and includes a writing module 701 and an obtaining module 702;
The writing module 701 is configured to send an access instruction to the CPLD chip through the SPI, where the access instruction includes a physical address and a register address of the I2C device to be accessed, so that the CPLD chip performs a read-write operation on the I2C device to be accessed through the I2C analog interface based on the access instruction, and obtains a read-write result;
the obtaining module 702 is configured to obtain, through the SPI, a read-write result of the CPLD chip to the I2C device to be accessed.
Optionally, the access instruction is a write instruction, where the write instruction carries data to be written, and the obtaining module 702 is specifically configured to:
And acquiring a writing result of the data to be written from the CPLD chip through the SPI, wherein the writing result is used for indicating the success or failure of writing.
Optionally, the access instruction is a read instruction, and the obtaining module 702 is specifically configured to:
and acquiring data to be read from the CPLD chip through the SPI, wherein the data to be read is the data read from a register corresponding to the register address in the I2C device to be accessed through the I2C analog interface by the CPLD chip.
Based on the same inventive concept, corresponding to the method embodiment, the embodiment of the invention provides a data access device, which is applied to a CPLD chip, wherein the CPLD chip is located in the switch of the embodiment. As shown in fig. 8, the apparatus includes a receiving module 801 and an accessing module 802;
A receiving module 801, configured to receive, through an SPI, an access instruction sent by a CPU, where the access instruction includes a physical address and a register address of an I2C device to be accessed;
the access module 802 is configured to perform read-write operation on the I2C device to be accessed through the I2C analog interface based on the access instruction, and store the read-write result, so that the CPU obtains the read-write result of the CPLD chip on the I2C device to be accessed through the SPI.
Optionally, the access instruction is a write instruction, where the write instruction carries data to be written, and the access module 802 is specifically configured to:
Through an I2C analog interface of the CPLD chip, address signals are sent to all I2C devices connected with the CPLD chip, and the address signals comprise physical addresses of the I2C devices to be accessed;
receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, wherein the confirmation message is sent under the condition that the physical address in the confirmation address signal is the same as the physical address of the I2C device to be accessed after the confirmation message receives the address signal;
Writing data to be written into a register corresponding to a register address in the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and the I2C analog interface;
And receiving a writing response sent by the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed, and storing a writing result of data to be written based on the writing response, wherein the writing result is used for indicating writing success or writing failure.
Optionally, the access instruction is a read instruction;
The access module 802 is specifically configured to:
Through an I2C analog interface of the CPLD chip, address signals are sent to all I2C devices connected with the CPLD chip, and the address signals comprise physical addresses of the I2C devices to be accessed;
receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, wherein the confirmation message is sent under the condition that the physical address in the confirmation address signal is the same as the physical address of the I2C device to be accessed after the confirmation message receives the address signal;
Reading data to be read from a register corresponding to a register address in the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and the register address;
and storing the data to be read so that the CPU can acquire the data to be read from the CPLD chip through the SPI.
Optionally, the device further comprises a pull-down module;
And the pulling-down module is used for continuously pulling down the SCL clock signal of the appointed I2C analog interface for 9 times if a recovery command of the CPU to the appointed I2C analog interface is received through the SPI bus.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments in part.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.

Claims (9)

1.一种交换机,其特征在于,包括:中央处理器CPU、复杂可编程逻辑器件CPLD芯片和多个集成电路总线I2C器件;1. A switch, characterized by comprising: a central processing unit CPU, a complex programmable logic device CPLD chip and a plurality of integrated circuit bus I2C devices; 所述CPU通过串行外设接口SPI与所述CPLD芯片连接;所述CPLD芯片包括多个I2C模拟接口,每个I2C模拟接口通过两个I/O管脚模拟实现;所述CPLD芯片包括的每个I2C模拟接口与不同的I2C器件连接;The CPU is connected to the CPLD chip via a serial peripheral interface SPI; the CPLD chip includes a plurality of I2C analog interfaces, each of which is implemented by two I/O pins; each of the I2C analog interfaces included in the CPLD chip is connected to a different I2C device; 所述CPU用于通过所述SPI向所述CPLD芯片发送访问指令;The CPU is used to send an access instruction to the CPLD chip through the SPI; 所述CPLD芯片用于基于所述访问指令通过I2C模拟接口对I2C器件进行读写操作;The CPLD chip is used to perform read and write operations on the I2C device through the I2C analog interface based on the access instruction; 所述CPLD芯片的第一I2C模拟接口连接于多个物理地址不同的I2C器件;和/或,所述CPLD芯片的第二I2C模拟接口连接于模拟开关,所述模拟开关连接于多个物理地址相同的I2C器件,所述模拟开关用于选择开启或关闭与所述模拟开关连接的各I2C器件的访问通道;The first I2C analog interface of the CPLD chip is connected to a plurality of I2C devices with different physical addresses; and/or, the second I2C analog interface of the CPLD chip is connected to an analog switch, the analog switch is connected to a plurality of I2C devices with the same physical address, and the analog switch is used to select to open or close the access channel of each I2C device connected to the analog switch; 当访问指令存在多个时,所述CPU具体用于通过SPI向CPLD芯片发送多个访问指令;所述CPLD芯片具体用于通过I2C模拟接口,分别对每个访问指令所针对的I2C器件进行读写操作,并存储各读写操作的读写结果。When there are multiple access instructions, the CPU is specifically used to send multiple access instructions to the CPLD chip through SPI; the CPLD chip is specifically used to perform read and write operations on the I2C device targeted by each access instruction through the I2C analog interface, and store the read and write results of each read and write operation. 2.根据权利要求1所述的交换机,其特征在于,2. The switch according to claim 1, characterized in that: 所述CPU包括I2C接口,所述CPU通过I2C接口与指定I2C器件连接;或者,The CPU includes an I2C interface, and the CPU is connected to a specified I2C device via the I2C interface; or, 所述CPLD芯片的其中一个I2C模拟接口与所述指定I2C器件相连。One of the I2C analog interfaces of the CPLD chip is connected to the designated I2C device. 3.根据权利要求2所述的交换机,其特征在于,所述指定I2C器件包括电源和风扇。3 . The switch according to claim 2 , wherein the designated I2C device comprises a power supply and a fan. 4.一种数据访问方法,其特征在于,应用于CPU,所述CPU位于权利要求1-3任一项所述的交换机中,所述方法包括:4. A data access method, characterized in that it is applied to a CPU, the CPU is located in the switch according to any one of claims 1 to 3, and the method comprises: 所述CPU通过SPI向CPLD芯片发送访问指令,所述访问指令包括待访问I2C器件的物理地址和寄存器地址,以使得所述CPLD芯片基于所述访问指令通过I2C模拟接口,对所述待访问I2C器件进行读写操作,得到读写结果;The CPU sends an access instruction to the CPLD chip through the SPI, wherein the access instruction includes a physical address and a register address of the I2C device to be accessed, so that the CPLD chip performs a read and write operation on the I2C device to be accessed through the I2C analog interface based on the access instruction to obtain a read and write result; 所述CPU通过所述SPI获取所述CPLD芯片对所述待访问I2C器件的读写结果。The CPU obtains the reading and writing results of the CPLD chip on the I2C device to be accessed through the SPI. 5.根据权利要求4所述的方法,其特征在于,所述访问指令为写入指令,所述写入指令携带待写入数据;5. The method according to claim 4, characterized in that the access instruction is a write instruction, and the write instruction carries the data to be written; 所述CPU通过所述SPI获取所述CPLD芯片对所述待访问I2C器件的读写结果,包括:The CPU obtains the reading and writing results of the CPLD chip on the I2C device to be accessed through the SPI, including: 所述CPU通过所述SPI从所述CPLD芯片中获取对所述待写入数据的写入结果,所述写入结果用于表示写入成功或写入失败。The CPU obtains a writing result of the data to be written from the CPLD chip through the SPI, and the writing result is used to indicate a writing success or a writing failure. 6.根据权利要求4所述的方法,其特征在于,所述访问指令为读取指令;所述CPU通过所述SPI获取所述CPLD芯片对所述待访问I2C器件的读写结果,包括:6. The method according to claim 4, characterized in that the access instruction is a read instruction; the CPU obtains the read and write results of the CPLD chip on the I2C device to be accessed through the SPI, comprising: 所述CPU通过所述SPI从所述CPLD芯片中获取待读取数据,所述待读取数据为所述CPLD芯片通过I2C模拟接口从所述待访问I2C器件中,所述寄存器地址对应的寄存器中读取的数据。The CPU obtains the data to be read from the CPLD chip through the SPI, and the data to be read is the data read from the register corresponding to the register address in the I2C device to be accessed by the CPLD chip through the I2C analog interface. 7.一种数据访问方法,其特征在于,应用于CPLD芯片,所述CPLD芯片位于权利要求1-3任一项所述的交换机中,所述方法包括:7. A data access method, characterized in that it is applied to a CPLD chip, the CPLD chip is located in the switch according to any one of claims 1 to 3, and the method comprises: 通过SPI接收CPU发送的访问指令,所述访问指令包括待访问I2C器件的物理地址和寄存器地址;Receive an access instruction sent by the CPU through the SPI, wherein the access instruction includes a physical address and a register address of the I2C device to be accessed; 基于所述访问指令通过I2C模拟接口,对所述待访问I2C器件进行读写操作,并存储读写结果,以便所述CPU通过所述SPI获取所述CPLD芯片对所述待访问I2C器件的读写结果。Based on the access instruction, the I2C device to be accessed is read and written through the I2C analog interface, and the read and write results are stored, so that the CPU can obtain the read and write results of the CPLD chip on the I2C device to be accessed through the SPI. 8.根据权利要求7所述的方法,其特征在于,所述访问指令为写入指令,所述写入指令携带待写入数据;8. The method according to claim 7, characterized in that the access instruction is a write instruction, and the write instruction carries the data to be written; 所述基于所述访问指令通过I2C模拟接口,对所述待访问I2C器件进行读写操作,并存储读写结果,包括:The step of performing read and write operations on the I2C device to be accessed through the I2C analog interface based on the access instruction and storing the read and write results includes: 通过所述CPLD芯片的I2C模拟接口,向所述CPLD芯片连接的各I2C器件发送地址信号,所述地址信号包括所述待访问I2C器件的物理地址;Sending an address signal to each I2C device connected to the CPLD chip through the I2C analog interface of the CPLD chip, wherein the address signal includes a physical address of the I2C device to be accessed; 接收待访问I2C器件通过I2C模拟接口向所述CPLD发送的确认消息,所述确认消息为所述待访问I2C器件接收到所述地址信号后,在确认所述地址信号中的物理地址与自身的物理地址相同的情况下发送的;Receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, wherein the confirmation message is sent by the I2C device to be accessed after receiving the address signal and confirming that the physical address in the address signal is the same as the physical address of the device itself; 通过与所述待访问I2C器件之间的I2C模拟接口,将所述待写入数据写入所述待访问I2C器件中所述寄存器地址对应的寄存器;Writing the data to be written into a register corresponding to the register address in the I2C device to be accessed through an I2C analog interface between the I2C device to be accessed and the register address; 通过与所述待访问I2C器件之间的I2C模拟接口,接收所述待访问I2C器件发送的写入响应,并基于所述写入响应存储对所述待写入数据的写入结果,所述写入结果用于表示写入成功或写入失败。A write response sent by the I2C device to be accessed is received through an I2C analog interface between the I2C device to be accessed, and a write result of the data to be written is stored based on the write response, wherein the write result is used to indicate a write success or a write failure. 9.根据权利要求7所述的方法,其特征在于,所述访问指令为读取指令;所述基于所述访问指令通过I2C模拟接口,对所述待访问I2C器件进行读写操作,并存储读写结果,包括:9. The method according to claim 7, wherein the access instruction is a read instruction; and performing read and write operations on the I2C device to be accessed through an I2C analog interface based on the access instruction and storing the read and write results comprises: 通过所述CPLD芯片的I2C模拟接口,向所述CPLD芯片连接的各I2C器件发送地址信号,所述地址信号包括所述待访问I2C器件的物理地址;Sending an address signal to each I2C device connected to the CPLD chip through the I2C analog interface of the CPLD chip, wherein the address signal includes a physical address of the I2C device to be accessed; 接收待访问I2C器件通过I2C模拟接口向所述CPLD发送的确认消息,所述确认消息为所述待访问I2C器件接收到所述地址信号后,在确认所述地址信号中的物理地址与自身的物理地址相同的情况下发送的;Receiving a confirmation message sent by the I2C device to be accessed to the CPLD through the I2C analog interface, wherein the confirmation message is sent by the I2C device to be accessed after receiving the address signal and confirming that the physical address in the address signal is the same as the physical address of the device itself; 通过与所述待访问I2C器件之间的I2C模拟接口,从所述待访问I2C器件中,所述寄存器地址对应的寄存器中读取待读取数据;Reading the data to be read from the register corresponding to the register address in the I2C device to be accessed through the I2C analog interface between the device and the I2C device to be accessed; 存储所述待读取数据,以便所述CPU通过所述SPI从所述CPLD芯片中获取所述待读取数据。The data to be read is stored so that the CPU can obtain the data to be read from the CPLD chip through the SPI.
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