CN107331295B - Display panel - Google Patents

Abstract

A display panel includes a substrate, a plurality of data lines, a plurality of gate lines, a power line, and a gate driving circuit. The power line is coupled to a voltage source. The gate driving circuit is arranged in a visible area of the display panel, coupled to the gate line and the power line, and generates a plurality of gate driving signals according to a start pulse. The gate line is formed by a first metal layer located on the substrate, the data line is formed by a second metal layer located above the first metal layer, the power line is formed by a third metal layer located above the second metal layer, and at least one projection area of the data line on the substrate overlaps with a projection area of the power line on the substrate.

Description

display panel

technical field

The present invention relates to a display panel, in particular to a display panel with a gate driving circuit arranged in a visible area.

Background technique

In a general display, the driving circuit is an important driving element. In the traditional technology, a driver chip is used as the driver circuit of the panel. In recent years, an integrated gate driver circuit (Integrated Gate Driver) has been developed. The gate driver circuit is fabricated on a panel. This technology is also collectively referred to as a gate driver on panel (GOP for short).

Since the development of the GOP technology, the general practice is to integrate the GOP circuit in the border areas on both sides of the substrate. However, this practice will occupy the border space on both sides of the panel, so that the border has a considerable width. For products such as mobile communication devices, wearable devices, and automotive central control panels, the design of extremely narrow bezels and non-rectangular panels has gradually become a product trend. Therefore, if a narrow bezel and a non-rectangular design must be implemented on the display module , the general traditional method of designing the GOP circuit on the frame will have certain limitations and difficulties.

Therefore, a novel circuit design and layout is required to meet the design requirements of extremely narrow bezels.

SUMMARY OF THE INVENTION

The invention discloses a display panel comprising a plurality of data lines, a plurality of gate lines, a power supply line and a gate drive circuit. The power line is coupled to a voltage source. The gate driving circuit is arranged in a visible area of the display panel, is coupled to the gate line and the power supply line, and generates a plurality of gate driving signals according to a start pulse. The gate lines are formed by a first metal layer on a substrate, the data lines are formed by a second metal layer above the first metal layer, the power lines are formed by a third metal layer above the second metal layer, And a projection area of at least one of the data lines on the substrate overlaps with a projection area of the power line on the substrate.

The invention further discloses a display panel, which includes a plurality of gate lines, a plurality of clock signal lines and a gate driving circuit. The clock signal line is used for providing a plurality of clock signals. The gate driving circuit is arranged in a visible area of the display panel, is coupled to the gate line and the clock signal line, and generates a plurality of gate driving signals according to a start pulse. The gate line and the clock signal line are formed by a first metal layer on a substrate, and the gate line and the clock signal line are parallel.

The invention further discloses a display panel, which includes a plurality of data lines, a plurality of gate lines, a plurality of clock signal lines, a power supply line and a gate driving circuit. The clock signal line is used for providing a plurality of clock signals. The power line is coupled to a voltage source. The gate driving circuit is arranged in a visible area of the display panel, is coupled to the gate line, the clock signal line and the power supply line, and generates a plurality of gate driving signals according to a start pulse. The gate lines and the clock signal lines are formed by a first metal layer, and the gate lines are parallel to the clock signal lines, the data lines are formed by a second metal layer, and the power lines are formed by a third metal layer.

Description of drawings

FIG. 1 is a block diagram showing a display device according to an embodiment of the present invention.

FIG. 2 is a diagram showing the structure of a gate driving circuit disposed in the visible area of the display panel according to the embodiment of the first aspect of the present invention.

FIG. 3 is a top view showing an example of an electronic device according to an embodiment of the present invention.

FIG. 4 is a block diagram showing a first-stage driving unit according to an embodiment of the first aspect of the present invention.

FIG. 5 is a circuit diagram showing the several-stage driving unit according to the first embodiment of the first aspect of the present invention.

FIG. 6 is a diagram showing signal waveforms according to an embodiment of the present invention.

FIG. 7 is a top view showing the layout of a block of a pixel matrix according to an embodiment of the present invention.

8A is a perspective view showing the layout of a block of a pixel matrix according to an embodiment of the present invention.

8B is a cross-sectional view showing the layout of the driving unit circuit area in the visible area of the display panel according to an embodiment of the present invention.

FIG. 9A is a top view showing an example of an electronic device according to an embodiment of the present invention.

9B is a cross-sectional view showing the layout of the non-driving unit circuit area in the visible area of the display panel according to an embodiment of the present invention.

FIG. 10A is a circuit diagram showing a several-stage driving unit according to the second embodiment of the first aspect of the present invention.

FIG. 10B is a circuit diagram showing a several-stage driving unit according to the third embodiment of the first aspect of the present invention.

FIG. 11A is a schematic diagram showing a gate driving circuit and a clock signal according to a fourth embodiment of the first aspect of the present invention.

FIG. 11B is a diagram showing signal waveforms according to the fourth embodiment of the first aspect of the present invention.

FIG. 12 is a block diagram illustrating an n-th stage driving unit according to an embodiment of the second aspect of the present invention.

FIG. 13A is a circuit diagram showing a several-stage driving unit according to the first embodiment of the second aspect of the present invention.

13B is a diagram showing signal waveforms according to the first embodiment of the second aspect of the present invention.

FIG. 14A is a circuit diagram showing a several-stage driving unit according to the second embodiment of the second aspect of the present invention.

FIG. 14B is a diagram showing signal waveforms according to the second embodiment of the second aspect of the present invention.

FIG. 15A is a circuit diagram showing a several-stage driving unit according to a third embodiment of the second aspect of the present invention.

FIG. 15B is a circuit diagram showing the several-stage driving unit according to the fourth embodiment of the second aspect of the present invention.

FIG. 16A is a diagram showing signal waveforms according to the sixth embodiment of the second aspect of the present invention.

FIG. 16B is a diagram showing another signal waveform according to the sixth embodiment of the second aspect of the present invention.

FIG. 16C is a diagram showing yet another signal waveform according to the sixth embodiment of the second aspect of the present invention.

FIG. 17 is a diagram showing the structure of a gate driving circuit disposed in the visible area of the display panel according to another embodiment of the present invention.

FIG. 18 is a top view showing the layout of a block of a pixel matrix according to another embodiment of the present invention.

FIG. 19A is a diagram showing exemplary waveforms of the clock signal and the gate driving signal when the parasitic capacitance is small.

FIG. 19B is a diagram showing example waveforms of the clock signal and the gate driving signal when the parasitic capacitance is large.

FIG. 20 is a diagram showing the structure of the gate driving circuit according to the first embodiment of the third aspect of the present invention.

FIG. 21 is a diagram showing signal waveforms according to the first embodiment of the third aspect of the present invention.

FIG. 22 shows an example of the ripple of the gate drive signal.

【Symbol Description】

100～display device;

101～display panel;

102～input unit;

110～gate drive circuit;

120～Data drive circuit;

130～pixel matrix;

140～control chip;

200, 200', 1700, AA ~ visual area;

200-1, 200-2, 200-3, 210, 220, 2201 ~ ripple;

310, 320 ~ drive unit circuit area;

500, 1500, GOP, GOP_E, GOP_F, GOP_M ~ drive unit;

501, 1501 ~ pull-up control circuit;

502, 1502 ~ pull-up output circuit;

503, 1503 ~ pull-down control circuit;

504, 1504-1, 1504-2 ~ pull-down output circuit;

Active~semiconductor active layer;

BP1, BP2, BP3 ~ insulating layer;

Cb(n), Cb(n+1), Cccom, Ccp, Cxcg, Cxcv～capacitor;

CE ~ common electrode;

CK, CK1, CK2, CK3, CK4, CK5, CKA, CKB, CKC, CKD, CKA_E, CKB_E, CKA_F, CKB_F, CKA_M, CKB_M, CLK~clock signal line;

DL, DL(1), DL(2), DL(3), DL(4), DL(5), DL(6) ~ data lines;

GE~gate;

GI ~ gate dielectric layer;

GL, GL(1), GL(2), GL(3), GL(4), GL(n-1), GL(n), GL(n+1) ~ gate line;

M1, M2, M3 ~ metal layer;

GOUT～gate drive signal; PFA～planarization layer;

PE ~ pixel electrode;

RESET~reset signal;

SD ~ source/drain;

STV, STV1, STV2 ~ start pulse;

T1(n), T1(n+1), T2(n), T2(n+1), T3(n), T3(n+1), T4(n-1), T4(n), T4( n+1), T4a(n), T4a(n+1)～transistor;

VSS ~ power cord.

Detailed ways

In order to make the above-mentioned and other objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail in conjunction with the accompanying drawings.

FIG. 1 is a block diagram showing a display device according to an embodiment of the present invention. As shown in the figure, the display device 100 may include a display panel 101 , a data driving circuit 120 and a control chip 140 . The display panel 101 includes a gate driving circuit 110 and a pixel matrix 130 , wherein the gate driving circuit 110 is arranged in the pixel matrix 130 . The pixel matrix 130 includes a plurality of pixel units, and each pixel unit is coupled to a set of staggered gate lines and data lines. The gate driving circuit 110 is used for generating corresponding gate driving signals on a plurality of gate lines to drive the pixel units. The data driving circuit 120 is used for generating corresponding data driving signals on a plurality of data lines to provide image data to the pixel units. The control chip 140 is used for generating a plurality of timing signals, including a clock signal, a reset signal, and a start pulse.

In addition, the display device 100 may further include an input unit 102 . The input unit 102 is used for receiving the image signal and outputting it to the control chip 140 . According to an embodiment of the present invention, the display device 100 can be applied to an electronic device, wherein the electronic device has various embodiments, including: a mobile phone, a digital camera, a personal digital assistant, a mobile computer, a desktop A computer, a television, a car monitor, a portable CD player, or any device that includes an image display function.

It should be noted that, in some embodiments of the present invention, the data driving circuit of the display device may be integrated into the control chip 140 . In these embodiments, image data may be provided to pixel matrix 130 through control chip 140 . Therefore, the architecture shown in FIG. 1 is only one of various embodiments of the present invention, and is not intended to limit the scope of the present invention.

Generally speaking, a display panel includes a visible area (Active Area, AA) and a frame area (Frame Area). According to an embodiment of the present invention, the gate driving circuit 110 is disposed within the visible area of the display panel 101 . The various gate driving circuits proposed by the present invention will be described in more detail below.

According to the first aspect of the present invention, all elements of the gate driving circuit 110 are arranged within the viewable area of the display panel 101 .

FIG. 2 is a diagram showing the structure of a gate driving circuit disposed in the visible area of the display panel according to the embodiment of the first aspect of the present invention. As shown in the figure, the gate driving circuit may include a plurality of driving units GOP disposed within the visible area (AA) 200 of the display panel. The gate driving circuit is coupled to at least one power line and at least two clock signal lines, wherein the power line is coupled to the voltage source VSS for providing the reference voltage VGL required by the system, and the clock signal line is coupled to the clock source , for providing at least two clock signals CKA and CKB. The gate driving circuit receives the start pulse STV and the reset signal RESET through the signal line, and generates a plurality of gate driving signals in response to the start pulse STV, and then the last stage driving unit GOP is turned off by the reset signal RESET.

According to an embodiment of the present invention, the driving units GOP may form a matrix, wherein one driving unit may be disposed between a plurality of data lines. Therefore, the layout of one driving unit can span several pixel units. For example, in an embodiment of the present invention, as shown in FIG. 5 , one driving unit can be arranged between 6 data lines, so the layout of one driving unit can span 5 pixel units. In other words, according to an embodiment of the present invention, for a row of pixel units of the pixel matrix, the number of driving units configured therein is less than the number of data lines of the display panel. It should be noted that, in other embodiments of the present invention, one driving unit may also be arranged between more than 6 or less than 6 data lines, so the present invention is not limited to any one embodiment.

FIG. 3 is a top view showing an example of an electronic device according to an embodiment of the present invention, wherein the areas 310 and 320 framed by dotted lines represent the driving unit circuit regions of the gate driving circuit, which may correspond to FIG. 2 The shown driving unit circuit areas 210 and 220 are used to illustrate the relative positions of the two column driving units in the gate driving circuit on the visible area of the panel of the electronic device.

According to an embodiment of the present invention, the gate driving circuit disposed in the visible area of the display panel may include N-level driving units, where N is a positive integer. FIG. 4 is a block diagram illustrating an n-th stage driving unit according to an embodiment of the present invention, wherein n is a positive integer and 0<n≦N. The driving unit 500 may include a pull-up control circuit 501, a pull-up output circuit 502, a pull-down control circuit 503, and a pull-down output circuit 504, wherein the pull-up output circuit 502 and the pull-down output circuit 504 are coupled to the nth gate line GL(n ) to control the output of the gate drive signal. As shown in FIG. 4 , all the elements of the driving unit 500 are arranged in the visible area of the display panel, and the signal lines are arranged in the frame area of the display panel.

In the embodiment of the first aspect of the present invention, since there are only signal traces left in the frame areas on both sides, the design requirements of extremely narrow frame and non-rectangular panel design requirements can be met.

FIG. 5 is a circuit diagram showing the several-stage driving unit according to the first embodiment of the first aspect of the present invention. For the sake of simplicity, FIG. 5 only shows a part of a column driving unit of the gate driving circuit, wherein the column driving unit, such as the transistors T1(n), T1(n+1), T2( n), T2(n+1), T3(n), T3(n+1), T4(n-1) and T4(n), and capacitors Cb(n) and Cb(n+1), are set at Between the data lines DL( 1 ) to DL( 6 ), the data lines DL( 1 ) to DL( 6 ) are only used for illustration, but not to limit the scope of the present invention.

The transistor T1 corresponds to the pull-up output circuit of the driving unit shown in FIG. 4 , the transistor T2 corresponds to the pull-up control circuit of the driving unit shown in FIG. 4 , and the transistor T3 corresponds to the pull-down control of the driving unit shown in FIG. 4 . circuit, the transistor T4 corresponds to the pull-down output circuit of the drive unit as shown in FIG. 4 . It should be noted that the pull-up output circuit, the pull-up control circuit, the pull-down control circuit, and the pull-down output circuit in the first embodiment of the first aspect are illustrated by each including one transistor, but in other embodiments, the aforementioned circuits also Each of them may include more than one transistor.

According to an embodiment of the present invention, the n-th stage driving unit may include transistors T1(n), T2(n), T3(n), T4(n) and a capacitor Cb(n). The transistor T1(n) has a first electrode coupled to the clock signal line CKA, and a second electrode coupled to the nth gate line GL(n). The transistor T2(n) has a control electrode and a first electrode coupled to the (n-1)th gate line GL(n-1), and a second electrode coupled to the control electrode of the transistor T1(n) . The transistor T3(n) has a control electrode coupled to the (n+1)th gate line GL(n+1), a first electrode coupled to the second electrode of the transistor T2(n), and a second electrode The pole is coupled to the power line VSS. The transistor T4(n) has a control electrode coupled to the clock signal line CKB, a first electrode coupled to the nth gate line GL(n), and a second electrode coupled to the power supply line VSS.

FIG. 6 is a diagram showing signal waveforms according to an embodiment of the present invention. When the gate pulse on the gate line GL(n-1) arrives, the transistor T2(n) is turned on, thereby turning on the transistor T1(n). When the clock pulse on the clock signal line CKA arrives, it will be transmitted to the gate line GL(n) through the turned-on transistor T1(n) and output as a gate pulse. When the gate pulse on the gate line GL(n+1) arrives, the transistor T3(n) is turned on, pulling down the voltage of the gate of the transistor T1(n) to turn off the transistor T1(n). Likewise, when the clock pulse on the clock signal line CKB arrives, the transistor T4(n) is turned on, pulling down the voltage of the nth gate line GL(n).

As shown in FIG. 5 , the driving units at all levels only include 4 transistors. Compared with the traditional design, the driving unit requires at least 13 transistors. The gate driving circuit proposed in the present invention can effectively reduce the pixel aperture ratio in the visible area. Loss.

In addition, in the embodiment of the present invention, in order to further reduce the loss of the pixel aperture ratio in the visible area, the layout of the circuit signal lines in the visible area can also be further designed.

According to the first embodiment of the present invention, the gate lines of the display panel are formed by a first metal layer, the data lines are formed by a second metal layer, and the power lines coupled to the voltage source VSS are formed by a third metal layer, wherein The first metal layer is formed on a substrate, the second metal layer is formed on the first metal layer, and the third metal layer is formed on the second metal layer, wherein the substrate can be a rigid substrate or a flexible substrate. Since the data lines and the power lines are formed in different metal layers, the data lines and the power lines can overlap spatially (ie, a projection area of the data lines and the power lines can overlap), thereby reducing the loss of pixel aperture ratio. Furthermore, according to the first embodiment of the present invention, the clock signal line is formed of the first metal layer and is parallel to the gate line. Contacts between different metal layers can be connected by contact vias.

7 is a top view of the layout of a block of a pixel matrix according to an embodiment of the present invention, in which the clock signal line CK may represent any clock signal line according to the present invention, for example, the above-mentioned clock signal Any one of the lines CKA and CKB, and the data line DL may represent any of the data lines described in the present invention, for example, any one of the above-mentioned data lines D( 1 ) to D( 6 ). As shown in the figure, the clock signal line CK is parallel to the gate lines GL(n), GL(n+1), etc., and the data line DL overlaps with a projection area of the power supply line VSS (so the same line is used in FIG. 7 to represent data line DL and power line VSS).

As shown in FIG. 7 , because no signal line passes through the pixel electrode opening area, not only a higher aperture ratio can be obtained, but also the aperture ratio between pixel units can be kept consistent, avoiding the appearance of picture quality similar to vertical lines. bad condition.

8A is a perspective view showing the layout of a block of a pixel matrix according to an embodiment of the present invention. PE is the pixel electrode, and CE is the common electrode. As shown in FIG. 8A , in the design of the present invention, the layout of the clock signal line CLK does not overlap with the pixel electrode PE, so the voltage of the pixel electrode will not have a coupling problem.

FIG. 8B is a layout cross-sectional view of the driving unit circuit area shown in the visible area of the display panel, which is a layout cross-sectional view along the tangent line from point A to point A' shown in FIG. 8A . As shown in FIG. 8B , each metal layer is sequentially formed on the substrate, wherein GE is the gate line formed on the first metal layer, GI is the gate dielectric layer (Gate Insulator), and SD is formed on the second metal layer The source/drain of the transistor, Active is the semiconductor active layer, BP1, BP2 and BP3 are the insulating layers, PFA is the planarization layer, PE is the pixel electrode, M3 is the third metal layer, CE is the common electrode, and the pixel electrodes PE and The material of the common electrode CE is a transparent conductive oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), fluorine doped tin oxide (FTO), aluminum doped Zinc oxide (aluminum dopedzinc oxide, AZO), gallium doped zinc oxide (gallium doped zinc oxide, GZO). According to an embodiment of the present invention, since the power line coupled to the voltage source VSS is formed by the third metal layer, the third metal layer is used to transmit the voltage signal of the voltage source VSS in the driving unit circuit region.

It should be noted that the layout stacking method shown in FIG. 8B is only one of various embodiments of the present invention, and is used to illustrate the concept of the present invention, but not to limit the scope of the present invention.

In addition, the setting of the third metal layer can also be matched with the application of in-cell touch technology (touch in cell), and the third metal layer is used to connect the common electrode CE to transmit touch sensing signals, thereby improving product applicability and added value .

FIG. 9A is a top view showing an example of an electronic device according to an embodiment of the present invention. 9B is a cross-sectional view showing the layout of the non-driving unit circuit area in the visible area of the display panel according to an embodiment of the present invention. As shown in FIG. 9A , the common electrode CE can be used as a touch sensing electrode in the visible area of the display panel to sense changes in capacitance. As shown in FIG. 9B , with the arrangement of the third metal layer, in the non-driving unit circuit region, the third metal layer M3 is connected to the common electrode CE through the contact hole.

As described above, in the first embodiment of the present invention, the clock signal line is formed of the first metal layer and is parallel to the gate line. In other embodiments of the present invention, the clock signal lines may also be formed of other metal layers.

According to the second embodiment of the present invention, the gate lines of the display panel are formed by the first metal layer M1, the data lines are formed by the second metal layer M2, the power lines coupled to the voltage source VSS are formed by the third metal layer M3, and The clock signal line may instead be formed of the second metal layer M2 and be parallel to the data line.

FIG. 10A is a circuit diagram showing a several-stage driving unit according to the second embodiment of the first aspect of the present invention. For simplicity of description, FIG. 10A only shows a part of a column driving unit of the gate driving circuit, and the data lines DL( 1 ) to DL( 6 ) are only used for illustration, but not for limiting the scope of the present invention.

As shown in the figure, the clock signal lines CKA and CKB are arranged in parallel and spaced apart from the data lines.

In addition, according to the third embodiment of the present invention, the gate lines of the display panel are formed by the first metal layer M1, the data lines are formed by the second metal layer M2, and the power lines coupled to the voltage source VSS are formed by the third metal layer M3 , and the clock signal line may be formed by the third metal layer M3 instead, and overlap with the data line.

FIG. 10B is a circuit diagram showing a several-stage driving unit according to the third embodiment of the first aspect of the present invention. For simplicity of description, FIG. 10B only shows a part of a column of driving units of the gate driving circuit, and the data lines DL( 1 ) to DL( 6 ) are only used for illustration, but not for limiting the scope of the present invention.

As shown in the figure, the clock signal lines CKA and CKB are arranged in parallel and spaced apart from the power lines coupled to the voltage source VSS, and overlap with the data lines. It is worth noting that, in order to show the connection points between the transistor and the clock signal line and the transistor and the power supply line, the data line and the power supply line, or the overlapping data line and the clock signal in FIG. 5 , FIG. 10A and FIG. 10B are arranged. Lines are drawn separately. However, it must be understood that when the data lines and the power lines, or the data lines and the clock signal lines are formed in different metal layers, their wirings may overlap in space, so that the projected areas thereof are as shown in FIG. 7 and FIG. 8B overlapping. In addition, it is worth noting that in other embodiments of the present invention, the wirings of the data lines, power lines and clock signal lines of different metal layers may or may not overlap in space, so the layout of the present invention is not limited to the above Example.

According to the fourth embodiment of the present invention, the number of clock signals can be further increased to reduce the duty cycle of the transistors in the driving unit.

FIG. 11A is a schematic diagram showing a gate driving circuit according to a fourth embodiment of the first aspect of the present invention. As shown in the figure, the driving units of all levels in the gate driving circuit can be respectively coupled to the clock signal lines CKA, CKB, CKC and CKD, and can continue to cycle in this order.

FIG. 11B is a diagram showing signal waveforms according to the fourth embodiment of the first aspect of the present invention. As shown in the figure, after the start pulse STV arrives, the clock signal lines CKA, CKB, CKC and CKD provide non-overlapping clock pulses in sequence, and the clock pulses will be sequentially sent from the gate lines GL(1), GL(2) , GL(3) and GL(4) outputs, compared with the embodiments shown in FIG. 5 and FIG. 6 , the duty cycle of the transistors (eg, transistors T1 and T4 ) in the driving unit can be reduced from 50% to 25%. In this way, the time during which the transistor elements in the driving unit are biased can be reduced, thereby effectively increasing the reliability of the circuit.

As described above, in the first aspect of the present invention, all elements of the gate driving circuit 110 are disposed within the visible area of the display panel 101 . In the second aspect of the present invention, some elements of the gate driving circuit 110 may be disposed in the frame area of the display panel 101 .

FIG. 12 is a block diagram showing an n-th stage driving unit according to an embodiment of the second aspect of the present invention, wherein n is a positive integer and 0<n≦N. The driving unit 1500 may include a pull-up control circuit 1501, a pull-up output circuit 1502, a pull-down control circuit 1503, and pull-down output circuits 1504-1 and 1504-2, wherein the pull-up output circuit 1502 and the pull-down output circuits 1504-1 and 1504-2 It is coupled to the nth gate line GL(n) for controlling the output of the gate driving signal. As shown in FIG. 12 , the pull-down output circuits 1504-1 and 1504-2 and the signal lines of the driving unit 1500 are arranged in the frame area of the display panel.

13A is a circuit diagram showing a several-stage driving unit according to the first embodiment of the second aspect of the present invention, wherein the transistor T1 corresponds to the pull-up output circuit of the driving unit shown in FIG. 12 , and the transistor T2 corresponds to the In the pull-up control circuit of the driving unit shown in FIG. 12 , the transistor T3 corresponds to the pull-down control circuit of the driving unit shown in FIG. 12 , and the transistors T4 and T4a correspond to the pull-down output circuit of the driving unit shown in FIG. 12 . It should be noted that the pull-up output circuit, the pull-up control circuit, the pull-down control circuit, and the pull-down output circuit in the first embodiment of the second aspect are illustrated by each including one transistor, but in other embodiments, the aforementioned circuits also Each of them may include more than one transistor. For simplicity of illustration, FIG. 13A only shows a part of a column driving unit of the gate driving circuit, wherein a part of the elements of the column driving unit, such as the transistors T1(n) and T1(n+1) shown in the figure , T2(n), T2(n+1), T3(n), T3(n+1), and capacitors Cb(n) and Cb(n+1), which are arranged on the data lines DL(1)~DL( 5), and other components, such as transistors T4(n), T4(n+1), T4a(n) and T4a(n+1), are arranged in the frame area. The data lines DL( 1 ) to DL( 5 ) are only used for illustration, rather than limiting the scope of the present invention.

According to an embodiment of the present invention, the n-th stage driving unit may include transistors T1(n), T2(n), T3(n), T4(n), T4a(n) and a capacitor Cb(n). The coupling manner of the transistors T1(n)-T3(n) is the same as that of the embodiment shown in FIG. 5, and details are not described herein again. In this embodiment, the transistor T4(n) has a control electrode coupled to the clock signal line CK1, a first electrode coupled to the nth gate line GL(n), and a second electrode coupled to the power supply line VSS, and transistor T4a(n) is coupled in the same manner as transistor T4(n).

13B is a diagram showing signal waveforms according to the first embodiment of the second aspect of the present invention. When the gate pulse on the gate line GL(n-1) arrives, the transistor T2(n) is turned on, thereby turning on the transistor T1(n). When the clock pulse on the clock signal line CKA arrives, it will be transmitted to the gate line GL(n) through the turned-on transistor T1(n) and output as a gate pulse. When the gate pulse on the gate line GL(n+1) arrives, the transistor T3(n) is turned on, pulling down the voltage of the gate of the transistor T1(n) to turn off the transistor T1(n). Likewise, when the clock pulse on the clock signal line CK1 arrives, the transistors T4(n) and T4a(n) are turned on, pulling down the voltage of the nth gate line GL(n).

It is worth noting that, although two clock signal lines CK1 and CK2 are newly added in FIG. 13A to provide clock signals to the transistors T4(n) and T4a(n) disposed in the border area, the present invention is not limited to this . In other embodiments of the present invention, the transistors T4(n) and T4a(n) disposed in the frame region can also be coupled to the clock signal line CKB as shown in FIGS. 14A , 15A and 15B. In other words, in other embodiments of the present invention, the transistors disposed in the frame area and the transistors disposed in the visible area may be coupled to the same clock signal line.

Like the first embodiment of the first aspect of the present invention, in the first embodiment of the second aspect of the present invention, the clock signal line is formed of the first metal layer M1, and as shown in FIG. 13A, within the visible area parallel to the gate line. In other embodiments of the present invention, the clock signal lines may also be formed of other metal layers.

FIG. 14A is a circuit diagram showing a several-stage driving unit according to the second embodiment of the second aspect of the present invention. 14A is similar to the circuit shown in FIG. 13A, the difference is only that the transistors T4(n) and T4a(n) arranged in the frame area are coupled to the clock signal line CKB, and the transistor T4(n+1) arranged in the frame area is connected to the clock signal line CKB. and T4a(n+1) are coupled to the clock signal line CKA. FIG. 14B is a diagram showing signal waveforms according to the second embodiment of the second aspect of the present invention. It is worth noting that the signal waveform shown in FIG. 14B can also be shared by the circuits of FIG. 15A and FIG. 15B .

In the third embodiment of the second aspect of the present invention, the gate lines of the display panel are formed by the first metal layer M1, the data lines are formed by the second metal layer M2, and the power lines coupled to the voltage source VSS are formed by the third metal layer The layer M3 is formed, and the clock signal lines may instead be formed of the second metal layer M2 and are parallel to the data lines.

FIG. 15A is a circuit diagram showing a several-stage driving unit according to a third embodiment of the second aspect of the present invention. For simplicity of description, FIG. 15A only shows a part of a column driving unit of the gate driving circuit, and the data lines DL( 1 ) to DL( 5 ) are only used for illustration, but not for limiting the scope of the present invention.

As shown in the figure, the clock signal lines CKA/CKB are arranged in parallel and spaced apart from the data lines.

In addition, in the fourth embodiment of the second aspect of the present invention, the gate lines of the display panel are formed by the first metal layer M1, the data lines are formed by the second metal layer M2, and the power lines coupled to the voltage source VSS are formed by the third metal layer M2. The metal layer M3 is formed, and the clock signal line may instead be formed of the third metal layer M3 and overlap with the data line.

FIG. 15B is a circuit diagram showing the several-stage driving unit according to the fourth embodiment of the second aspect of the present invention. For simplicity of illustration, FIG. 15B only shows a part of a column driving unit of the gate driving circuit, and the data lines DL( 1 ) to DL( 5 ) are only used for illustration, but not for limiting the scope of the present invention.

As shown in the figure, the clock signal lines CKA/CKB are arranged in parallel and spaced apart from the power lines coupled to the voltage source VSS, and overlap with the data lines. It is worth noting that, in order to show the connection points between the transistor and the clock signal line and the transistor and the power supply line, the data lines and the power supply lines or the overlapping data lines in FIG. 13A , FIG. 14A , FIG. 15A and FIG. 15B Drawn separately from the clock signal lines. However, it must be understood that when the data lines and the power lines, or the data lines and the clock signal lines are formed in different metal layers, their wirings may overlap in space, so that the projected areas thereof are as shown in FIG. 7 and FIG. 8B overlapping. In addition, it is worth noting that in other embodiments of the present invention, the wirings of the data lines, power lines and clock signal lines of different metal layers may or may not overlap in space, so the layout of the present invention is not limited to the above Example.

In addition, in the fifth embodiment of the second aspect of the present invention, the number of clock signals in the visible area can also be increased to more than two as shown in FIG. 11A to reduce the duty cycle of the transistors in the visible area.

In addition, in the sixth embodiment of the second aspect of the present invention, when the elements disposed in the frame area and the elements disposed in the visible area of the driving unit are coupled to different clock signal lines as shown in FIG. The number of clock signals of the elements disposed in the frame area can be further increased to reduce the duty cycle of the transistors in the frame area.

FIG. 16A is a signal waveform diagram according to the sixth embodiment of the second aspect of the present invention, which is an embodiment in which one more clock signal line CK3 is added to the first embodiment of the second aspect shown in FIG. 13A . As shown in the figure, the clock signal lines CK1, CK2 and CK3 sequentially provide non-overlapping clock pulses to the transistors T4 and T4a of different stages. Therefore, compared with the embodiment shown in FIG. 13B, the transistors ( For example, the duty cycle of transistors T4 and T4a) can be reduced from 50% to 33%.

FIG. 16B is a diagram showing another signal waveform according to the sixth embodiment of the second aspect of the present invention. This embodiment adds two more clock signal lines CK3 to the first embodiment of the second aspect shown in FIG. 13A . Example with CK4. As shown in the figure, the clock signal lines CK1, CK2, CK3 and CK4 sequentially provide non-overlapping clock pulses to the transistors T4 and T4a of different stages. Therefore, compared with the embodiment shown in FIG. The duty cycle of the transistors (eg, transistors T4 and T4a) can be reduced from 50% to 25%.

16C is a diagram showing yet another signal waveform according to the sixth embodiment of the second aspect of the present invention. This embodiment adds three additional clock signal lines CK3 to the first embodiment of the second aspect shown in FIG. 13A , Examples of CK4 and CK5. As shown in the figure, the clock signal lines CK1, CK2, CK3, CK4 and CK5 sequentially provide non-overlapping clock pulses to the transistors T4 and T4a of different stages. Therefore, compared with the embodiment shown in FIG. The duty cycle of the region's transistors (eg, transistors T4 and T4a) can be reduced from 50% to 20%.

Therefore, according to the sixth embodiment of the second aspect of the present invention, the time during which the transistor elements in the frame region are biased can be reduced, effectively increasing the reliability of the circuit.

Example shown above. For example, although the layout of the clock signal lines CKA and CKB in the visible area 200 in FIG. 2 is horizontal, and the layout of the power lines VSS in the visible area 200 is vertical, the present invention is not limited thereto.

FIG. 17 is a diagram showing the structure of a gate driving circuit disposed in the visible area of the display panel according to another embodiment of the present invention. As shown in the figure, in this embodiment, the layout of the clock signal lines CKA and CKB in the visible area 200 is vertical, and the layout of the power lines VSS in the visible area 200 is horizontal.

However, whether it is connected to the driving unit GOP by extending horizontally or vertically into the visible area, it cannot be avoided that the clock signal will be affected by the parasitic capacitance in the visible area, resulting in insufficient driving capability, which in turn causes the gate line output signal to be seriously attenuated. .

FIG. 18 is a top view showing the layout of a block of a pixel matrix according to another embodiment of the present invention. As shown in the figure, the interleaved clock signal lines CLKA/CLKB and the power supply line VSS will form a parasitic capacitance Cxcv, the interleaved clock signal lines CLKA/CLKB and the gate line will form a parasitic capacitance Cxcg, and the clock signal lines CLKA/CLKB pass through the opening area A parasitic capacitance Ccp is generated with the pixel electrode, and a parasitic capacitance Cccom is formed with the common electrode between the clock signal lines CLKA/CLKB through the opening area. When the panel resolution is higher, the formed parasitic capacitance is larger, resulting in poorer clock signal driving capability.

FIG. 19A is a diagram showing exemplary waveforms of the clock signal and the gate driving signal when the parasitic capacitance is small. FIG. 19B is a diagram showing example waveforms of the clock signal and the gate driving signal when the parasitic capacitance is large. As shown in the figure, when the parasitic capacitance is large, the driving capability of the clock signal will be deteriorated, thereby causing serious distortion of the gate driving signal.

In order to solve the above problems, in the third aspect of the present invention, a novel clock signal routing structure and a novel clock signal timing configuration method are proposed to disperse the influence of parasitic capacitance on the clock signal.

According to the embodiment of the third aspect of the present invention, the driving unit circuit in the visible area can be divided into a plurality of areas, such as the above-mentioned driving unit circuit area. The division of the circuit area is not limited to vertical or horizontal division. The circuit configuration of each driving unit circuit area has a dedicated clock signal line to drive the corresponding driving unit. For example, in an embodiment of the present invention, the first driving unit circuit area and the second driving unit circuit area in the visible area are driven by different groups of clock signal lines.

FIG. 20 is a diagram showing the structure of the gate driving circuit according to the first embodiment of the third aspect of the present invention. In this embodiment, the driving unit circuit in the visible area 200' is divided into three areas: front, middle and rear. For example, the driving unit circuit area 200-1 marked in the figure includes the front driving unit GOP_F, the driving unit The circuit area 200-2 includes the middle-stage driving unit GOP_M and the driving unit circuit area 200-3 includes the rear-stage driving unit GOP_E. Each driving unit circuit area is driven with a different clock signal. For example, the driving unit circuit area 200-1 is driven by the first group of clock signals CKA_F and CKB_F, the driving unit circuit area 200-2 is driven by the second group of clock signals CKA_M and CKB_M, and the driving unit circuit area 200-3 is driven by the third group of clock signals The signals CKA_E and CKB_E are driven to evenly distribute the parasitic capacitance among the three groups of clock signal lines.

FIG. 21 is a diagram showing signal waveforms according to the first embodiment of the third aspect of the present invention. According to the concept of the third aspect of the present invention, different groups of clock signals are configured in different driving unit circuit areas, and the timing control chip is used to provide time-sharing clock signals, which can effectively reduce the parasitic capacitance felt by the clock signal line. one third.

More specifically, different groups of clock signals are allocated to output clock pulses at different times, so as to drive the driving units in the corresponding driving unit circuit regions. Taking the architecture shown in FIG. 20 as an example, the three groups of clock signals will output clock pulses at different times in a time-sharing manner as shown in FIG. 21 . The clock signals CKA_E and CKB_E will output clock pulses in the period when the driving unit circuit area 200 - 3 needs to operate. At this time, the clock signals CKA_M and CKB_M and the states of CKA_F and CKB_F are not output. For example, the voltage levels of the clock signals CKA_M and CKB_M and CKA_F and CKB_F are pulled down to the level of the reference voltage VGL. When the driving units of all levels in the driving unit circuit area 200-3 are completed in sequence, the driving units of all levels in the driving unit circuit area 200-2 will operate in sequence. At this time, the clock signals CKA_M and CKB_M will output clock pulses, and the states of the clock signals CKA_E and CKB_E will be converted to no output. For example, the voltage levels of the clock signals CKA_E and CKB_E and CKA_F and CKB_F are pulled down to the level of the reference voltage VGL. When the driving units of all levels in the driving unit circuit area 200-2 are completed in sequence, the driving units of all levels in the driving unit circuit area 200-1 will operate in sequence. At this time, the clock signals CKA_F and CKB_F will output clock pulses, and the states of the clock signals CKA_M and CKB_M will be converted to no output. For example, the voltage levels of the clock signals CKA_E and CKB_E and CKA_M and CKB_M are pulled down to the level of the reference voltage VGL. As a result, the parasitic capacitance felt by the clock signal line is only one-third of the original.

It should be noted that, although in the above-mentioned embodiments, the driving unit circuit is divided into three regions in order to clearly illustrate the concept of the present invention, the present invention is not limited thereto. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention, for example, dividing the driving unit circuit into two regions, or more than three regions. In addition, the division method of the driving unit circuit is not limited to the above-mentioned front, middle, rear or left, middle and right division.

In addition, it should be noted that although in the above-mentioned embodiment, each driving unit circuit area is coupled to two clock signal lines to receive the corresponding clock signal, the present invention is not limited to this. In other embodiments of the present invention, each driving unit circuit area can also be respectively coupled to more than two clock signal lines as shown in FIG. 11A , for example, the driving unit GOP shown in FIG. 11A can be regarded as the same driving unit circuit The driving units in the area are respectively coupled to the clock signal lines CKA, CKB, CKC and CKD, and can continue to cycle in this order to reduce the duty cycle of the transistors in the visible area.

In addition, it is worth noting that the concept introduced in the third aspect of the present invention is not only applicable to all the elements of the gate driving circuit introduced in the embodiments of the first aspect of the present invention are arranged in the visible area of the display panel The structure can also be applied to the structure of arranging some elements of the gate driving circuit in the frame area of the display panel described in the embodiment of the second aspect of the present invention, including the structure shown in FIG. The embodiment structure in which the transistors and the transistors arranged in the visible area are coupled to different clock signal lines, as shown in Figures 14A, 15A and 15B, the transistors arranged in the border area and the transistors arranged in the visible area are Embodiment architectures coupled to the same clock signal lines, and the embodiment architectures shown in Figures 16A, 16B, and 16C that increase the number of clock signals provided to elements disposed in the bezel area.

In other words, in the clock signal timing configuration method proposed in the third aspect of the present invention, combined with the partition configuration of each group of clock signals and the technology of distributing the clock signals of each group to output clock pulses at different times, each group of clock signals only In the driving unit circuit area that it is responsible for, it has output when it needs to operate, and maintains its voltage at the level of the reference voltage VGL during the rest of the time and does not output. In this way, not only can the parasitic capacitance felt by the clock signal line be effectively reduced, but also power consumption can be saved, and the time during which the transistor elements in the driving unit are biased can be reduced, thereby effectively increasing the reliability of the circuit. In addition, the time when the clock signal is not output can also avoid unnecessary ripple on the gate drive signal. For example, when the gate driving signal GOUT as shown in FIG. 22 does not need to generate a pulse, the ripple 2201 can be avoided due to the clock pulse output of the clock signal line CLK.

The use of ordinal numbers such as "first", "second", "third", etc., which are used to modify elements in the claims do not in themselves imply any priority, order of precedence, order between elements, or method performance The order of the steps is used only as an indicator to distinguish different elements with the same name (with different ordinal numbers).

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention The scope defined by the appended claims shall prevail.

Claims (15)

1. A display panel, comprising:

a substrate;

a plurality of data lines;

a plurality of gate lines;

the power line is coupled with a voltage source;

a gate driving circuit disposed in a visible area of the display panel, coupled to the gate lines and the power line, and generating gate driving signals according to a start pulse; and

a plurality of clock signal lines coupled to the gate driving circuit for providing a plurality of clock signals,

wherein the plurality of gate lines are formed of a first metal layer on the substrate, the plurality of data lines are formed of a second metal layer over the first metal layer, the power supply line is formed of a third metal layer over the second metal layer, and a projection area of at least one of the plurality of data lines on the substrate overlaps with a projection area of the power supply line on the substrate, and wherein the plurality of clock signal lines are formed of the first metal layer and are parallel to the plurality of gate lines, and the gate driving circuit is disposed between one of the plurality of gate lines and one of the plurality of clock signal lines.

2. The display panel of claim 1, wherein the plurality of clock signal lines are formed of the third metal layer, the plurality of clock signal lines are parallel to the power supply line, and a projected area of at least one of the plurality of data lines on the substrate overlaps with a projected area of at least one of the plurality of clock signal lines on the substrate.

3. The display panel of claim 1, wherein the gate driving circuit comprises N-stage driving units, and wherein the nth-stage driving unit comprises:

a first transistor having a first electrode coupled to the first clock signal line and a second electrode coupled to the nth gate line;

a second transistor having a control electrode and a first electrode coupled to the (n-1) th gate line, and a second electrode coupled to the control electrode of the first transistor; and

a third transistor having a control electrode coupled to the (n +1) th gate line, a first electrode coupled to the second electrode of the second transistor, and a second electrode coupled to the power line,

where N and N are positive integers and 0< N ≦ N.

4. The display panel of claim 3, wherein the nth stage driving unit further comprises:

a fourth transistor having a control electrode coupled to the second clock signal line, a first electrode coupled to the nth gate line, and a second electrode coupled to the power line.

5. The display panel of claim 3, further comprising:

a fourth transistor having a control electrode coupled to the second clock signal line, a first electrode coupled to the nth gate line, and a second electrode coupled to the power line,

wherein the fourth transistor is disposed in a frame region of the display panel.

6. A display panel, comprising:

a plurality of gate lines;

a plurality of clock signal lines for providing a plurality of clock signals; and

a gate driving circuit disposed in a visible area of the display panel, coupled to the gate lines and the clock signal lines, and generating gate driving signals according to a start pulse,

wherein the gate line and the plurality of clock signal lines are formed of a first metal layer on a substrate, and the plurality of gate lines are parallel to the plurality of clock signal lines, and the gate driving circuit is disposed between one of the plurality of gate lines and one of the plurality of clock signal lines.

7. The display panel of claim 6, further comprising:

a substrate;

the power line is coupled with a voltage source; and

a plurality of data lines for transmitting data signals,

wherein the plurality of data lines are formed of a second metal layer located above the first metal layer, the power line is formed of a third metal layer located above the second metal layer, and a projection area of at least one of the plurality of data lines on the substrate overlaps with a projection area of the power line on the substrate.

8. The display panel of claim 7, wherein the gate driving circuit comprises N-stage driving units, and wherein the nth-stage driving unit comprises:

a first transistor having a first electrode coupled to the first clock signal line and a second electrode coupled to the nth gate line;

a second transistor having a control electrode and a first electrode coupled to the (n-1) th gate line, and a second electrode coupled to the control electrode of the first transistor; and

a third transistor having a control electrode coupled to the (n +1) th gate line, a first electrode coupled to the second electrode of the second transistor, and a second electrode coupled to the power line,

where N and N are positive integers and 0< N ≦ N.

9. The display panel of claim 8, wherein the nth stage driving unit further comprises:

a fourth transistor having a control electrode coupled to the second clock signal line, a first electrode coupled to the nth gate line, and a second electrode coupled to the power line.

10. The display panel of claim 7, further comprising:

a fourth transistor having a control electrode coupled to the second clock signal line, a first electrode coupled to the nth gate line, and a second electrode coupled to the power line,

wherein the fourth transistor is disposed in a frame region of the display panel.

11. A display panel, comprising:

a plurality of data lines;

a plurality of gate lines;

a plurality of clock signal lines for providing a plurality of clock signals;

the power line is coupled with a voltage source; and

a gate driving circuit disposed in a visible area of the display panel, coupled to the gate lines, the clock signal lines and the power line, and generating gate driving signals according to a start pulse,

wherein the plurality of gate lines and the plurality of clock signal lines are formed of a first metal layer, and the plurality of gate lines are parallel to the plurality of clock signal lines, the plurality of data lines are formed of a second metal layer, the power supply line is formed of a third metal layer, and the gate driving circuit is disposed between one of the plurality of gate lines and one of the plurality of clock signal lines.

12. The display panel of claim 11, wherein the first metal layer is formed on a substrate, the second metal layer is formed over the first metal layer, and the third metal layer is formed over the second metal layer, and a projection area of at least one of the plurality of data lines on the substrate overlaps a projection area of the power line on the substrate.

13. The display panel of claim 11, wherein the gate driving circuit comprises N-stage driving units, and wherein the nth-stage driving unit comprises:

a first transistor having a first electrode coupled to the first clock signal line and a second electrode coupled to the nth gate line;

a second transistor having a control electrode and a first electrode coupled to the (n-1) th gate line, and a second electrode coupled to the control electrode of the first transistor; and

a third transistor having a control electrode coupled to the (n +1) th gate line, a first electrode coupled to the second electrode of the second transistor, and a second electrode coupled to the power line,

where N and N are positive integers and 0< N ≦ N.

14. The display panel of claim 13, wherein the nth stage driving unit further comprises:

a fourth transistor having a control electrode coupled to the second clock signal line, a first electrode coupled to the nth gate line, and a second electrode coupled to the power line.

15. The display panel of claim 13, further comprising:

a fourth transistor having a control electrode coupled to the second clock signal line, a first electrode coupled to the nth gate line, and a second electrode coupled to the power line,

wherein the fourth transistor is disposed in a frame region of the display panel.

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