CN104503177A - Array substrate, manufacturing method thereof and display panel - Google Patents

Abstract

The invention discloses an array substrate, a manufacturing method thereof, and a display panel, including a plurality of gate lines, a plurality of data lines, and a plurality of drive leads, wherein the gate lines correspond to the drive leads one by one; the data Lines and the driving lead wires are arranged in a spacer; two adjacent data lines and two adjacent gate lines enclose a pixel area; the pixel area includes a thin film transistor and a pixel electrode; the pixel electrode and the One of the drain or the source of the thin film transistor is connected; the gate line is connected with the gate of the thin film transistor; the gate line is connected with the driving lead, and the driving lead is used to connect The driving signal generated by the gate driving circuit is transmitted to the gate line; the data line is connected to the other of the source or the drain of the thin film transistor. The invention improves the aperture ratio of the display.

Description

Array substrate, manufacturing method thereof, and display panel

technical field

The present invention relates to the field of electronic equipment, in particular to an array substrate, a manufacturing method thereof, and a display panel.

Background technique

Thin Film Transistor Liquid Crystal Display (TFT-LCD) is currently widely used in mobile phones, handheld computers and other portable devices due to its advantages such as low power consumption, low operating voltage, no X-ray radiation, high definition, and small size. in electronic products. Driven by market competition, thin-film transistor liquid crystal displays with lighter weight, better display effect and lower price are becoming more and more popular. The gate drive technology that integrates the amorphous silicon gate driver with the active matrix can reduce the number of TFT-LCDs by one driver chip, which can effectively make the display lighter, reduce costs, and increase the reliability of the display. .

Therefore, in recent years, gate drive technology has gradually become a hot spot in development and research. However, at present, the gate drive circuit in most displays is designed in the frame part, which occupies a large position of the frame. In order to narrow the frame of the display, the gate drive circuit can be designed below the display area (that is, the step area ) to reduce the size of the border, or even achieve no border. This method requires additional driving wires to connect the scanning signal of the gate drive to the gate lines. Due to the introduction of the driving wires, how to ensure the aperture ratio of the display is a problem that needs to be paid attention to. Therefore, there is an urgent need for an array substrate that can increase the aperture ratio of a display.

Contents of the invention

Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display panel, which are used to solve the problem of low aperture ratio of narrow-frame or frameless displays.

In order to achieve the above purpose, an embodiment of the present invention provides an array substrate, including:

A plurality of gate lines, a plurality of data lines and a plurality of drive leads, the gate lines correspond to the drive leads one by one; the data lines and the drive leads are arranged in separate layers; two adjacent data lines A pixel area is surrounded by two adjacent gate lines;

The pixel area includes a thin film transistor and a pixel electrode;

The pixel electrode is connected to one of the drain or the source of the thin film transistor;

The gate line is connected to the gate of the thin film transistor; the gate line is connected to the driving lead, and the driving lead is used to transmit the driving signal generated by the gate driving circuit to the gate Wire;

The data line communicates with the other of the source or the drain of the thin film transistor.

Preferably, the centerline of the projection of the data lines on the array substrate completely overlaps the centerline of the projection of the driving leads on the array substrate.

Preferably, the projection of the data lines on the array substrate partially overlaps the projection of the driving leads on the array substrate.

Preferably, the projections of the data lines on the array substrate and the projections of the driving leads on the array substrate do not overlap.

Preferably, the gate line communicates with the driving lead through a first connection hole.

Preferably, the data line is in the same layer as the source and drain of the thin film transistor.

Preferably, the array substrate further includes a light-shielding layer, and the light-shielding layer is on the same layer as the driving leads.

Preferably, a buffer layer, a first insulating layer and a second insulating layer are sequentially arranged between the driving lead wire and the data line.

Preferably, the array substrate includes: a light-shielding layer, a buffer layer, a semiconductor layer, a first insulating layer, a gate, a second insulating layer, and the second connection hole, the third connection hole and the The source and drain of the semiconductor layer are connected.

The embodiment of the present invention also provides a method for manufacturing an array substrate, the method comprising:

providing a substrate;

disposing a first metal layer on the substrate and patterning a light-shielding layer and driving leads;

a buffer layer, a semiconductor layer, and a first insulating layer are sequentially arranged on the substrate, and a first connection hole penetrating through the first insulating layer and the buffer layer is formed on the driving lead;

disposing a second metal layer on the substrate and patterning a gate line, the gate line is connected to the driving lead through the first connection hole;

A second insulating layer and a third metal layer are sequentially arranged on the substrate, and a source electrode, a drain electrode, and a data line are patterned, and the data line is connected to one of the source electrode or the drain electrode;

A passivation layer and a transparent conductive layer are sequentially arranged on the substrate, and the transparent conductive layer is patterned to form a pixel electrode, and the pixel electrode communicates with the other of the drain electrode or the source electrode.

Preferably, the method further includes making a second connection hole and a third connection hole on the first insulating layer and the second insulating layer, and the source and the drain pass through the second connection hole and the third connection hole respectively. The third connection hole is connected to the semiconductor layer.

Preferably, the centerline of the projection of the data lines on the substrate completely overlaps the centerline of the projection of the driving leads on the substrate.

Preferably, the projection of the data lines on the substrate partially overlaps the projection of the driving leads on the substrate.

Preferably, the projections of the data lines on the substrate do not overlap with the projections of the driving leads on the substrate.

An embodiment of the present invention also provides a display panel, including the above-mentioned array substrate.

In the above embodiment, the array substrate includes a plurality of gate lines, a plurality of data lines, and a plurality of driving leads, and the gate lines are in one-to-one correspondence with the driving leads; the data lines are separated from the driving leads. Layer setting; two adjacent data lines and two adjacent gate lines form a pixel area; the pixel area includes a thin film transistor and a pixel electrode; the pixel electrode and the drain or source of the thin film transistor One of the poles is connected; the gate line is connected with the gate of the thin film transistor; the gate line is connected with the driving lead, and the driving lead is used to drive the gate drive circuit generated The signal is transmitted to the gate line; the data line is connected to the other of the source or the drain of the thin film transistor. In the embodiment of the present invention, the drive leads are placed under the data lines, and the projections of the drive leads on the array substrate and the projections of the data lines on the array substrate can partially overlap. The more overlapping parts, the greater the aperture ratio of the display, and the display The higher the pixels, the more obvious the aperture ratio will be improved.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings that need to be used in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For Those of ordinary skill in the art can also obtain other drawings based on these drawings without making creative efforts.

FIG. 1 is a schematic structural diagram of an array substrate in an embodiment of the present invention;

2a to 2d are structural schematic diagrams of an array substrate part and cross section in an embodiment of the present invention;

3a to 3c are structural schematic diagrams of another array substrate part and cross section in an embodiment of the present invention;

4a to 4c are structural schematic diagrams of another array substrate part and cross section in an embodiment of the present invention;

5 is a schematic flowchart of a method for manufacturing an array substrate in an embodiment of the present invention;

6a to 6f are schematic flowcharts of another manufacturing method of an array substrate in an embodiment of the present invention;

FIG. 7 is a display panel in an embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments . Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

An embodiment of the present invention provides an array substrate. FIG. 1 shows a schematic structural view of the array substrate, and FIGS. 103 overlaps with the data line 101 , and for the convenience of display, the data line 101 is omitted in FIG. 1 . Figure 2d shows a partial top view structure of an array substrate. In order to clearly show the embodiment of the present invention, the light shielding layer 106, the buffer layer 107, the first insulating layer 109, the second insulating layer 110 and the passivation layer are omitted in Figure 2d. layer 113, the specific structural positions of each film layer can be referred to in Figure 2a to Figure 2c, in order to more clearly show the connection relationship between the various structures, the intersection of the data line 101 and the gate line is treated transparently, which can be clearly seen from the figure A first connection hole 201 , a second connection hole 202 , a third connection hole 203 and a fourth connection hole 204 are shown. 2a to 2c are the cross-sections of three regions of part of the array substrate shown in Fig. 2d, which are the cross-sections of A-A'301, B-B'302 and C-C'303 respectively. The A-A' 301 area in the embodiment of the present invention is a cross section of the thin film transistor on the array substrate.

1 and 2a to 2d, the array substrate includes: a plurality of gate lines 102, a plurality of data lines 101 and a plurality of driving leads 103, and the gate lines 102 correspond to the driving leads 103 one by one The data line 101 and the driving lead wire 103 are arranged in a separate layer; two adjacent data lines 101 and two adjacent gate lines 102 form a pixel area 104; the pixel area 104 includes a thin film transistor and A pixel electrode 105; the pixel electrode 105 is connected to one of the drain 112 or the source 111 of the thin film transistor; the gate line 102 is connected to the gate 115 of the thin film transistor; the gate The line 102 communicates with the driving lead 103, and the driving lead 103 is used to transmit the driving signal generated by the gate drive circuit to the gate line 102; the data line 101 is connected to the source 111 of the thin film transistor Or another phase of the drain 112 is connected. As shown in FIG. 1 , each driving lead 103 corresponds to one gate line 102 , and is used to connect the gate line 102 with the gate driving circuit. In the embodiment of the present invention, the projection of the data line 101 on the array substrate and the projection of the driving lead 103 on the array substrate may partially overlap, completely overlap, or not overlap. The larger the ratio, the higher the pixels of the display, and the more obvious the improvement of the aperture ratio; thus, although the driving lead 103 is newly added, the aperture ratio will not be affected or the influence will be relatively small. FIG. 1 and FIG. 2a to FIG. 2d show the situation that the projection of the data line 101 on the array substrate completely overlaps the projection of the driving lead wire 103 on the array substrate.

Preferably, the projection centerline of the data line 101 on the array substrate completely overlaps the projection centerline of the driving lead 103 on the array substrate. As shown in FIGS. 2a to 2d, in this embodiment, the data lines 101 and the driving leads 103 are completely overlapped, and the data lines 101 and the driving leads 103 are in different layers, which can increase the aperture ratio of the display as much as possible. The higher the pixels of the display, the more obvious the increase in aperture ratio.

Preferably, the gate line 102 communicates with the driving lead 103 through the first connection hole 201 . The gate line 102 is connected to the driving lead 103 through a first connection hole 201 , as shown in FIG. 2 b .

Preferably, the data line 101 is in the same layer as the source 111 and the drain 112 of the TFT. In this embodiment, the data line 101 is connected to the source electrode 111 of the thin film transistor, and the source electrode 111 and the drain electrode 112 are simultaneously manufactured from the same material during the manufacturing process.

Preferably, the array substrate further includes a light-shielding layer 106 , and the light-shielding layer 106 is in the same layer as the driving leads 103 . As shown in the three regions A-A'301, B-B'302, and C-C'303 in Fig. In the area 303, the layer on the substrate 114 is the driving lead 103. During the manufacturing process, the light-shielding layer 106 and the driving lead 103 are manufactured at the same time, which can save a mask. At the same time, since the data lines 101 and the driving wires 103 are in different layers, the data lines 101 and the driving wires 103 can be overlapped to reduce shading and increase the aperture ratio of the display.

Preferably, a buffer layer 107 , a first insulating layer 109 and a second insulating layer 110 are sequentially provided between the driving leads 103 and the data lines 101 . The buffer layer 107 , the first insulating layer 109 and the second insulating layer 110 are used to isolate the driving lead 103 from the data line 101 .

Preferably, the array substrate includes: a light shielding layer 106, a buffer layer 107, a semiconductor layer 108, a first insulating layer 109, a gate 115, a second insulating layer 110, and 202 . The third connection hole 203 is connected to the source 111 and the drain 112 of the semiconductor layer 108 . Wherein, the gate 115 is connected to the gate line 102, the source 111 is connected to the data line 101, the drain 112 is connected to the pixel electrode 105, and the source 111 It communicates with the drain 112 through the semiconductor layer 108 . The buffer layer 107 is used to isolate the light shielding layer 106 from the semiconductor layer 108, the first insulating layer 109 is used to isolate the semiconductor layer 108 from the gate 115, and the second insulating layer 110 is used to for isolating the gate 115 from the source 111 and isolating the gate 115 from the drain 112 .

Preferably, Fig. 3a to Fig. 3c show another array substrate according to the embodiment of the present invention, wherein A-A'301 shown in Fig. 3c can be referred to Fig. 2a. The array substrate includes: a plurality of gate lines 102, a plurality of data lines 101 and a plurality of drive leads 103, the gate lines 102 correspond to the drive leads 103 one by one; the data lines 101 correspond to the drive leads 103; The lead wires 103 are arranged in separate layers; the projection of the data line 101 on the array substrate and the projection of the drive lead wire 103 on the array substrate do not overlap, and the projection of the data line 101 on the array substrate is not overlapped with the projection of the drive lead wire 103 on the array substrate. The projections on the array substrate are adjacent; two adjacent data lines 101 and two adjacent gate lines 102 form a pixel area 104; the pixel area 104 includes a thin film transistor and a pixel electrode 105; the pixel The electrode 105 is connected with the drain 112 of the thin film transistor; the gate line 102 is connected with the gate 115 of the thin film transistor; the gate line 102 is connected with the driving lead 103, and the driving The wire 103 is used to transmit the driving signal generated by the gate driving circuit to the gate line 102; the data line 101 is connected to the source 111 of the thin film transistor. As shown in Figure 1 and Figures 3a to 3c, the projection of the data line 101 on the array substrate and the projection of the driving lead 103 on the array substrate do not overlap, the data line 101 and the driving lead 103 in the B-B'302 and C-C'303 regions As shown, the data line 101 and the driving lead 103 do not overlap, and the data line 101 and the driving lead 103 are in different layers, which can reduce the parasitic capacitance between the data line 101 and the driving lead 103, and because the The projection of the data line 101 on the array substrate is adjacent to the projection of the driving lead 103 on the array substrate, which can reduce the shielding area of the black matrix. Therefore, compared with the prior art, the aperture ratio of the display can also be improved. The higher the pixels, the more obvious the aperture ratio will be improved.

Preferably, Fig. 4a to Fig. 4c show another array substrate according to the embodiment of the present invention, wherein A-A'301 shown in Fig. 4c can be referred to Fig. 2a. The array substrate includes: a plurality of gate lines 102, a plurality of data lines 101 and a plurality of drive leads 103, the gate lines 102 correspond to the drive leads 103 one by one; the data lines 101 correspond to the drive leads 103; Lead wires 103 are arranged in separate layers; the projection of the data line 101 on the array substrate partially overlaps the projection of the driving lead wire 103 on the array substrate; two adjacent data lines 101 and two adjacent gate lines 102 A pixel area 104 is enclosed; the pixel area 104 includes a thin film transistor and a pixel electrode 105; the pixel electrode 105 is connected to the drain 112 of the thin film transistor; the gate line 102 is connected to the gate of the thin film transistor The pole 115 is connected; the gate line 102 is connected with the drive lead 103, and the drive lead 103 is used to transmit the drive signal generated by the gate drive circuit to the gate line 102; the data line 101 It is connected with the source 111 of the thin film transistor. As shown in FIG. 1 and FIG. 4a to FIG. 4c, the projection of the data line 101 on the array substrate and the projection of the driving lead 103 on the array substrate partially overlap. The higher the aperture ratio is, the more obvious the improvement is, and at the same time, the parasitic capacitance generated between the data line 101 and the driving lead line 103 can be reduced.

FIG. 5 shows the flow of the manufacturing method of the array substrate, which can be used to make the above-mentioned array substrate, but is not limited to the array substrate provided in this embodiment. Specific steps of the described process include:

Step S501 , providing a substrate 114 .

Step S502 , disposing a first metal layer on the substrate 114 and patterning the light shielding layer 106 and the driving leads 103 .

In step S503, a buffer layer 107, a semiconductor layer 108, and a first insulating layer 109 are sequentially provided on the substrate 114, and a first connection hole penetrating through the first insulating layer 109 and the buffer layer is formed on the driving lead 201.

Step S504, disposing a second metal layer on the substrate 114 and patterning a gate line 102 and a gate 115, the gate line 102 is connected to the gate 115, and the gate line 102 passes through the The first connection hole 201 is connected to the driving lead 103 .

In step S505, the second insulating layer 110 and the third metal layer are sequentially arranged on the substrate 114, and the source electrode 111, the drain electrode 112, and the data line 101 are patterned, and the data line 101 is connected to the source electrode 111 or One of the drains 112 is connected. Wherein, the projection of the data line 101 on the substrate 114 and the projection of the driving lead 103 on the substrate 114 may partially overlap or may not overlap. The centerlines of the projections of the driving leads 103 on the substrate 114 are completely overlapped. The aperture ratio of the display can be improved, the more overlapping parts, the larger the aperture ratio of the display, the higher the pixels of the display, the more obvious the aperture ratio is improved, and the aperture ratio of the display can be maximized when the overlap is complete, when the When the projection of the data line 101 on the substrate 114 does not overlap with the projection of the driving lead 103 on the substrate 114 , reducing the parasitic capacitance between the data line 101 and the driving lead 103 is most obvious.

In step S505, it also includes: making a second connection hole 202 and a third connection hole 203 on the first insulating layer 109 and the second insulating layer 110, and the source electrode 111 and the drain electrode 112 respectively pass through the first insulating layer 109 and the second insulating layer 110. The second connection hole 202 and the third connection hole 203 are connected to the semiconductor layer 108 .

Step S506, sequentially disposing a passivation layer 113 and a transparent conductive layer on the substrate 114, and patterning the transparent conductive layer to form a pixel electrode 105, the pixel electrode 105 is connected to the other of the drain electrode 112 or the source electrode 111 Connected one by one.

In the step S506, when the common electrode is at the top, a first connection hole 201 is made on the passivation layer 113, and the pixel electrode 105 is connected to the drain electrode 112 through the fourth connection hole 204 pass; when the common electrode is in the middle position, make the fourth connection hole 204 on the passivation layer 113 and the second insulating layer 110, the pixel electrode 105 and the drain electrode 112 or the source electrode 111 The other one is connected.

In order to better explain the present invention, an embodiment of the present invention also provides a method for manufacturing an array substrate, which can be used for manufacturing the above-mentioned array substrate, but is not limited to the array substrate provided in this embodiment.

6a to 6f show the flow of the manufacturing method of the array substrate.

The manufacturing method includes: as shown in FIG. 6 a , providing a substrate 114 , the substrate 114 is usually a transparent glass substrate, and may also be other transparent substrates, such as a transparent plastic substrate. A first metal layer is formed on the substrate 114 , and photolithography is performed on the first metal layer to pattern the light shielding layer 106 and the driving lead 103 . The first metal layer is usually selected from a metal with low resistance, such as an alloy formed by one or more combinations of Cr, W, Ti, Ta, Mo, Al, and Cu.

As shown in FIG. 6 b , for ease of display, the top view in FIG. 6 b does not show the light shielding layer 106 , the buffer layer 107 , and the first insulating layer 109 . A buffer layer 107, a semiconductor layer 108, and a first insulating layer 109 are sequentially formed on the substrate 114 and the first metal layer, and the semiconductor layer 108 is subjected to photolithography, and the semiconductor layer 108 is patterned. After patterning The semiconductor layer 108 is located in the area corresponding to the light-shielding layer, which is shown in the A-A'301 area in FIG. 103, as shown in the area B-B' 302 in Fig. 6b. The first connection hole 201 is used to connect the gate line 102, and the gate line 102 communicates with the driving lead 103 through the first connection hole 201. The first insulating layer 109 is usually made of silicon nitride. Other insulating materials are possible. The semiconductor layer 108 is usually amorphous silicon or polycrystalline silicon.

As shown in FIG. 6 c , for ease of display, the top view in FIG. 6 c does not show the light shielding layer 106 , the buffer layer 107 , and the first insulating layer 109 . Form a second metal layer on the substrate 114, perform photolithography on the second metal layer, and pattern the second metal layer to form the gate line 102 and the gate 115, and the gate line 102 and the gate line 102 are The gate line 115 is connected, and the gate line 102 is connected to the driving lead line 103 through the first connection hole 201 . The second metal layer is usually selected from a metal with low resistance, such as an alloy formed by one or more combinations of Cr, W, Ti, Ta, Mo, Al, and Cu.

As shown in FIG. 6d , for ease of display, the top view in FIG. 6d does not show the light shielding layer 106 , the buffer layer 107 , the first insulating layer 109 , and the second insulating layer 110 . Form a second insulating layer 110 on the substrate 114, make a second connection hole 202 and a third connection hole 203 on the second insulation layer 110, the second connection hole 202 and the third connection hole 203 Part of the semiconductor layer 108 is exposed, as shown in the region A-A' 301 in FIG. The second insulating layer 110 is usually made of silicon nitride, and of course other insulating materials can also be used.

As shown in FIG. 6e , for ease of illustration, the top view in FIG. 6e does not show the light shielding layer 106 , the buffer layer 107 , the first insulating layer 109 , and the second insulating layer 110 . Form a third metal layer on the substrate 114, perform photolithography on the third metal layer, and pattern the third metal layer to form data lines 101, source electrodes 111, and drain electrodes 112. The source electrodes 111 Connected to the data line 101, the source electrode 111 communicates with the semiconductor layer 108 through the second connection hole 202, and the drain electrode 112 communicates with the semiconductor layer 108 through the third connection hole 203. connect. The projection of the data line 101 on the substrate 114 completely overlaps the projection of the driving lead 103 on the substrate 114 , which can increase the aperture ratio of the display. The third metal layer is usually selected from a metal with low resistance, such as an alloy formed by one or more combinations of Cr, W, Ti, Ta, Mo, Al, and Cu.

As shown in FIG. 6f , for ease of illustration, the top view in FIG. 6f does not show the light shielding layer 106 , the buffer layer 107 , the first insulating layer 109 , the second insulating layer 110 , and the passivation layer 113 . A passivation layer 113 is formed on the substrate 114 , and a fourth connection hole 204 is formed on the passivation layer 113 to expose part of the drain electrode 112 . The fourth connection hole 204 is used to connect the pixel electrode 105 . The passivation layer 113 can be a transparent insulating film, preferably silicon nitride or an organic film.

Form a fourth metal layer on the substrate 114, perform photolithography on the fourth metal layer, and pattern the fourth metal layer, and connect the fourth metal layer to the drain via the fourth connection hole 204. The poles 112 are connected. The specific structure can be seen in Fig. 2a to Fig. 2d, and the fourth metal layer is usually made of a transparent conductive material.

Through the above manufacturing process, the manufactured array substrate can increase the aperture ratio of the display, and the higher the pixel of the display, the more obvious the aperture ratio is improved.

Preferably, as shown in FIG. 7 , an embodiment of the present invention further provides a display panel, including the above-mentioned array substrate. The display panel may provide an aperture ratio of the display.

While preferred embodiments of the invention have been described, additional changes and modifications to these embodiments can be made by those skilled in the art once the basic inventive concept is appreciated. Therefore, it is intended that the appended claims be construed to cover the preferred embodiment as well as all changes and modifications which fall within the scope of the invention.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and equivalent technologies thereof, the present invention also intends to include these modifications and variations.

Claims (15)

1. An array substrate, characterized in that, comprising: A plurality of gate lines, a plurality of data lines and a plurality of drive leads, the gate lines correspond to the drive leads one by one; the data lines and the drive leads are arranged in separate layers; two adjacent data lines A pixel area is surrounded by two adjacent gate lines; The pixel area includes a thin film transistor and a pixel electrode; The pixel electrode is connected to one of the drain or the source of the thin film transistor; The gate line is connected to the gate of the thin film transistor; the gate line is connected to the driving lead, and the driving lead is used to transmit the driving signal generated by the gate driving circuit to the gate Wire; The data line communicates with the other of the source or the drain of the thin film transistor. 2 . The array substrate according to claim 1 , wherein the central line of the projection of the data lines on the array substrate completely overlaps the central line of the projection of the driving leads on the array substrate. 3. The array substrate according to claim 1, wherein the projection of the data lines on the array substrate partially overlaps the projection of the driving leads on the array substrate. 4. The array substrate according to claim 1, wherein the projections of the data lines on the array substrate and the projections of the driving leads on the array substrate do not overlap. 5 . The array substrate according to claim 1 , wherein the gate lines communicate with the driving leads through a first connection hole. 6. The array substrate according to claim 1, wherein the data line is in the same layer as the source and drain of the thin film transistor. 7. The array substrate according to claim 6, further comprising a light-shielding layer, the light-shielding layer being in the same layer as the driving leads. 8 . The array substrate according to claim 7 , wherein a buffer layer, a first insulating layer and a second insulating layer are sequentially disposed between the driving lead wire and the data line. 9. The array substrate according to claim 1, wherein the array substrate comprises: a light-shielding layer, a buffer layer, a semiconductor layer, a first insulating layer, a gate, a second insulating layer, And a source and a drain connected to the semiconductor layer through the second connection hole and the third connection hole. 10. A method for manufacturing an array substrate, characterized in that the method comprises: providing a substrate; disposing a first metal layer on the substrate and patterning a light-shielding layer and driving leads; a buffer layer, a semiconductor layer, and a first insulating layer are sequentially arranged on the substrate, and a first connection hole penetrating through the first insulating layer and the buffer layer is formed on the driving lead; disposing a second metal layer on the substrate and patterning a gate line, the gate line is connected to the driving lead through the first connection hole; A second insulating layer and a third metal layer are sequentially arranged on the substrate, and a source electrode, a drain electrode, and a data line are patterned, and the data line is connected to one of the source electrode or the drain electrode; A passivation layer and a transparent conductive layer are sequentially arranged on the substrate, and the transparent conductive layer is patterned to form a pixel electrode, and the pixel electrode communicates with the other of the drain electrode or the source electrode. 11. The method according to claim 10, further comprising, forming a second connection hole and a third connection hole on the first insulating layer and the second insulating layer, and the source and The drain is connected to the semiconductor layer through the second connection hole and the third connection hole respectively. 12. The method according to claim 10, wherein the centerline of the projection of the data line on the substrate completely overlaps the centerline of the projection of the driving lead line on the substrate. 13. The method according to claim 10, wherein the projection of the data line on the substrate partly overlaps the projection of the driving lead line on the substrate. 14. The method according to claim 10, wherein the projections of the data lines on the substrate do not overlap with the projections of the driving leads on the substrate. 15. A display panel, characterized by comprising the array substrate according to any one of claims 1-9.