CN107316873B - Array substrate and display device - Google Patents

Abstract

The invention discloses an array substrate and a display device. Through design, the orthographic projections of the semiconductor layer, the common electrode line, the source-drain metal layer, the common electrode layer and the pixel electrode layer on the base substrate have a common overlap in the non-opening area. area, so that the first capacitor is formed between the common electrode layer and the pixel electrode layer at the overlapping area, the second capacitor is formed between the common electrode layer and the source-drain metal layer at the overlapping area, and the semiconductor layer and the common electrode line are A third capacitor is formed at the overlapping area, so that the first capacitor, the second capacitor and the third capacitor are connected in parallel to form a part of the storage capacitor. On the basis of the existing storage capacitor formed by the common electrode layer and the pixel electrode layer in the existing open area, the array is enlarged by adding the first capacitor, the second capacitor and the third capacitor in parallel in the non-open area. The storage capacitor of the substrate can improve the pixel voltage retention rate of the array substrate and reduce the problem of poor flickering of the display device.

Description

Array substrate and display device

technical field

The present invention relates to the field of display technology, in particular to an array substrate and a display device.

Background technique

With the continuous development of thin film transistor (TFT, Thin Film Transistor) liquid crystal display technology, low temperature polysilicon (LTPS, Low Temperature Poly-silicon) TFT display devices with low power consumption, high resolution, fast response and high aperture ratio are gradually become mainstream and widely used.

In the LTPS-based TFT display device, the storage capacitor in the array substrate mainly exists in the area where the pixel electrode and the common electrode overlap in the open area, and there is no overlap between the pixel electrode and the common electrode in the non-open area, that is, the thin film transistor area. As the requirements for product resolution and aperture ratio increase, the pixel pitch (PixelPitch) in the array substrate will become smaller and smaller, and thus the storage capacitance of the array substrate will become smaller and smaller. After the scanning frequency is reduced, the retention time of one frame becomes longer, and the retention capacity of the panel is higher. Because under the condition of the same leakage current, the smaller the storage capacitor, the lower the retention rate of the pixel voltage, which will lead to lower pixel voltage retention rate. This leads to the occurrence of undesirable phenomena such as flicker, which greatly reduces the display quality of the array substrate.

Therefore, how to improve the storage capacitance of the array substrate without affecting the aperture ratio is a technical problem that needs to be solved urgently in the art.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide an array substrate and a display device to solve the problem of small storage capacitance in the prior art.

An array substrate provided by an embodiment of the present invention includes a base substrate, a semiconductor layer, a gate insulating layer, a gate metal layer, an interlayer dielectric layer, a source-drain metal layer, a semiconductor layer, a gate insulating layer, a gate metal layer, an interlayer dielectric layer, a source-drain metal layer, a flat layer, a common electrode layer, a passivation layer, a pixel electrode layer, and a common electrode line disposed on the base substrate; wherein,

Orthographic projections of the semiconductor layer, the common electrode line, the source-drain metal layer, the common electrode layer and the pixel electrode layer on the base substrate have a common overlapping area;

A first capacitor is formed between the common electrode layer and the pixel electrode layer at the overlapping area, and a second capacitor is formed between the common electrode layer and the source-drain metal layer at the overlapping area, so A third capacitor is formed at the overlapping region between the semiconductor layer and the common electrode line;

The first capacitor, the second capacitor and the third capacitor are connected in parallel to form a part of the storage capacitor.

On the other hand, an embodiment of the present invention further provides a display device, including: the above-mentioned array substrate provided by the embodiment of the present invention.

The beneficial effects of the present invention are as follows:

In an array substrate and a display device provided by an embodiment of the present invention, the pattern position of each film layer is changed by design, so that the semiconductor layer, the common electrode line, the source-drain metal layer, the common electrode layer and the element electrode layer are arranged on the base substrate. The orthographic projection above has a common overlapping area in the non-opening area, so that the first capacitor is formed between the common electrode layer and the pixel electrode layer at the overlapping area, and the first capacitance is formed between the common electrode layer and the source-drain metal layer at the overlapping area. Two capacitors, a third capacitor is formed at the overlapping area between the semiconductor layer and the common electrode line, so that the first capacitor, the second capacitor and the third capacitor are connected in parallel to form a part of the storage capacitor. On the basis of the existing storage capacitor formed by the common electrode layer and the pixel electrode layer in the existing opening area, by adding the first capacitor, the second capacitor and the third capacitor in parallel in the non-open area, the opening is not affected. In the case of high ratio, the storage capacitance of the array substrate is increased, the pixel voltage retention rate of the array substrate can be improved, and the problem of poor flickering of the display device can be reduced.

Description of drawings

FIG. 1a is a schematic diagram of a plane structure of an array substrate according to an embodiment of the present invention;

Figure 1b is a schematic cross-sectional view along AA in Figure 1a;

Fig. 1c is a schematic cross-sectional view along BB in Fig. 1a;

FIG. 2a is the second schematic diagram of the plane structure of the array substrate provided by the embodiment of the present invention;

Figure 2b is a schematic cross-sectional view along A'A' in Figure 2a;

Figure 2c is a schematic cross-sectional view along B'B' in Figure 2a;

FIG. 3 is a third schematic diagram of a plane structure of an array substrate provided by an embodiment of the present invention;

FIG. 4 is a fourth schematic diagram of a plane structure of an array substrate according to an embodiment of the present invention;

5a to 5h are schematic diagrams of the plane structure of each film layer in FIG. 1a, respectively;

6a to 6h are schematic diagrams of the plane structure of each film layer in FIG. 2a;

FIG. 7 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present invention clearer, the specific implementations of the array substrate and the display device provided by the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only used to illustrate and explain the present invention, but not to limit the present invention. And the embodiments in this application and the features in the embodiments may be combined with each other without conflict.

An embodiment of the present invention provides an array substrate, as shown in FIG. 1a to FIG. 1c, comprising: a base substrate 01, a semiconductor layer 02, a gate insulating layer 03, and a gate metal layer 04 that are sequentially stacked on the base substrate 01 , an interlayer dielectric layer 05, a source-drain metal layer 06, a flat layer 07, a common electrode layer 08, a passivation layer 09, a pixel electrode layer 10, and a common electrode line 20 disposed on the base substrate 01; wherein,

The orthographic projections of the semiconductor layer 02, the common electrode line 20, the source-drain metal layer 06, the common electrode layer 08 and the pixel electrode layer 10 on the base substrate 01 have a common overlapping area (shown by the dotted box in FIG. 1a);

The first capacitor C1 is formed between the common electrode layer 08 and the pixel electrode layer 10 at the overlapping area, the second capacitor C2 is formed between the common electrode layer 08 and the source-drain metal layer 06 at the overlapping area, and the semiconductor layer 02 and the common electrode line A third capacitor C3 is formed at the overlapping area between 20;

The first capacitor C1, the second capacitor C2 and the third capacitor C3 are connected in parallel to form a part of the storage capacitor.

Specifically, FIG. 1 a is a schematic plan view of an array substrate, FIG. 1 b is a cross-sectional view along AA in FIG. 1 a , and FIG. 1 c is a cross-sectional view along BB in FIG. 1 a .

Specifically, in the above-mentioned array substrate provided by the embodiment of the present invention, the pattern position of each film layer is changed by design, and the semiconductor layer 02 , the common electrode line 20 , the source-drain metal layer 06 , the common electrode layer 08 and the pixel electrode layer 10 are The orthographic projection on the base substrate 01 has a common overlapping area in the non-opening area (shown by the dotted box in FIG. 1a ), so that a first capacitor C1 is formed between the common electrode layer 08 and the pixel electrode layer 10 at the overlapping area, A second capacitor C2 is formed between the common electrode layer 08 and the source-drain metal layer 06 at the overlapping area, and a third capacitor C3 is formed between the semiconductor layer 02 and the common electrode line 20 at the overlapping area, so that the first capacitor C1, the third capacitor C3 are formed at the overlapping area. The second capacitor C2 and the third capacitor C3 are connected in parallel to form a part of the storage capacitor. On the basis of the existing storage capacitor formed by the common electrode layer and the pixel electrode layer in the existing open area, by adding the first capacitor C1, the second capacitor C2 and the third capacitor C3 in parallel in the non-open area, the Without affecting the aperture ratio, the storage capacitance of the array substrate is increased, the pixel voltage retention rate of the array substrate can be improved, and the problem of poor flickering of the display device can be reduced.

In the specific implementation, in the above-mentioned array substrate provided by the embodiment of the present invention, since the semiconductor layer 02 is disposed under the gate metal layer 04, that is, the thin film transistor formed on the base substrate 01 is a top-gate thin film transistor, which is In order to prevent the backlight source from irradiating the channel region 023 of the thin film transistor to generate photo-generated carriers, thereby affecting the normal on or off state of the thin film transistor, generally the channel region 023 needs to be shielded. Specifically, as shown in FIG. 1a, the array substrate generally needs to include: a metal shielding layer disposed between the base substrate 01 and the semiconductor layer 02; the metal shielding layer specifically includes: shielding electrodes 11, and the shielding electrodes 11 will be provided The channel region 023 in the shielding semiconductor layer 02 , that is, the orthographic projection of the shielding electrode 11 on the base substrate 01 will cover the orthographic projection of the channel region 023 on the base substrate 01 . Preferably, the area occupied by the shielding electrode 11 is generally larger than the area occupied by the channel region 023 to achieve better shielding effect. Specifically, the material of the metal shielding layer can be selected from metal materials such as aluminum, tungsten, and chromium, or metal compound materials, which are not limited herein.

In specific implementation, in the above-mentioned array substrate provided by the embodiment of the present invention, since the channel region 023 shielded by the shielding electrode 11 is the overlapping region of the semiconductor layer 02 and the gate 041 , and the common electrode line 20 is substantially parallel to the gate line 041 , therefore, the orthographic projection of the shielding electrode 11 on the base substrate 01 does not overlap with the common electrode line 20 . Based on this, in the above-mentioned array substrate provided by the embodiment of the present invention, the common electrode line 20 and the shielding electrode 11 may be arranged in the same layer, that is, the metal shielding layer specifically includes: the shielding electrode 11 and the common electrode line 20; at this time, the gate metal The layer 04 specifically includes: the gate 041 and the gate line 042; the common electrode line 20 can be roughly parallel to the gate line 042, and since the common electrode line 20 and the gate line 042 are not in the same film layer, they are not limited by the manufacturing process, The orthographic projections of the two on the base substrate 01 can be very close without short-circuit and signal interference problems. Based on this, when the common electrode line 20 and the shield electrode 11 are disposed on the metal shield layer in the same layer, the wiring of the non-open area can be designed to be more compact, which is more conducive to maintaining a large aperture ratio of the pixel.

In specific implementation, in the above-mentioned array substrate provided by the embodiment of the present invention, the film layer position of the common electrode line 20 may be disposed on the gate metal layer 04 in addition to the above-mentioned setting in the same layer as the shielding electrode 11 . At this time, as shown in FIGS. 2 a to 2 c , the gate metal layer 04 specifically includes: a gate electrode 041 , a gate line 042 and a common electrode line 20 ; the common electrode line 20 may be substantially parallel to the gate line 042 . At this time, since the gate metal layer 04 is located between the source-drain metal layer 06 and the semiconductor layer 02, the common electrode line 20 and the source-drain metal layer 06 may form a fourth capacitor C4 at the overlapping area; the first capacitor C1 , the second capacitor C2, the third capacitor C3 and the fourth capacitor C4 are connected in parallel to form a part of the storage capacitor. The added fourth capacitance C4 can further increase the storage capacitance of the array substrate relative to the structure shown in FIG. 1a.

Specifically, Fig. 2a is a schematic plan view of an array substrate, Fig. 2b is a cross-sectional view along A'A' in Fig. 2a, and Fig. 2c is a cross-sectional view along B'B' in Fig. 2a.

Specifically, by comparing the storage capacitors in the existing array substrates, the increase ratio of the storage capacitors in the array substrates provided by the embodiments of the present invention can be calculated. Specifically, when designing the common electrode line in the array substrate, there are only two parts of capacitance in the thin film transistor region: the capacitance between the semiconductor layer and the common electrode line (equivalent to the third capacitance C3) and the common electrode line and the source-drain metal capacitance between layers (equivalent to the fourth capacitance C4). However, in the above-mentioned array substrate provided by the embodiment of the present invention, by adjusting the pattern of each film layer, two parts of capacitance are newly added in the thin film transistor area, that is, the overlapping area between the common electrode layer 08 and the pixel electrode layer 10 forms the first part of the capacitance. A capacitor C1, and a second capacitor C2 is formed at the overlapping area between the common electrode layer 08 and the source-drain metal layer 06.

From the corresponding capacitance values in the thin film transistor area listed in Table 1 below, it can be known that, through theoretical calculation, the capacitances C1 and C2 added in the thin film transistor area are 2.29 times that of the existing capacitances C3 and C4.

capacitance Capacitance value per unit area (F/m²) The first capacitor C1 1.15E-05 The second capacitor C2 5.14E-04 The third capacitor C3 3.32E-04 Fourth capacitor C4 7.50E-05

Table 1

In addition, the increase of the first capacitor C1 and the second capacitor C2 in the above-mentioned array substrate provided by the embodiment of the present invention increases the percentage of the total storage capacitor relative to the size of the existing storage capacitor in the opening area. Taking 5.03HD and 5.46FHD products as examples, if the above-mentioned array substrate provided by the embodiment of the present invention is used, the percentage (Perc.) of the total storage capacitance increase is calculated:

5.03HD:Perc.=19.62*1.29/257.91=9.81%

5.46FHD:Pecc.=23.48*1.29/118.48=25.56%

The percentage of new capacitors is: applied to 5.03HD products, the storage capacitor will increase by 9.81%; applied to 5.46FHD products, the storage capacitor will increase by 25.56%.

In specific implementation, in the above-mentioned array substrate provided by the embodiment of the present invention, as shown in FIG. 1a and FIG. 2a, the source-drain metal layer 06 generally specifically includes: a source contact electrode 061 and a drain contact electrode 062; a source contact electrode The electrode 061 is used for conducting the source electrode 021 in the semiconductor layer 02 and the data signal line, and the drain contact electrode 062 is used for conducting the drain electrode 022 in the semiconductor layer 02 and the pixel electrode layer 10 . In the specific implementation, in order to ensure the stability of the added first capacitor C1, the second capacitor C2 and the third capacitor C3 in parallel, and not be disturbed by the signal of the data signal line, the overlapping area is generally located in the area where the drain contact electrode 062 is located, That is, in fact, the second capacitor C2 is formed at the overlapping area between the common electrode layer 08 and the drain contact electrode 062 in the source-drain metal layer 06 .

During specific implementation, in the above-mentioned array substrate provided by the embodiment of the present invention, as shown in FIG. 1a and FIG. 2a, the semiconductor layer 02 generally specifically includes: a source electrode 021, a drain electrode 022 and a channel region 023; As shown in FIG. 2c, the drain contact electrode 062 is specifically connected to the drain electrode 022 through the first contact hole a, and the first contact hole a penetrates the gate insulating layer 03 and the interlayer dielectric layer 05; as shown in FIG. 1c and FIG. 2c, The drain contact electrode 062 is connected to the pixel electrode layer 10 through the second contact hole b and the third contact hole c. The second contact hole b penetrates the flat layer 07, the third contact hole c penetrates the passivation layer 09, and the second contact hole The orthographic projection of b on the base substrate 01 covers the orthographic projection of the third contact hole c on the base substrate 01 .

Based on this, in the above-mentioned array substrate provided by the embodiment of the present invention, as shown in FIG. 1a and FIG. 2a, the drain contact electrode 062 can be divided into a punched area and an overlapping area (indicated by the dotted line box in the figure). The hole a, the second contact hole b, and the third contact hole c are located in the punched area.

Preferably, in the above-mentioned array substrate provided by the embodiment of the present invention, as shown in FIG. 1a and FIG. 1c , the first contact hole a and the third contact hole c may have overlapping areas in the punched area to reduce punching. The hole area occupies a proportion in the drain contact electrode 062, thereby increasing the proportion of the overlapping area to increase the capacitance values of the first capacitor C1, the second capacitor C2 and the third capacitor C3 formed at the overlapping area.

In specific implementation, in the above-mentioned array substrate provided by the embodiment of the present invention, in order to maximize the area of the first capacitor C1, the second capacitor C2 and the third capacitor C3 connected in parallel in the non-display area, as shown in Figure 1a, As shown in FIG. 2a, FIG. 3 and FIG. 4, the common electrode line 20 can be designed to have a portion protruding in the extension direction, and the area of the drain contact electrode 062 can be increased to completely cover the common electrode line protruding in the extension direction. After that, ensure that the semiconductor layer 02, the common electrode layer 08 and the pixel electrode layer 10 completely cover the area where the drain contact electrode 062 is located, that is, the common electrode layer 08 and the pixel electrode layer 10 are changed from the existing uncovered thin film transistor area to cover The thin film transistor area, so that the orthographic projections of the semiconductor layer 02, the common electrode line 20, the source-drain metal layer 06, the common electrode layer 08 and the pixel electrode layer 10 on the base substrate 01 have a common overlapping area of L-shape, which can maximize the Increase the storage capacitor value as much as possible.

In the specific implementation, in the above-mentioned array substrate provided by the embodiment of the present invention, the pattern of the semiconductor layer 02 can be specifically designed according to the required wiring. Specifically, the pattern of the semiconductor layer 02 can be L-shaped as shown in FIG. 2a, The pattern of the semiconductor layer 02 may also be U-shaped as shown in FIG. 1a and FIG. 4 , or the pattern of the semiconductor layer 02 may also be a zigzag shape as shown in FIG. 3 , which is not limited herein.

In specific implementation, in the above-mentioned array substrate provided by the embodiment of the present invention, the number of gates 041 formed in the gate metal layer 04 is not limited. As shown in FIG. 3 and FIG. 4 , there are two gates 041 , and when there are two gates 041 , the thin film transistor can be formed with a double-gate structure, which can reduce the leakage current when the thin film transistor is turned off.

The specific structure shown in FIG. 1a in the above-mentioned array substrate provided by the embodiment of the present invention is described in detail below with reference to the schematic plan structures of each film layer shown in FIG. 5a to FIG. 5h.

Specifically, as shown in FIG. 5a, it is a metal shielding layer in the above-mentioned array substrate provided by an embodiment of the present invention. The metal shielding layer specifically includes: shielding electrodes 11 and common electrode lines 20; , the area of the common electrode line 20 and the subsequently formed semiconductor layer 02, the drain contact electrode 062, the common electrode layer 08 and the pixel electrode layer 10 on the base substrate 01 has a common overlapping area, to maximize the storage capacitance. In the specific implementation, the pattern of the shielding electrode 11 and the common electrode line 20 in the metal shielding layer is generally formed simultaneously by a patterning process. The material of the metal shielding layer can be aluminum, tungsten, chromium or other metals and metal compounds, etc. Do limit.

Specifically, a buffer layer can be formed on the metal shielding layer to prevent substances in the base substrate 01 from diffusing into each film layer structure on the base substrate 01 in a subsequent process, for example, during the crystallization of the semiconductor layer 02, while the It affects the quality of the fabricated array substrate. The buffer layer usually covers the entire base substrate 01, and via holes are formed only in some areas. Since the buffer layer is similar to the prior art, in the above-mentioned array substrate provided by the embodiment of the present invention, the planar structure of the buffer layer is not performed. Specific instructions. The material of the buffer layer may be silicon nitride, silicon oxide, or a composite material of silicon nitride and silicon oxide, which is not limited herein.

Specifically, as shown in FIG. 5b , it is the semiconductor layer 02 provided on the buffer layer in the above-mentioned array substrate provided in the embodiment of the present invention. The semiconductor layer 02 specifically includes: a source electrode 021, a drain electrode 022 and a channel region 023; both the source electrode 021 and the drain electrode 022 have undergone a doping process to have conductivity, and the orthographic projection of the channel region 023 on the substrate 01 is Covered by the orthographic projection of the shielding electrode 11 on the base substrate 01 , the specific number of channel regions 023 is the same as the number of gates 041 formed subsequently and overlaps each other. Specifically, the third capacitor C3 is formed at the overlapping area between the common electrode line 20 and the semiconductor layer 02 .

Specifically, the gate insulating layer 03 formed on the semiconductor layer 02 usually covers the entire base substrate 01, and only via holes are formed in some regions. In the above-mentioned array substrate, the planar structure of the gate insulating layer 03 is not described in detail. The material of the gate insulating layer 03 may be silicon oxide, silicon nitride, or a composite insulating material composed of silicon oxide and silicon nitride, which is not limited herein.

Specifically, as shown in FIG. 5 c , it is the gate metal layer 04 provided on the gate insulating layer 03 in the above-mentioned array substrate provided by the embodiment of the present invention. The gate metal layer 04 specifically includes: a gate 041 and a gate line 042; the gate line 042 is substantially parallel to the common electrode line 20 and the orthographic projections on the base substrate 01 do not overlap each other; the gate 041 may be two, two gates The orthographic projection of the pole 041 on the base substrate 01 and the orthographic projection of the channel region 023 in the semiconductor layer 02 on the base substrate 01 respectively have overlapping regions. In specific implementation, the patterns of the gate 041 and the gate line 042 in the gate metal layer 04 are generally formed at the same time through a patterning process. The material of the gate metal layer 04 can be aluminum, tungsten, chromium or other metals and metal compounds, etc. Not limited.

Specifically, the interlayer dielectric layer 05 formed on the gate metal layer 04 plays the role of protecting the gate metal layer 04 and isolating the gate metal layer 04 and the source-drain metal layer 06 formed subsequently. The interlayer dielectric layer 05 is usually It can cover the entire base substrate 01, and via holes are only formed in some areas. Since the interlayer dielectric layer 05 is similar to the prior art, in the above-mentioned array substrate provided by the embodiment of the present invention, no interlayer dielectric layer is used. The plane structure of 05 is described in detail.

Specifically, as shown in FIG. 5d , a first contact for electrically connecting the drain electrode 022 in the semiconductor layer 02 and the drain contact electrode 062 formed subsequently is also formed in the interlayer dielectric layer 05 and the gate insulating layer 03 The hole a, and the fourth contact hole d for electrically connecting the source electrode 021 in the semiconductor layer with the source contact electrode 061 formed subsequently will not be repeated here. The shape of the first contact hole a and the fourth contact hole d may be a circle, a square, a triangle, a trapezoid or other polygons, which are not limited herein. In FIG. 5d , the first contact hole a and the fourth contact hole d are taken as an example in which the shapes are square.

Specifically, as shown in FIG. 5e , it is the source-drain metal layer 06 provided on the interlayer dielectric layer 05 in the above-mentioned array substrate provided by the embodiment of the present invention. The source-drain metal layer 06 specifically includes: a source contact electrode 061 and a drain contact electrode 062; the source contact electrode 061 and the source electrode 021 in the semiconductor layer 02 have an overlapping area, and pass through the fourth contact hole d in the overlapping area It is electrically connected to the source electrode 021; the drain contact electrode 062 has an overlapping area with the drain electrode 022 in the semiconductor layer 02, and is electrically connected to the drain electrode 022 through the first contact hole a in the overlapping area. In addition, the area occupied by the drain contact electrode 062 is relatively large. In addition to covering the overlapping area of the semiconductor layer 02 and the common electrode line 20 (shown by the dotted box in the figure), it also covers the area including the first contact hole a. The hole area is drilled to ensure that the drain contact electrode 062 can be electrically connected to the pixel electrode layer 10 formed subsequently through the second contact hole b and the third contact hole c formed subsequently.

Specifically, the flattening layer 07 formed on the source-drain metal layer 06 plays a role of protecting the source-draining metal layer 06 and flattening the surface of the array substrate. The flattening layer 07 can usually cover the entire base substrate 01, and only Parts of the region are formed with via holes. Since the flattening layer 07 is similar to the prior art, in the above-mentioned array substrate provided by the embodiment of the present invention, the plane structure of the flattening layer 07 is not described in detail. The material of the flattening layer 07 can be an inorganic insulating material or an organic insulating material. Preferably, the flattening layer 07 is an organic resin material, which is less rigid than an inorganic material and is beneficial to the flattening of the array substrate.

Specifically, as shown in FIG. 5f , a second contact hole b for electrically connecting the drain contact electrode 062 with the pixel electrode 10 formed subsequently is also formed in the flat layer 07 , which is not repeated here. The shape of the second contact hole b may be a circle, a square, a triangle, a trapezoid or other polygons, which are not limited herein. In FIG. 5f , the second contact hole b has a square shape as an example for illustration.

Specifically, as shown in FIG. 5g , it is the common electrode layer 08 provided on the flat layer 07 in the above-mentioned array substrate provided by the embodiment of the present invention. The orthographic projection of the common electrode layer 08 on the base substrate 01 will cover the orthographic projection of the drain contact electrode 062 on the base substrate 01, and the second contact hole b area will have an opening area e, that is, no pattern, so as to It is ensured that the pixel electrode layer 10 formed subsequently can be electrically connected to the drain contact electrode 062 through the second contact hole b. In addition, since the common electrode layer 08 covers the drain contact electrode 062, the common electrode layer 08 forms a capacitance with the drain contact electrode 062 in the non-open region e, and thus the common electrode layer 08 and the drain contact electrode 062 can overlap with the drain contact electrode 062 at the overlapping region. A second capacitor C2 connected in parallel with the third capacitor C3 is formed as a part of the storage capacitor.

Moreover, the material of the common electrode layer 08 is usually a transparent conductive material such as indium tin oxide (ITO). The shape of the opening area e in the common electrode layer 08 may be a circle, a square, a triangle, a trapezoid or other polygons, which is not limited herein. In FIG. 5g, the shape of the opening area e is taken as an example to be described as a square.

Specifically, the passivation layer 09 formed on the common electrode layer 08 plays the role of protecting the common electrode layer 08 and isolating the common electrode layer 08 and the pixel electrode layer 10 formed subsequently, and the passivation layer 09 can usually cover the entire substrate The substrate 01 only has vias formed in some regions. Since the passivation layer 09 is similar to the prior art, the planar structure of the passivation layer 09 is not specifically described in the above-mentioned array substrate provided by the embodiments of the present invention. The material of the passivation layer 09 may be an inorganic insulating material or an organic insulating material.

Specifically, a third contact hole c for electrically connecting the drain contact electrode 062 with the pixel electrode 10 formed subsequently is also formed in the passivation layer 09, and details are not repeated here. The shape of the third contact hole c may be a circle, a square, a triangle, a trapezoid or other polygons, which are not limited herein. Generally, the third contact hole c is located in the region where the second contact hole b is located, and FIG. 5h illustrates by taking an example that the shape and size of the third contact hole c is the same as that of the second contact hole b.

Specifically, as shown in FIG. 5h , it is the pixel electrode layer 10 provided on the passivation layer 09 in the above-mentioned array substrate provided by the embodiment of the present invention. Different from the prior art, the orthographic projection of the pixel electrode layer 10 on the base substrate 01 will cover the orthographic projection of the drain contact electrode 062 on the base substrate 01, so as to ensure that the pixel electrode layer 10 is at the area of the drain contact electrode 062 A capacitor is formed with the common electrode layer 08, and then the common electrode layer 08 and the pixel electrode layer 10 form a first capacitor C1 in parallel with the third capacitor C3 and the second capacitor C2 at the overlapping area, as part of the storage capacitor to increase Storage capacitors of the array substrate. In addition, the material of the pixel electrode layer 10 is usually a transparent conductive material such as indium tin oxide (ITO).

The following describes in detail the specific structure shown in FIG. 2a in the above-mentioned array substrate provided by the embodiment of the present invention with reference to the schematic plan structures of each film layer shown in FIG. 6a to FIG. 6h.

Specifically, as shown in FIG. 6 a , it is a metal shielding layer in the above-mentioned array substrate provided by an embodiment of the present invention, and the metal shielding layer specifically includes: a shielding electrode 11 . In specific implementation, the pattern of the shielding electrode 11 in the metal shielding layer is generally formed simultaneously by one patterning process. The material of the metal shielding layer may be aluminum, tungsten, chromium or other metals and metal compounds, which are not limited herein.

Specifically, a buffer layer can be formed on the metal shielding layer to prevent substances in the base substrate 01 from diffusing into each film layer structure on the base substrate 01 in a subsequent process, for example, during the crystallization of the semiconductor layer 02, while the It affects the quality of the fabricated array substrate. The buffer layer usually covers the entire base substrate 01, and via holes are formed only in some areas. Since the buffer layer is similar to the prior art, in the above-mentioned array substrate provided by the embodiment of the present invention, the planar structure of the buffer layer is not performed. Specific instructions. The material of the buffer layer may be silicon nitride, silicon oxide, or a composite material of silicon nitride and silicon oxide, which is not limited herein.

Specifically, as shown in FIG. 6b , it is the semiconductor layer 02 provided on the buffer layer in the above-mentioned array substrate provided in the embodiment of the present invention. The semiconductor layer 02 specifically includes: a source electrode 021, a drain electrode 022 and a channel region 023; both the source electrode 021 and the drain electrode 022 have undergone a doping process to have conductivity, and the orthographic projection of the channel region 023 on the substrate 01 is Covered by the orthographic projection of the shielding electrode 11 on the base substrate 01 , the specific number of channel regions 023 is the same as the number of gates 041 formed subsequently and overlaps each other.

Specifically, the gate insulating layer 03 formed on the semiconductor layer 02 usually covers the entire base substrate 01, and only via holes are formed in some regions. In the above-mentioned array substrate, the planar structure of the gate insulating layer 03 is not described in detail. The material of the gate insulating layer 03 may be silicon oxide, silicon nitride, or a composite insulating material composed of silicon oxide and silicon nitride, which is not limited herein.

Specifically, as shown in FIG. 6c , it is the gate metal layer 04 provided on the gate insulating layer 03 in the above-mentioned array substrate provided by the embodiment of the present invention. The gate metal layer 04 specifically includes: a gate 041, a gate line 042 and a common electrode line 20; the common electrode line 20 has a portion protruding in the extension direction, which can increase the common electrode line 20, the semiconductor layer 02, and the drain contact electrode 062 The orthographic projections of the common electrode layer 08 and the pixel electrode layer 10 on the base substrate 01 have a common overlapping area to maximize the storage capacitance. Specifically, the common electrode line 20 and the semiconductor layer 02 overlap each other. The third capacitor C3 is formed at the area; the gate line 042 is approximately parallel to the common electrode line 20 and the orthographic projections on the base substrate 01 do not overlap each other; The orthographic projections on the semiconductor layer 02 respectively have overlapping regions with the orthographic projections of the channel regions 023 in the semiconductor layer 02 on the base substrate 01 . In the specific implementation, the patterns of the gate 041, the gate line 042 and the common electrode line 20 in the gate metal layer 04 are generally formed simultaneously by one patterning process. The material of the gate metal layer 04 can be aluminum, tungsten, chromium or other metals and metals Compounds and the like are not limited here.

Specifically, the interlayer dielectric layer 06 formed on the gate metal layer 04 plays the role of protecting the gate metal layer 04 and isolating the gate metal layer 04 and the source-drain metal layer 06 formed subsequently. The interlayer dielectric layer 06 is usually It can cover the entire base substrate 01, and via holes are only formed in some areas. Since the interlayer dielectric layer 06 is similar to the prior art, in the above-mentioned array substrate provided by the embodiment of the present invention, no interlayer dielectric layer is used. The plane structure of 06 is explained in detail.

Specifically, as shown in FIG. 6d , a first contact for electrically connecting the drain electrode 022 in the semiconductor layer 02 and the drain contact electrode 062 formed subsequently is also formed in the interlayer dielectric layer 06 and the gate insulating layer 03 The hole a, and the fourth contact hole d for electrically connecting the source electrode 021 in the semiconductor layer with the source contact electrode 061 formed subsequently will not be repeated here. The shape of the first contact hole a and the fourth contact hole d may be a circle, a square, a triangle, a trapezoid or other polygons, which are not limited herein. In FIG. 6d , the first contact hole a and the fourth contact hole d are taken as an example in which the shapes are square.

Specifically, as shown in FIG. 6e , it is the source-drain metal layer 06 provided on the interlayer dielectric layer 06 in the above-mentioned array substrate provided by the embodiment of the present invention. The source-drain metal layer 06 specifically includes: a source contact electrode 061 and a drain contact electrode 062; the source contact electrode 061 and the source electrode 021 in the semiconductor layer 02 have an overlapping area, and pass through the fourth contact hole d in the overlapping area It is electrically connected to the source electrode 021; the drain contact electrode 062 has an overlapping area with the drain electrode 022 in the semiconductor layer 02, and is electrically connected to the drain electrode 022 through the first contact hole a in the overlapping area, and the first contact hole a is located at The punched area does not overlap with the overlapping area, therefore, a fourth capacitor C4 is formed at the overlapping area between the drain contact electrode and the common electrode line 20 . In addition, the area occupied by the drain contact electrode 062 is relatively large. In addition to covering the overlapping area of the semiconductor layer 02 and the common electrode line 20 (shown by the dotted box in the figure), it also covers the area including the first contact hole a. The hole area is drilled to ensure that the drain contact electrode 062 can be electrically connected to the pixel electrode layer 10 formed subsequently through the second contact hole b and the third contact hole c formed subsequently.

Specifically, the flattening layer 07 formed on the source-drain metal layer 06 plays a role of protecting the source-draining metal layer 06 and flattening the surface of the array substrate. The flattening layer 07 can usually cover the entire base substrate 01, and only Parts of the region are formed with via holes. Since the flattening layer 07 is similar to the prior art, in the above-mentioned array substrate provided by the embodiment of the present invention, the plane structure of the flattening layer 07 is not described in detail. The material of the flattening layer 07 can be an inorganic insulating material or an organic insulating material. Preferably, the flattening layer 07 is an organic resin material, which is less rigid than an inorganic material and is beneficial to the flattening of the array substrate.

Specifically, as shown in FIG. 6f , a second contact hole b for electrically connecting the drain contact electrode 062 to the pixel electrode 10 formed subsequently is also formed in the flat layer 07 , which is not repeated here. The shape of the second contact hole b may be a circle, a square, a triangle, a trapezoid or other polygons, which are not limited herein. In FIG. 6f , the second contact hole b has a square shape as an example for illustration.

Specifically, as shown in FIG. 6g , it is the common electrode layer 08 provided on the flat layer 07 in the above-mentioned array substrate provided by the embodiment of the present invention. The orthographic projection of the common electrode layer 08 on the base substrate 01 will cover the orthographic projection of the drain contact electrode 062 on the base substrate 01, and the second contact hole b area will have an opening area e, that is, no pattern, so as to It is ensured that the pixel electrode layer 10 formed subsequently can be electrically connected to the drain contact electrode 062 through the second contact hole b. Moreover, since the common electrode layer 08 covers the drain contact electrode 062, the common electrode layer 08 will form a capacitance with the drain contact electrode 062 in the non-open area e, and then the common electrode layer 08 and the drain contact electrode 062 may overlap with the drain contact electrode 062. A second capacitor C2 connected in parallel with the third capacitor C3 is formed as a part of the storage capacitor.

Moreover, the material of the common electrode layer 08 is usually a transparent conductive material such as indium tin oxide (ITO). The shape of the opening area e in the common electrode layer 08 may be a circle, a square, a triangle, a trapezoid or other polygons, which is not limited herein. In FIG. 6g, the shape of the opening area e is taken as an example for illustration.

Specifically, the passivation layer 09 formed on the common electrode layer 08 plays the role of protecting the common electrode layer 08 and isolating the common electrode layer 08 and the pixel electrode layer 10 formed subsequently, and the passivation layer 09 can usually cover the entire substrate The substrate 01 only has vias formed in some regions. Since the passivation layer 09 is similar to the prior art, the planar structure of the passivation layer 09 is not specifically described in the above-mentioned array substrate provided by the embodiments of the present invention. The material of the passivation layer 09 may be an inorganic insulating material or an organic insulating material.

Specifically, a third contact hole c for electrically connecting the drain contact electrode 062 with the pixel electrode 10 formed subsequently is also formed in the passivation layer 09, and details are not repeated here. The shape of the third contact hole c may be a circle, a square, a triangle, a trapezoid or other polygons, which are not limited herein. Generally, the third contact hole c is located in the region where the second contact hole b is located, and FIG. 6h illustrates by taking an example that the shape and size of the third contact hole c is the same as that of the second contact hole b.

Specifically, as shown in FIG. 6h , it is the pixel electrode layer 10 provided on the passivation layer 09 in the above-mentioned array substrate provided by the embodiment of the present invention. Different from the prior art, the orthographic projection of the pixel electrode layer 10 on the base substrate 01 will cover the orthographic projection of the drain contact electrode 062 on the base substrate 01, so as to ensure that the pixel electrode layer 10 is at the area of the drain contact electrode 062 A capacitor is formed with the common electrode layer 08, and then the common electrode layer 08 and the pixel electrode layer 10 form a first capacitor C1 in parallel with the third capacitor C3 and the second capacitor C2 at the overlapping area, as part of the storage capacitor to increase Storage capacitors of the array substrate. In addition, the material of the pixel electrode layer 10 is usually a transparent conductive material such as indium tin oxide (ITO).

Based on the same inventive concept, an embodiment of the present invention further provides a display device, as shown in FIG. 7 , including the above-mentioned array substrate provided by the embodiment of the present invention. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, and the like. Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be repeated here, nor should it be regarded as a limitation of the present invention. For the implementation of the display device, reference may be made to the above-mentioned embodiments of the array substrate, and repeated descriptions will not be repeated.

The above-mentioned array substrate and display device provided by the embodiments of the present invention change the pattern position of each film layer by design, so that the semiconductor layer, the common electrode line, the source-drain metal layer, the common electrode layer and the pixel electrode layer are on the base substrate. The orthographic projection has a common overlapping area in the non-open area, so that a first capacitor is formed between the common electrode layer and the pixel electrode layer at the overlapping area, and a second capacitor is formed between the common electrode layer and the source-drain metal layer at the overlapping area. A third capacitor is formed at the overlapping area between the semiconductor layer and the common electrode line, so that the first capacitor, the second capacitor and the third capacitor are connected in parallel to form a part of the storage capacitor. On the basis of the existing storage capacitor formed by the common electrode layer and the pixel electrode layer in the existing opening area, by adding the first capacitor, the second capacitor and the third capacitor in parallel in the non-open area, the opening is not affected. In the case of high rate, the storage capacitance of the array substrate is increased, the pixel voltage retention rate of the array substrate can be improved, and the problem of poor flicker of the display device can be reduced.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention. Thus, provided that these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims (10)

1. An array substrate, comprising: the device comprises a substrate base plate, a semiconductor layer, a gate insulating layer, a gate metal layer, an interlayer dielectric layer, a source drain metal layer, a flat layer, a common electrode layer, a passivation layer, a pixel electrode layer and a common electrode wire, wherein the semiconductor layer, the gate insulating layer, the gate metal layer, the interlayer dielectric layer, the source drain metal layer, the flat layer, the common electrode layer, the passivation layer and the pixel electrode layer; wherein,

the orthographic projections of the semiconductor layer, the common electrode wire, the source drain metal layer, the common electrode layer and the pixel electrode layer on the substrate have a common overlapping area;

a first capacitor is formed between the common electrode layer and the pixel electrode layer at the overlapping area, a second capacitor is formed between the common electrode layer and the source drain metal layer at the overlapping area, and a third capacitor is formed between the semiconductor layer and the common electrode line at the overlapping area;

the first capacitor, the second capacitor and the third capacitor are connected in parallel to form a part of the storage capacitor.

2. The array substrate of claim 1, wherein the gate metal layer specifically comprises: a gate electrode, a gate line and the common electrode line; the common electrode line is parallel to the grid line;

a fourth capacitor is formed between the common electrode line and the source drain metal layer in the overlapping area; the first capacitor, the second capacitor, the third capacitor and the fourth capacitor are connected in parallel to form a part of the storage capacitor.

3. The array substrate of claim 1, further comprising: the metal shielding layer is arranged between the substrate base plate and the semiconductor layer;

the metal shielding layer specifically includes: a shield electrode and the common electrode line;

the gate metal layer specifically includes: a gate electrode and a gate line; the common electrode line is parallel to the gate line.

4. The array substrate according to any one of claims 1 to 3, wherein the source drain metal layer specifically comprises: a source contact electrode and a drain contact electrode;

the overlapping region is located in a region where the drain contact electrode is located.

5. The array substrate of claim 4, wherein the semiconductor layer comprises: a source, a drain and a channel region;

the drain contact electrode is connected with the drain through a first contact hole, and the first contact hole penetrates through the gate insulating layer and the interlayer dielectric layer;

the drain contact electrode is connected with the pixel electrode layer through a second contact hole and a third contact hole, the second contact hole penetrates through the flat layer, the third contact hole penetrates through the passivation layer, and the orthographic projection of the second contact hole on the substrate base plate covers the orthographic projection of the third contact hole on the substrate base plate;

the drain contact electrode is divided into a punching region and the overlapping region, and the first contact hole, the second contact hole, and the third contact hole are located in the punching region.

6. The array substrate of claim 5, wherein the first contact hole and the third contact hole have an overlapping area in the via region.

7. The array substrate of claim 6, wherein the overlap region is L-shaped.

8. The array substrate of claim 5, wherein the pattern of the semiconductor layer is L-shaped, U-shaped or zigzag.

9. The array substrate of claim 2 or 3, wherein the number of the gates is two.

10. A display device, comprising: an array substrate as claimed in any one of claims 1 to 9.

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