CN116632001B - Semiconductor device and design assisting device for semiconductor device - Google Patents

Abstract

The invention discloses a semiconductor device and a design auxiliary device for the semiconductor device, which belong to the field of semiconductor technology. The semiconductor device includes: a MOM capacitor, the MOM capacitor includes a plurality of first electrodes and a plurality of second electrodes, and the The first electrodes and the second electrodes are arranged alternately in the first direction, and the first electrodes or the second electrodes are stacked in the second direction; the first shielding part is located on the second electrode in the second direction. One side of the MOM capacitor, and the area between the first shielding part and the MOM capacitor is electrically insulated; and a second shielding part is located on the other side of the MOM capacitor in the second direction, and the The area between the second shielding part and the MOM capacitor is electrically insulated. Through the semiconductor device and the design auxiliary device for the semiconductor device provided by the present invention, the degree of freedom of circuit design can be improved and the volume of the semiconductor device can be reduced.

Description

Semiconductor device and design auxiliary device for semiconductor device

Technical field

The invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a semiconductor device and a design assistance device for the semiconductor device.

Background technique

Capacitors are important components in integrated circuits and are widely used in memory, microwave, radio frequency or smart cards and other chips. In a semiconductor device, a metal-oxide-metal (MOM) capacitor has an electrode group in which a plurality of electrodes face each other, and a pair of shield parts facing each other across the MOM capacitor. set up. In the semiconductor device, each shield portion is connected to the ground potential, and the MOM capacitor is surrounded by the shield portion, thereby suppressing noise received by the MOM capacitor from surrounding signal lines. However, the shielding parts need to be connected to each other, which increases the layout area.

Contents of the invention

An object of the present invention is to provide a semiconductor device and a design assisting device for a semiconductor device. The semiconductor device and a design assisting device for a semiconductor device provided by the present invention can improve the degree of freedom of circuit design and achieve miniaturization of the semiconductor device. At the same time, Improve the efficiency of design operations.

In order to solve the above technical problems, the present invention is implemented through the following technical solutions:

The invention provides a semiconductor device, including:

MOM capacitor, the MOM capacitor includes a plurality of first electrodes and a plurality of second electrodes, and the first electrodes and the second electrodes are alternately arranged in a first direction, the first electrodes or the second electrodes The electrodes are stacked in a second direction, wherein the first direction and the second direction are perpendicular;

The first shielding part is located on one side of the MOM capacitor in the second direction, and the area between the first shielding part and the MOM capacitor is electrically insulated; and

The second shielding part is located on the other side of the MOM capacitor in the second direction, and the area between the second shielding part and the MOM capacitor is electrically insulated.

In an embodiment of the present invention, the first shielding part and the second shielding part are connected to ground terminals with different potentials.

In an embodiment of the present invention, the ground terminal includes a first ground terminal and a second ground terminal, and the first ground terminal and the second ground terminal have different potentials.

In an embodiment of the present invention, the first shielding part is connected to the first ground terminal or the second ground terminal, and the second shielding part is connected to the second ground terminal or the first ground terminal. connect.

In an embodiment of the present invention, the first electrode has at least one first main line.

In an embodiment of the present invention, the second electrode has at least one second main line, and the second main line and the first main line are alternately arranged in the first direction.

In an embodiment of the present invention, in the first direction, a wiring space is provided on both sides of the MOM capacitor, and in the wiring space, the first shielding part and the second shielding part are electrically insulation.

The present invention also provides a design assistance device for a semiconductor device, which is used for the above-mentioned semiconductor device, including:

A storage unit to store a plurality of symbols constituting the connection status of a plurality of elements in the semiconductor device, the symbols including representing the first electrode, the second electrode, the first shielding portion and the second The four-terminal connection symbol for the connection status of the shield; and

A circuit diagram design assisting unit is configured to call the symbols stored in the storage unit to design the circuit diagram of the semiconductor device.

In an embodiment of the present invention, the design assistance device further includes:

a layout design assisting unit to assist in the design of the layout of the semiconductor device; and

The verification unit compares the connection information between each component in the circuit diagram data with the connection information between each component in the layout data to verify whether the connection information matches.

In an embodiment of the present invention, the connection information between each component in the circuit diagram data and the connection information between each component in the layout data are stored in the storage unit.

As described above, the present invention provides a semiconductor device and a design assisting device for a semiconductor device, which can reduce the number of wire connections and the area of the wiring space in the semiconductor device, thereby miniaturizing the semiconductor device. The degree of freedom of wiring of each terminal of the semiconductor device can be improved, the wiring requirements of different circuits can be met, and the degree of freedom of the design of the semiconductor device and wiring can be improved. It can reduce the error output related to connection information in LVS verification and improve the efficiency of design work.

Of course, any product implementing the present invention does not necessarily need to achieve all the above-mentioned advantages at the same time.

Description of the drawings

In order to explain the technical solutions of the embodiments of the present invention more clearly, the drawings needed to describe the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without exerting creative efforts.

FIG. 1 is a schematic diagram of an electronic device circuit of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a four-terminal semiconductor device with a MOM capacitor according to an embodiment of the present invention.

FIG. 3 is a top view of the semiconductor device shown in FIG. 2 .

Part (a) in Figure 4 is a schematic diagram of the connection relationship between the first shielding part and the second shielding part and the ground terminal. Part (b) in Figure 4 is another diagram of the connection relationship between the first shielding part and the second shielding part and the ground terminal. A schematic diagram of a connection relationship.

FIG. 5 is a schematic structural diagram of the hardware structure of the design assistance device in an embodiment of the present invention.

FIG. 6 is a functional block diagram of a functional example of the design assisting device in an embodiment of the present invention.

7 is a schematic diagram of the parasitic capacitance when the first shielding part and the second shielding part of the MOM capacitor are metal-joined and connected to the ground terminal in an embodiment of the present invention.

8 is a schematic diagram of the connection symbols when the first shielding part and the second shielding part of the MOM capacitor are metal-joined and then connected to the ground terminal in an embodiment of the present invention.

FIG. 9 is a schematic diagram of the parasitic capacitance when the first shielding part and the second shielding part of the MOM capacitor are connected to different ground terminals in an embodiment of the present invention.

10 is a schematic diagram of the connection symbols when the first shielding part and the second shielding part of the MOM capacitor are connected to different ground terminals in an embodiment of the present invention.

FIG. 11 is a flow chart of the layout ratio schematic diagram verification process in an embodiment of the present invention.

FIG. 12 is a cross-sectional view of a three-terminal semiconductor device in the prior art.

Explanation of reference numbers:

1. Semiconductor device; 2. MOM capacitor; 3. First electrode; 4. Second electrode; 5. First shielding part; 6. Second shielding part; 8. Electronic device circuit; 10. Design auxiliary device; 11. CPU; 12. Auxiliary storage device; 13. Main storage device; 14. Communication interface; 15. Input section; 16. Display section; 18. Bus; 31. First main line; 41. Second main line; 101. Storage unit; 102a, circuit diagram design auxiliary unit; 102b, layout diagram design auxiliary unit; 103, verification unit; 103a, netlist extraction unit; 103b, comparison unit; GND1, first ground terminal; GND2, second ground terminal; LD, layout data ;S, wiring space; SD, circuit diagram data; Sym, symbol data; V1, first supply voltage terminal; V2, second supply voltage terminal; 1', three-terminal semiconductor device; 2', first MOM capacitor; 3 ', A electrode; 4', B electrode; 5', three-terminal first shielding part; 6', three-terminal second shielding part; S', first wiring space.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present invention.

Referring to FIG. 1 , in one embodiment of the present invention, a schematic diagram of an electronic device circuit having a semiconductor device provided by the present invention is provided. The electronic device circuit 8 includes a first supply voltage terminal V1 , a second supply voltage terminal V2 , a first ground terminal GND1 , a second ground terminal GND2 , and a semiconductor device 1 , wherein the first supply voltage terminal V1 and the second supply voltage terminal V2 The first ground terminal GND1 and the second ground terminal GND2 are connected to different ground potentials. The electronic device circuit 8 is, for example, a device in which single-function semiconductor devices such as diodes, transistors, resistors, and capacitors are integrated into one chip. In this embodiment, the semiconductor device 1 in the electronic device circuit 8 includes, for example, a MOM capacitor.

Please refer to FIG. 2 . In one embodiment of the present invention, FIG. 2 is a cross-sectional view of the semiconductor device 1 , for example, a four-terminal semiconductor device having a MOM capacitor. The direction in which the first electrodes 3 and the second electrodes 4 are alternately arranged is called a first direction X, and the direction perpendicular to the first direction X is called a second direction Y. In addition, in the depth direction perpendicular to the first direction X and the second direction Y, the cross section shown in FIG. 2 is formed continuously within a prescribed range, which will not be elaborated in the present invention.

Please refer to FIGS. 2 to 3 . In one embodiment of the present invention, FIG. 3 is a top view of the semiconductor device shown in FIG. 2 . The semiconductor device 1 includes a MOM capacitor 2 , a first shield portion 5 and a second shield portion 6 . The MOM capacitor 2 is a capacitive element utilizing coupling capacitance between wirings. The MOM capacitor 2 includes a first electrode 3 and a second shield portion 6 . There are two electrodes 4, and the first electrode 3 and the second electrode 4 are arranged alternately. The first shielding part 5 is disposed in the stacking direction of the semiconductor device 1, that is, in the second direction Y. The first shielding part 5 is disposed on one side of the first electrode 3 and the second electrode 4, and the second shielding part 6 is disposed on one side of the first electrode 3 and the second electrode 4. In the direction Y, it is located on the other side of the first electrode 3 and the second electrode 4 . That is, in the second direction Y, the first shielding part 5 and the second shielding part 6 are disposed on both sides of the MOM capacitor 2 , and the first shielding part 5 and the second shielding part 6 are in the area between both sides of the MOM capacitor 2 Internal electrical insulation set.

Please refer to Figures 2 to 3. In an embodiment of the present invention, in the MOM capacitor 2, the first electrode 3 has more than one first main line 31, and the second electrode 4 also has more than one second main line 41. . Among them, one or more first main lines 31 or second main lines 41 are alternately arranged in the predetermined first direction X. More than one first main line 31 and second main line 41 are provided adjacent to each other along the direction of the line segment 1-l' connecting the first electrode 3 and the second electrode 4. Through the structure provided by the present invention, a coupling capacitance (parasitic capacitance) is generated between the first main line 31 and the second main line 41 .

Please refer to FIGS. 2 to 3 . In one embodiment of the present invention, in the second direction Y perpendicular to the first direction The two shielding parts 6 function to arrange the MOM capacitor 2 between the first shielding part 5 and the second shielding part 6 . The first shielding part 5 covers the MOM capacitor 2 and can suppress the coupling capacitance generated between the signal line (not shown in the figure) arranged near the MOM capacitor 2 and the MOM capacitor 2 to prevent the MOM capacitor 2 from receiving the signal from the signal line. noise. Moreover, the first shielding part 5 can suppress the coupling capacitance generated between the signal line of the layer wiring provided above the first shielding part 5 and the MOM capacitor 2, thereby suppressing the noise received by the MOM capacitor 2 from the signal line.

Referring to FIGS. 2 to 3 , in one embodiment of the present invention, the second shielding part 6 is disposed on the side of the MOM capacitor 2 away from the first shielding part 5 in the second direction Y. And the second shielding part 6 is provided to cover the MOM capacitor 2, which can suppress the coupling capacitance generated between the signal line (not shown in the figure) arranged near the MOM capacitor 2 and the MOM capacitor 2, so as to suppress the MOM capacitor 2 from being blocked. Noise received on the signal line. In addition, the second shielding portion 6 can suppress the coupling electricity generated between the signal line of the layer wiring provided below the first shielding portion 5 and the MOM capacitor 2, thereby suppressing the noise received by the MOM capacitor 2 from the signal line. At the same time, in the vertical direction where the first electrodes 3 and the second electrodes 4 are alternately arranged, the space for the metal connection of the first shield part 5 and the second shield part 6 can be reduced, thereby achieving the effect of miniaturization.

Please refer to FIG. 12 . In another embodiment of the present invention, FIG. 12 is a cross-sectional view of a three-terminal semiconductor device including a three-terminal connection symbol with a MOM capacitor. Among them, in the second direction Y, the three-terminal semiconductor device 1' has a three-terminal first shielding part 5' and a three-terminal second shielding part 6' in the first wiring space S' around the first MOM capacitor 2'. Metal bonding is performed with the three-terminal semiconductor device 1'. That is, the three-terminal first shielding part 5' and the three-terminal second shielding part 6' have the same potential and can be regarded as one structure electrically. Therefore, the three-terminal semiconductor device 1' is a semiconductor device including three terminals: the A electrode 3', the B electrode 4', the three-terminal first shield portion 5', and the three-terminal second shield portion 6'.

Please refer to FIG. 2 . In another embodiment of the present invention, in the wiring space S around the MOM capacitor 2 , the first shielding part 5 and the second shielding part 6 are not metal-jointed in the second direction Y. , therefore the number of wiring connections and the area of the wiring space S in the semiconductor device 1 can be reduced, and the semiconductor device 1 can be miniaturized.

Referring to FIGS. 2 to 4 , in an embodiment of the present invention, in the four-terminal semiconductor device 1 , the first shielding part 5 and the second shielding part 6 may have different terminals. FIG. 4 is a schematic diagram showing the connection relationship between the first shield part 5 and the second shield part 6 and different ground terminals of the semiconductor device according to the present invention. In the examples of parts (a) and (b) in Figure 4 , the first shielding part 5 and the second shielding part 6 are respectively connected to different ground terminals, that is, the first shielding part 5 and the second shielding part 6 are Two terminals.

Please refer to Figure 4. In one embodiment of the present invention, in part (a) of Figure 4, the first shielding part 5 is connected to the first ground terminal GND1 with a prescribed potential, and the second shielding part 6 is connected to the second ground terminal GND1. The ground terminal GND2 is connected, and the second ground terminal GND2 and the first ground terminal GND1 have different potentials. In another embodiment of the present invention, as shown in part (b) of FIG. 4 , the first shielding part 5 is connected to the second ground terminal GND2 with a prescribed potential, and the second shielding part 6 is connected to the first grounding terminal GND1. The first ground terminal GND1 and the second ground terminal GND2 have different potentials. In addition, in the four-terminal semiconductor device 1 provided by the present invention, in the second direction Y, the first shielding portion 5 and the second shielding portion 6 are not metal-joined to each other, that is, the first shielding portion 5 and the second shielding portion 6 are insulated. . Therefore, the first shielding part 5 and the second shielding part 6 have independent terminals and are respectively connected to ground terminals with different potentials, which can increase the freedom of wiring of each terminal of the semiconductor device and meet the wiring requirements of different circuits. The degree of freedom in designing the semiconductor device 1 and wiring can be improved.

The present invention also provides a design auxiliary device for a semiconductor device. As shown in FIG. 5 , in one embodiment of the present invention, a schematic diagram of the hardware structure of the design auxiliary device is provided, and the design auxiliary device 10 for a semiconductor device includes a computer system. , for example, includes a CPU 11, an auxiliary storage device 12, a main storage device 13, a communication interface 14, an input unit 15, a display unit 16, a bus 18, and the like. Among them, the auxiliary storage device 12 is used to store the program executed by the CPU 11 and data referenced by the program, and the auxiliary storage device 12 is, for example, a magnetic disk, a magneto-optical disk, a semiconductor memory, or the like. The main storage device 13 is used to store a work area when executing each program, and the main storage device 13 is, for example, a magnetic disk, a magneto-optical disk, a semiconductor memory, or the like. The communication interface 14 is used to connect to a network. The input unit 15 includes, for example, an input device such as a keyboard or a mouse. The display unit 16 is, for example, a liquid crystal display device for displaying data. Each component is connected via a bus 18 , for example.

Please refer to FIG. 5 . In one embodiment of the present invention, the auxiliary storage device 12 stores a series of programs for realizing various functions described below, such as design assistance programs, etc., and the programs are transferred to the auxiliary storage device 12 through the CPU 11 . The information is read into the main storage device 13 and the information is processed and calculated to realize various functions. In other embodiments, the program may also choose other suitable forms, such as choosing a form that is pre-installed in the auxiliary storage device 12 , a form that is provided in a state stored in other computer-readable storage media, or via wired or wireless The form of communication unit transmission, etc. Among them, the computer-readable storage medium is a magnetic disk, a magneto-optical disk, a CD-ROM, a DVD-ROM or a semiconductor memory, etc.

Please refer to FIG. 6 . In one embodiment of the present invention, a functional block diagram of a functional example of the design assisting device 10 is used as an example for elaboration. The design assisting device 10 includes a storage unit 101 and a circuit diagram design assisting unit 102a. , layout design assisting unit 102b and verification unit 103.

Please refer to FIG. 2 and FIG. 6 . In one embodiment of the present invention, in the design assisting device 10 , the storage unit 101 stores the design drawing of the semiconductor device 1 , such as the symbol data and components of the components used in making the circuit diagram. The physical characteristic value, and the symbol type is, for example, in sym format. The symbols of the elements stored in the storage unit 101 are, for example, symbols of semiconductor elements such as resistive elements, capacitive elements, and transistors. In other embodiments, the components stored in the storage unit 101 may also include symbols of various components not disclosed in this embodiment, such as power supply components or control ICs. In addition, a plurality of symbols are also stored in the storage unit 101, and the plurality of symbols include, for example, the first electrode 3, the second electrode 4, the first shielding portion 5 and the second shielding portion 6 corresponding to the semiconductor device 1 in this embodiment. The four-terminal connection symbols of the connection status also include multiple symbols of the connection status of multiple components required for designing electronic device circuits.

Please refer to Figures 2, 7 and 8. In one embodiment of the present invention, Figure 7 shows the parasitic capacitance when the first shielding part and the second shielding part of the MOM capacitor are metal-joined and connected to the ground terminal. Schematic diagram. 8 is a schematic diagram of the connection symbols when the first shield part and the second shield part of the MOM capacitor are connected to the ground terminal after metal bonding. In this embodiment, when the first shielding part 5 and the second shielding part 6 are at the same potential, their connection symbols are as shown in Figure 8. The connection symbols include the terminals of the first electrode, the terminals of the second electrode and a ground. Three-terminal connection symbol for terminal.

Please refer to Figures 2, 9 and 10. In another embodiment of the present invention, Figure 9 is a schematic diagram of the parasitic capacitance when the first shielding part and the second shielding part of the MOM capacitor are connected to different ground terminals. FIG. 10 is a schematic diagram of the connection symbols when the first shielding part and the second shielding part of the MOM capacitor are connected to different ground terminals. In this embodiment, when the first shielding part 5 and the second shielding part 6 are at different potentials, their connection symbols are as shown in Figure 10. The connection symbols include the terminals of the first electrode, the terminals of the second electrode, and the terminals of the second electrode. A four-terminal connection symbol for a ground terminal GND1 and a second ground terminal GND2. In addition, in the four-terminal connection symbol, the first ground terminal GND1 and the second ground terminal GND2 can be marked as a common GND, and can also be used as a three-terminal connection symbol.

Please refer to FIGS. 6 to 10 . In one embodiment of the present invention, the three-terminal connection symbol and the four-terminal connection symbol represent the MOM capacitor and the first shielding part and the second shielding part disposed on both sides of the MOM capacitor. The symbol of the connection state is stored in the storage unit 101 in the form of symbol data sym. In addition, the storage unit 101 also stores connection information of wiring between components in a circuit diagram and a layout diagram generated based on the operation of a designer to be described later. Specifically, for example, the storage unit 101 stores circuit diagram data SD including connection information (net list) between components in the circuit diagram, and layout data LD including connection information (net list) between components in the layout diagram.

Referring to FIGS. 5 to 10 , in an embodiment of the present invention, in the design assistance device 10 , the circuit diagram design assistance unit 102 a uses the stored symbol data sym to assist in the circuit design of the semiconductor device. Among them, the circuit diagram design assisting unit 102a accepts input operations via the input unit 15, and is connected to the storage unit 101 so as to enable bidirectional communication. By using the circuit diagram design assisting unit 102a, using the symbol data sym stored in the storage unit 101, a circuit diagram of the electronic device circuit to be designed can be created. The circuit diagram data SD created by the circuit diagram design assisting unit 102a can be stored in the storage unit 101. In this embodiment, in addition to the four-terminal connection symbols, any implementable method can be selected for the circuit design assisting technology of other semiconductor devices. That is, any implementable method can be selected for the circuit diagram design assisting unit 102a involved in this embodiment. It is a well-known technical method, and the present invention is not limited to this.

Referring to FIGS. 5 and 6 , in an embodiment of the present invention, in the design assisting device 10 , the layout design assisting unit 102 b assists in the design of the layout of the semiconductor device. The floor plan design assisting unit 102b accepts input operations via the input unit 15 and is connected to the storage unit 101 so as to enable bidirectional communication. By using the layout design assisting unit 102b, using the symbol data sym stored in the storage unit 101, a layout diagram of the electronic device circuit to be designed can be created. The layout data LD created by the layout design assisting unit 102b can be stored in the storage unit 101. The present invention does not limit the specific implementation of the design assistance technology of the layout diagram of the semiconductor device, and any known technology that can be implemented can be selected.

Referring to FIGS. 5 and 6 , in an embodiment of the present invention, in the design assistance device 10 , the verification unit 103 is used to verify whether the connection information between the components shown in the layout diagram and the circuit diagram of the semiconductor device matches. Specifically, the verification unit 103 compares the connection information between each component in the circuit diagram data SD and the connection information between each component in the layout data LD based on the circuit diagram data SD and layout data LD stored in the storage unit 101 to verify. Whether the connection information matches. In addition, the verification unit 103 also includes, for example, a netlist extraction unit 103a and a comparison unit 103b in order to perform Layout Versus Schematics (LVS) verification described later.

Please refer to FIGS. 5 to 6 . In one embodiment of the present invention, in the design assistance device 10 , the netlist extraction unit 103 a extracts the circuit diagram data SD and layout data LD of the electronic device circuit stored in the storage unit 101 As input, netlists are extracted separately. For electronic device circuits, the comparison unit 103b is used to compare the netlist extracted from the circuit diagram data SD and the netlist extracted from the layout data LD to determine whether they are equal. The verification unit 103 displays the comparison result of the comparison unit 103b on the display unit 16 to determine whether the connection information of the circuit diagram and the layout diagram match, that is, whether they are equal, and notifies the designer of the evaluation result.

Please refer to Figures 5 and 6. In another embodiment of the present invention, the layout design auxiliary unit 102b and the verification unit 103 may not be provided in the design auxiliary device 10. For example, the layout design auxiliary unit 102b may be selected. Do it using other computer systems. At the same time, the verification unit 103 also selects other computer systems to obtain circuit diagram data designed by the design assistance device 10 and layout data designed by other computer systems via communication media, and uses these data to perform LVS verification.

Please refer to FIG. 1 and FIG. 11. In an embodiment of the present invention, FIG. 11 is a flow chart of the LVS verification process involved in this embodiment. In LVS verification, it is verified that in the logic circuit design stage, the components produced and the connection information between components are properly implemented in the layout design. Specifically, in the LVS verification, the netlist extracted based on the circuit diagram data SD is compared with the netlist extracted based on the layout data LD of the electronic device circuit 8 to verify whether they are equivalent.

Please refer to Figures 6 and 11. In one embodiment of the present invention, in step S11, the netlist extraction unit 103a in the verification unit 103 extracts a netlist containing connection information between components obtained from the circuit diagram data SD. . In step S12, the net list extraction unit 103a in the verification unit 103 extracts a net list using the connection information between components in the layout data LD restored from the layout data LD.

Referring to FIG. 6 and FIG. 11 , in an embodiment of the present invention, in step S13 to step S16 , the verification unit 103 performs LVS verification. Specifically, the verification unit 103 compares the netlist extracted based on the circuit diagram data SD and the netlist extracted based on the layout data LD, and then determines whether the netlist extracted from the circuit diagram data SD is consistent with the netlist extracted from the layout data LD. If the netlist of the circuit diagram data SD matches the netlist extracted from the layout data LD, a normal determination is made. If the netlist of the circuit diagram data SD does not match the netlist extracted from the layout data LD, the verification unit 103 makes an error determination.

Please refer to FIGS. 1 to 10 . In one embodiment of the present invention, the semiconductor device design assisting device 10 has a first shielding portion 5 and a second shielding portion 6 in the semiconductor device 1 having a MOM capacitor 2 . The four-terminal connection symbols connected to different ground terminals enable the design of a semiconductor device in which the first shield portion 5 and the second shield portion 6 are connected to different ground terminals. It is possible to avoid the problem that the first shielding part 5 and the second shielding part 6 are directly connected, causing an area that is too large and is not conducive to layout. Moreover, the design assisting device 10 can avoid being unable to design due to the absence of a connection symbol representing such a circuit among the three-terminal connection symbols when the first shielding part 5 and the second shielding part 6 are connected to different ground terminals. Ensure the smooth progress of the design. At the same time, when designing the connection method for connecting the first shielding part 5 and the second shielding part 6 to different ground terminals, it is possible to avoid replacing the existing three-terminal connection symbols and avoid causing the netlist extracted based on the circuit diagram data SD to be inconsistent with the layout-based The netlist extracted by data LD becomes inconsistent, thereby avoiding erroneous judgments in LVS verification and ensuring the accuracy of LVS verification of semiconductor devices. Therefore, the first shielding part and the second shielding part provided by the present application are connected to the semiconductor device with different ground terminals, breaking through the limitation of the semiconductor device with the three-terminal connection symbol.

Referring to FIGS. 10 and 12 , in one embodiment of the present invention, in a design aid for a semiconductor device, there is a four-terminal connection symbol as one of the connection symbols. Therefore, when designing a circuit, the four-terminal connection symbol is used. Connection symbols can increase the degree of freedom in the design of semiconductor devices. And by using the design aid of the semiconductor device adopted in this embodiment, the first shielding part and the second shielding part are allowed to be connected to different ground terminals, which can avoid the need to surround the MOM capacitor with the shielding metal as shown in FIG. 12 The layers are connected at both ends. That is, the semiconductor device provided by the present invention can increase the degree of freedom in wiring processing, increase the degree of freedom in circuit design, and achieve miniaturization of the semiconductor device. Furthermore, by using symbols corresponding to actual circuits when creating design drawings, erroneous output related to connection information during LVS verification can be reduced and the efficiency of design work can be improved.

As described above, the present invention provides a semiconductor device and a semiconductor device design assisting device that can reduce the number of wiring connections and wiring in the semiconductor device by not connecting the first shield portion and the second shield portion in the wiring space. The area of the space enables the semiconductor device to be miniaturized. By having the first shielding part and the second shielding part having independent terminals and being connected to ground terminals with different potentials, the freedom of wiring of each terminal of the semiconductor device can be improved, the wiring requirements of different circuits can be met, and the semiconductor device can be improved Design freedom related to wiring. By using symbols corresponding to actual circuits when creating design drawings, erroneous output related to connection information during LVS verification can be reduced and the efficiency of design work can be improved.

Reference throughout this specification to "one embodiment," "anembodiment," or "a specific embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment includes In at least one embodiment of the invention, and not necessarily in all embodiments. Thus, various references to the phrases "in one embodiment," "inan embodiment," or "in a specific embodiment" are used in various places throughout this specification. Representations do not necessarily refer to the same embodiment. Furthermore, the particular features, structures, or characteristics of any particular embodiment of the invention may be combined in any suitable manner with one or more other embodiments. It will be understood that other variations and modifications of the embodiments of the invention described and illustrated herein are possible in light of the teachings herein and will be considered part of the spirit and scope of the invention.

The embodiments of the present invention disclosed above are only used to help explain the present invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Obviously, many modifications and variations are possible in light of the contents of this specification. These embodiments are selected and described in detail in this specification to better explain the principles and practical applications of the present invention, so that those skilled in the art can better understand and utilize the present invention. The invention is limited only by the claims and their full scope and equivalents.

Claims (9)

1. A design auxiliary device for semiconductor devices, used for the design of semiconductor devices, characterized in that it includes: A storage unit to store a plurality of symbols constituting the connection status of a plurality of elements in the semiconductor device, the symbols including four terminals representing the connection status of the first electrode, the second electrode, the first shield part and the second shield part. connecting symbols; and a circuit diagram design assisting unit to call the symbols stored in the storage unit to design the circuit diagram of the semiconductor device; Wherein, the semiconductor device includes: MOM capacitor, the MOM capacitor includes a plurality of first electrodes and a plurality of second electrodes, and the first electrodes and the second electrodes are alternately arranged in a first direction, the first electrodes or the second electrodes The electrodes are stacked in a second direction, wherein the first direction and the second direction are perpendicular; The first shielding part is located on one side of the MOM capacitor in the second direction, and the area between the first shielding part and the MOM capacitor is electrically insulated; and The second shielding part is located on the other side of the MOM capacitor in the second direction, and the area between the second shielding part and the MOM capacitor is electrically insulated. 2. The design assisting device for a semiconductor device according to claim 1, wherein the design assisting device further includes: a layout design assisting unit to assist in the design of the layout of the semiconductor device; and The verification unit compares the connection information between each component in the circuit diagram data with the connection information between each component in the layout data to verify whether the connection information matches. 3. The design assistance device for a semiconductor device according to claim 2, wherein the connection information between components in the circuit diagram data and the connection information between components in the layout data are stored in the storage unit . 4. The design assisting device for a semiconductor device according to claim 1, wherein the first shield part and the second shield part are connected to ground terminals having different potentials. 5. The design aid for a semiconductor device according to claim 4, wherein the ground terminal includes a first ground terminal and a second ground terminal, and the potentials of the first ground terminal and the second ground terminal are different. 6. The design assisting device for a semiconductor device according to claim 5, wherein the first shielding portion is connected to the first ground terminal or the second ground terminal, and the second shielding portion is connected to the first ground terminal or the second ground terminal. The second ground terminal or the first ground terminal is connected. 7. The design aid for a semiconductor device according to claim 1, wherein the first electrode has at least one first main line. 8. The design aid for a semiconductor device according to claim 7, wherein the second electrode has at least one second main line, and the second main line and the first main line are in the first direction. Alternate settings. 9. The design assistance device for a semiconductor device according to claim 1, wherein in the first direction, wiring spaces are provided on both sides of the MOM capacitor, and in the wiring space, the The first shielding part and the second shielding part are electrically insulated.