CN107231154B - Multi-module shared pipeline stage circuit structure for low-power consumption pipeline ADC - Google Patents

Abstract

The invention discloses a multi-module shared pipeline stage circuit structure for a low power consumption pipeline ADC, wherein the first multiplying digital-analog unit MDAC1 and the second multiplying digital-analog unit MDAC2 time-division multiplex the third capacitors C _f1 , The fourth capacitor C _f2 and the first operational amplifier OPA; sub_ADC1 and sub_ADC2 time-division multiplexing Latch1 and Latch2; when the clock phase Φ1 is at a high level, C _f1 samples the reference level V _dac2 , and C _f2 is used as a feedback capacitor and OPA. Realize the functions of subtraction, remainder, and redundant amplification of MDAC2; when the clock phase Φ2 is at a high level, C _f1 and C _f2 are used as the feedback capacitors of MDAC1 and OPA to realize the functions of subtraction, remainder, and redundancy amplification of MDAC1. At the same time, C _f1 and C _f2 are used as the sampling capacitors of MDAC2 to complete the sampling operation of MDAC2; Latch1 and Latch2 realize the comparison between the input signal of sub_ADC1 and the reference threshold when the clock phase Φ1 is high level; when the clock phase Φ2 is high level, Implements the comparison of the sub_ADC2 input signal with the reference threshold. The invention can reduce the power consumption of the pipeline ADC and improve the conversion precision.

Description

Multi-module shared pipeline stage circuit structure for low-power consumption pipeline ADC

Technical Field

The invention relates to the field of analog-to-digital converters, in particular to a multi-module shared pipeline stage circuit structure for a low-power-consumption pipeline ADC.

Background

With the rapid development of semiconductor technology, high-speed and high-precision analog-to-digital converters have been widely used in the fields of digital communication, military radar, and the like. A Pipeline analog-to-digital converter (Pipeline ADC) is one of mainstream ADC products at present, and requirements on speed and precision can be well met. In the pipeline analog-to-digital converter, a single pipeline stage circuit is used as an important component to determine the performance of the whole pipeline analog-to-digital converter.

In a traditional low-power consumption assembly line ADC, power consumption is reduced by adopting operational amplifier sharing and capacitor sharing, but due to continuous work of the operational amplifier and the capacitor, the problems of memory effect and stability exist, so that the precision of the ADC is reduced, and meanwhile, the speed of the ADC is limited due to switches introduced by the operational amplifier sharing and the capacitor sharing; the other solution is to adopt a switch operational amplifier technology, but the pipeline ADC of the switch operational amplifier structure has the problem that the system speed is limited by the on and off operations of each clock phase operational amplifier. Meanwhile, the input capacitors of the operational amplifier are different in different clock phases of the input geminate transistors which are switched on and off, so that the feedback coefficient and the gain of the operational amplifier are changed.

Disclosure of Invention

The technical problem is as follows: in order to overcome the defects in the prior art, the invention provides a multi-module shared pipeline stage circuit structure with three-phase clock control, shared operational amplifiers, shared capacitors and shared comparators, so that the number of operational amplifiers and comparators in the circuit is reduced, and the power consumption of the system is reduced.

The technical scheme is as follows: in order to achieve the purpose, the invention adopts the technical scheme that:

a multi-module shared pipeline stage circuit structure suitable for a low-power consumption pipeline ADC comprises a first multiplying digital-to-analog unit (MDAC1), a first inter-stage ADC (sub _ ADC1), a second multiplying digital-to-analog unit (MDAC2) and a second inter-stage ADC (sub _ ADC 2); the first multiplying digital-to-analog unit (MDAC1) and the second multiplying digital-to-analog unit (MDAC2) time-division multiplex a third capacitor (C)_f1) A fourth capacitor (C)_f2) And a first operational amplifier (OPA); the first inter-stage ADC (sub _ ADC1) and the second inter-stage ADC (sub _ ADC2) time-division multiplex a first Latch (Latch1) and a second Latch (Latch 2);

the third capacitor (C) is arranged when the clock phase phi 1 is at a high level_f1) For reference level V_dac2Sampling, fourth capacitance (C)_f2) The feedback capacitor and the first operational amplifier (OPA) are used as a module unit of a second multiplying digital-to-analog unit (MDAC2) to realize the functions of subtraction, remainder and redundant amplification of the second multiplying digital-to-analog unit (MDAC 2); the third phase when the clock phase Φ 2 is highCapacitance (C)_f1) And a fourth capacitance (C)_f2) The feedback capacitor of the first multiplying digital-to-analog unit (MDAC1) and the first operational amplifier (OPA) realize the functions of subtraction, remainder and redundancy amplification of the first multiplying digital-to-analog unit (MDAC1), and meanwhile, the third capacitor (C)_f1) And a fourth capacitance (C)_f2) As the sampling capacitance of the second multiplying digital-to-analog unit (MDAC2), completing the sampling operation of the second multiplying digital-to-analog unit (MDAC 2); the third capacitor (C) is at high level of the clock phase Phia_f1) And a fourth capacitance (C)_f2) The first operational amplifier (OPA) performs reset operation to eliminate memory effect;

the first Latch (Latch1) and the second Latch (Latch2) are used as a first inter-stage ADC (sub _ ADC1) comparator when the clock phase phi 1 is at a high level, so that comparison between an input signal and a reference threshold value is realized; when the clock phase Φ 2 is at a high level, the comparator is used as a second inter-stage ADC (sub _ ADC2) to realize comparison between the input signal and the reference threshold; when the clock phase Φ a1 is at a high level, a reset operation is performed;

the clock phase Φ a has a high level before the rising edge of the clock phase Φ 2 arrives, and the clock phase Φ a1 has a high level before the rising edges of the clock phase Φ 1 and the clock phase Φ 2 arrive.

In a specific embodiment, the first multiplying digital-to-analog unit (MDAC1) comprises a first capacitor (C)_s1) A second capacitor (C)_s2) A third capacitor (C)_f1) A fourth capacitor (C)_f2) The circuit comprises a first switch (S1), a second switch (S2), a fifth switch (S5), a sixteenth switch (S16), a seventeenth switch (S17), a twenty-second switch (S22), a twentieth switch (S23), a twenty-fourth switch (S24), a twenty-fifth switch (S25), a first coding circuit (Decoder1), a thirty-second switch (S32), a thirty-third switch (S33) and a first operational amplifier (OPA);

the second multiplying digital-to-analog unit (MDAC2) comprises a third capacitor (C)_f1) A fourth capacitor (C)_f2) An eighth switch (S8), a thirteenth switch (S13), a fourteenth switch (S14), a fifteenth switch (S15), a twenty-second switch (S22), a second encoding circuit (Decoder2), and a first operational amplifier (OPA);

wherein the first capacitor (C)_s1) Right polar plate and second capacitor (C)_s2) The right pole plate is connected with the upper end of the fifth switch (S5) and the left end point of the twenty-fifth switch (S25), and the left pole plate is connected with the right end point of the first switch (S1) and the right end point of the twenty-fourth switch (S24); left terminal of first switch (S1) and input signal V_inConnected to a second switch (S2); the left side of the twenty-fourth switch (S24) is connected to ground; a second capacitance (C)_s2) The left side is connected with the right side of the second switch (S2), the right side of the twentieth switch (S23), and the left side of the twentieth switch (S23) is connected with the reference level V_dac1(ii) a Third capacitance (C)_f1) And a fourth capacitance (C)_f2) The left side of the first operational amplifier is connected with the upper side of a sixteenth switch (S16) and the right side of a twenty-fifth switch (S25), and is connected with the negative input end of the first operational amplifier (OPA); the lower side of the sixteenth switch (S16) is connected with the ground level and is connected with the positive input end of the first operational amplifier (OPA); third capacitance (C)_f1) The right side is connected with the left side of a twenty-second switch (S22) and the left side of a fifteenth switch (S15), and a fourth capacitor (C)_f2) The right side of the second switch is connected with the right side of a twenty-second switch (S22), the upper side of a seventeenth switch (S17) and the left side of an eighth switch (S8), and is also connected with the output end of a first operational amplifier (OPA); the output end of the first coding circuit (Decoder1) controls the state of the twentieth switch (S23); the working state of the first coding circuit (Decoder1) is controlled by a thirty-third switch (S33) and a thirty-second switch (S32);

the right side of the eighth switch (S8) is connected to the third stage input, and the right side of the fifteenth switch (S15) is connected to the reference level V_dac2The control end of the fifteenth switch (S15) is connected with the output of the second coding circuit (Decoder2), and the second coding circuit (Decoder2) is controlled by a thirteenth switch (S13) and a fourteenth switch (S14);

the first switch (S1), the second switch (S2), the eighth switch (S8), the thirteenth switch (S13) and the fourteenth switch (S14) are controlled by the clock phase Φ 1, the twenty-second switch (S22) is controlled by the inverted clock of the clock phase Φ 1, the twenty-fourth switch (S24), the twenty-fifth switch (S25), the thirty-third switch (S33) and the thirty-twelfth switch (S32) are controlled by the clock phase Φ 2, and the sixteenth switch (S16) and the seventeenth switch (S17) are controlled by the clock phase Φ 2_aControlling, the fifth switch (S5) is controlled by the clock phase phi 1E; wherein the falling edge ratio of the clock phase phi 1E isThe falling edge of the clock phase Φ 1 advances.

In a specific embodiment, the first inter-stage ADC (sub _ ADC1) includes a third switch (S3), a fourth switch (S4), a sixth switch (S6), a seventh switch (S7), an eighteenth switch (S18), a nineteenth switch (S19), a twentieth switch (S20), a twenty-first switch (S21), a twenty-sixth switch (S26), a twenty-seventh switch (S27), a fifth capacitor (C) and a third capacitor (C) and a fourth capacitor (C) and a fifth capacitor (C) and a sixth capacitor (C) and a fifth capacitor (C) are connected_sc11) A sixth capacitor (C)_sc12) A first Latch (Latch1) and a second Latch (Latch 2);

the second inter-stage ADC (sub _ ADC2) comprises a ninth switch (S9), a tenth switch (S10), an eleventh switch (S11), a twelfth switch (S12), a twenty-eighth switch (S28), a twenty-ninth switch (S29), a thirty-third switch (S30), a thirty-third switch (S31), and a seventh capacitor (C)_sc21) An eighth capacitor (C)_sc22) A first Latch (Latch1) and a second Latch (Latch 2);

fifth capacitance (C)_sc11) The left side is connected with the right side of the third switch (S3) and the upper side of the eighteenth switch (S18), and the lower side of the eighteenth switch (S18) is connected with a threshold voltage Vth 1; the left side of the third switch (S3) is connected with the left side of the fourth switch (S4), and is connected with an input signal; fifth capacitance (C)_sc11) The right side of the first Latch (Latch1) is connected with the upper side of a sixth switch (S6) and is connected with the input end of a preventive amplifier 1(pre1), the output end of the preventive amplifier 1(pre1) is connected with the left side of a twenty-sixth switch (S26), the right side of the twenty-sixth switch (S26) is connected with the input end of a first Latch (Latch1), and the reset of the first Latch (Latch1) is controlled by a twentieth switch (S20); sixth capacitance (C)_sc12) The left side is connected with the right side of a fourth switch (S4) and the upper side of a nineteenth switch (S19), and the lower side of the nineteenth switch (S19) is connected with a threshold voltage Vth 2; sixth capacitance (C)_sc12) The right side of the second switch (S7) is connected with the upper side of a seventh switch (S7) and is connected with the input end of a preventive amplifier 2(pre2), the output end of the preventive amplifier 2(pre2) is connected with the left side of a twenty-seventh switch (S27), the right side of the twenty-seventh switch (S27) is connected with the input end of a second Latch (Latch2), and the reset of the second Latch (Latch2) is controlled by the twenty-first switch (S21);

the right side of the twenty-eighth switch (S28) is connected with the right side of the twenty-ninth switch (S29) and is connected with the output end of the first operational amplifier (OPA), the left side of the twenty-eighth switch (S28) is connected with the upper side of the tenth switch (S10) andseventh capacitance (C)_sc21) Right side connected to a seventh capacitor (C)_sc21) The left side of the switch is connected with the upper side of a thirtieth switch (S30) and the right side of a twelfth switch (S12), and the left side of the twelfth switch (S12) is connected with the input end of a first Latch (Latch 1); the left side of the twenty-ninth switch (S29), the upper side of the ninth switch (S9) and the eighth capacitor (C)_sc22) Right side connected to an eighth capacitor (C)_sc22) The left side of the second Latch (Latch2) is connected with the upper side of a thirty-one switch (S31) and the right side of an eleventh switch (S11), and the left side of the eleventh switch (S11) is connected with the input end of a second Latch (Latch 2);

a third switch (S3), a fourth switch (S4), a ninth switch (S9), a tenth switch (S10), an eleventh switch (S11) and a twelfth switch (S12) are controlled by the clock phase Φ 1, a twenty-sixth switch (S26), a twenty-seventh switch (S27), a twenty-eighteen switch (S28) and a twenty-ninth switch (S29) are controlled by the clock phase Φ 2, an eighteenth switch (S18) and a nineteenth switch (S19) are controlled by the clock phase Φ a, a sixth switch (S6) and a seventh switch (S7) are controlled by the clock phase Φ 1E, a thirtieth switch (S30) and a thirty-eleventh switch (S31) are controlled by the clock phase Φ 2E, and a twentieth switch (S20) and a twenty-first switch (S21) are controlled by the clock phase Φ a 1; the falling edge of the clock phase phi 1E is earlier than that of the clock phase phi 1, and the falling edge of the clock phase phi 2E is earlier than that of the clock phase phi 2.

Has the advantages that: the multi-module shared pipeline stage circuit structure suitable for the three-phase clock control operational amplifier sharing, the capacitor sharing and the comparator sharing of the low-power consumption pipeline ADC has the advantages that the first MDAC (MDAC1) sampling path and the first inter-stage ADC (sub-ADC 1) sampling path are completely matched through the introduction of the three-phase clock, the aperture error is eliminated, the problem of memory effect in the design of the operational amplifier sharing and the capacitor sharing is solved, and the system precision is improved. Meanwhile, the number of operational amplifiers and the number of comparators in the former two-stage pipeline stage circuit are reduced by half by realizing the multi-module sharing structure, the power consumption of the system is reduced, the low-power-consumption design is realized, and the multi-module sharing structure is suitable for the low-power-consumption pipeline ADC.

Drawings

FIG. 1 is a circuit diagram of an embodiment of the present invention;

FIG. 2 is a circuit diagram of a three-phase clock in an embodiment of the present invention;

FIG. 3 is a timing diagram illustrating operation of the present invention when the clock phase Φ 1 is high;

FIG. 4 is a timing diagram illustrating operation of the present invention when the clock phase Φ a is high;

fig. 5 is a timing chart illustrating the operation of the embodiment of the present invention when the clock phase Φ 2 is high.

Detailed Description

The technical solution of the present invention is described in detail below with reference to the accompanying drawings and embodiments.

The embodiment of the invention discloses a multi-module shared pipeline stage circuit structure for a low-power consumption pipeline ADC, which consists of a first multiplication digital-analog unit (MDAC1), a first inter-stage ADC (sub _ ADC1), a second multiplication digital-analog unit (MDAC2) and a second inter-stage ADC (sub _ ADC 2). Wherein the first multiplying digital-to-analog unit (MDAC1) and the second multiplying digital-to-analog unit (MDAC2) time-division multiplex the third capacitor (C)_f1) A fourth capacitor (C)_f2) And a first operational amplifier (OPA); the first inter-stage ADC (sub _ ADC1) and the second inter-stage ADC (sub _ ADC2) time-division multiplex the first Latch (Latch1) and the second Latch (Latch2), and the time-division multiplexing of the shared devices is realized by controlling the three-phase clock. A third capacitor (C) when the first clock phase phi 1 is at a high level_f1) For reference level V_dac2Sampling, fourth capacitance (C)_f2) The feedback capacitor and the first operational amplifier (OPA) are used as module units of a second multiplying digital-to-analog unit (MDAC2) to realize the functions of subtraction, remainder and redundant amplification of the second multiplying digital-to-analog unit (MDAC 2); a third capacitor (C) when the second clock phase phi 2 is at high level_f1) And a fourth capacitance (C)_f2) The feedback capacitor of the first multiplying digital-to-analog unit (MDAC1) and the first operational amplifier (OPA) realize the functions of subtraction, remainder and redundant amplification of the first multiplying digital-to-analog unit (MDAC1), and meanwhile, the third capacitor (C)_f1) And a fourth capacitance (C)_f2) As the sampling capacitance of the second multiplying digital-to-analog unit (MDAC2), completing the sampling operation of the second multiplying digital-to-analog unit (MDAC 2); the first Latch (Latch1) and the second Latch (Latch2) are used as a first inter-stage ADC (sub _ ADC1) comparator when the first clock phase Φ 1 is at a high level, so as to compare the input signal with a reference threshold; in the second clock phase phiWhen 2 is high level, the comparator is used as a comparator of the second inter-stage ADC (sub _ ADC2) to realize the comparison between the input signal and the reference threshold; the shared device is reset under the control of the third clock phase to eliminate the memory effect. FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, and in FIG. 1, a first multiplying digital-to-analog unit (MDAC1) includes a first capacitor (C)_s1) A second capacitor (C)_s2) A third capacitor (C)_f1) A fourth capacitor (C)_f2) The circuit comprises a first switch (S1), a second switch (S2), a fifth switch (S5), a sixteenth switch (S16), a seventeenth switch (S17), a twenty-second switch (S22), a twentieth switch (S23), a twenty-fourth switch (S24), a twenty-fifth switch (S25), a first coding circuit (Decoder1), a thirty-third switch (S32), a thirty-third switch (S33) and a first operational amplifier (OPA). Wherein the first capacitor (C)_s1) Right polar plate and second capacitor (C)_s2) The right pole plate is connected with the upper end of the fifth switch (S5) and the left end point of the twenty-fifth switch (S25), and the left pole plate is connected with the right end point of the first switch (S1) and the right end point of the twenty-fourth switch (S24). Left terminal of first switch (S1) and input signal V_inConnected to the second switch (S2). The left side of the twenty-fourth switch (S24) is connected to ground. A second capacitance (C)_s2) The left side is connected with the right side of the second switch (S2), the right side of the twentieth switch (S23) is connected, and the left side of the twentieth switch (S23) is connected with V_dac1. Third capacitance (C)_f1) And a fourth capacitance (C)_f2) The left side is connected with the upper side of a sixteenth switch (S16) and the right side of a twenty-fifth switch (S25), and is connected with the negative input end of a first operational amplifier (OPA). The sixteenth switch (S16) has its underside connected to ground and to the positive input of the first operational amplifier (OPA). Third capacitance (C)_f1) The right side is connected with the left side of a twenty-second switch (S22) and the left side of a fifteenth switch (S15), and a fourth capacitor (C)_f2) The right side is connected with the right side of a twenty-second switch (S22), the upper side of a seventeenth switch (S17) and the left side of an eighth switch (S8), and is also connected with the output end of a first operational amplifier (OPA). The output terminal of the first encoding circuit (Decoder1) controls the state of the twentieth switch (S23). The working state of the first coding circuit (Decoder1) is controlled by the thirty-third switch (S33) and the thirty-second switch (S32), and the other side of the switches is respectively arranged at the first Latch (Latch1)And a second Latch (Latch 2).

The first inter-stage ADC (sub _ ADC1) comprises a third switch (S3), a fourth switch (S4), a sixth switch (S6), a seventh switch (S7), an eighteenth switch (S18), a nineteenth switch (S19), a twentieth switch (S20), a twenty-first switch (S21), a twenty-sixth switch (S26), a twenty-seventh switch (S27), a fifth capacitor (C19)_sc11) A sixth capacitor (C)_sc12) A first Latch (Latch1) and a second Latch (Latch 2).

Wherein the fifth capacitor (C)_sc11) The left side is connected with the upper side of an eighteenth switch (S18) on the right side of a third switch (S3), and the lower side of the eighteenth switch (S18) is connected with a threshold voltage V_th1. The left side of the third switch (S3) is connected with the left side of the fourth switch (S4), and is connected with the input signal. Fifth capacitance (C)_sc11) Is connected with the upper side of a sixth switch (S6) and is connected with the input end of a preventive amplifier 1(pre1), the output end of the preventive amplifier 1(pre1) is connected with the left side of a twenty-sixth switch (S26), the right side of the twenty-sixth switch (S26) is connected with the input end of a first Latch (Latch1), and the reset of the first Latch (Latch1) is controlled by the twentieth switch (S20).

Sixth capacitance (C)_sc12) The left side is connected with the upper side of a nineteenth switch (S19) at the right side of the fourth switch (S4), and the lower side of the nineteenth switch (S19) is connected with a threshold voltage V_th2. Sixth capacitance (C)_sc12) Is connected with the upper side of a seventh switch (S7) and is connected with the input end of a preventive amplifier 2(pre2), the output end of the preventive amplifier 2(pre2) is connected with the left side of a twenty-seventh switch (S27), the right side of the twenty-seventh switch (S27) is connected with the input end of a second Latch (Latch2), and the reset of the second Latch (Latch2) is controlled by the twenty-first switch (S21).

The second multiplying digital-to-analog unit (MDAC2) comprises a third capacitor (C)_f1) A fourth capacitor (C)_f2) The switch comprises an eighth switch (S8), a thirteenth switch (S13), a fourteenth switch (S14), a fifteenth switch (S15), a twenty-second switch (S22), a second coding circuit (Decoder2) and a first operational amplifier (OPA).

Wherein the third capacitor (C)_f1) A fourth capacitor (C)_f2) The first operational amplifier (OPA) is shared with the first multiplying digital-to-analog unit (MDAC1) and is connected in the same way. The right side of the eighth switch (S8) is connected with the third stage input and the tenthThe right side of the five-switch (S15) is connected with a reference level V_dac2The control end of the fifteenth switch (S15) is connected with the output of the second coding circuit (Decoder2), the second coding circuit (Decoder2) is controlled by a thirteenth switch (S13) and a fourteenth switch (S14), the left side of the thirteenth switch (S13) is connected with the output of the second Latch (Latch2) and the left side of the thirty-third switch (S32), and the left side of the fourteenth switch (S14) is connected with the output of the first Latch (Latch1) and the left side of the thirty-third switch (S33).

The second inter-stage ADC (sub _ ADC2) includes a ninth switch (S9), a tenth switch (S10), an eleventh switch (S11), a twelfth switch (S12), a twenty-eighth switch (S28), a twenty-ninth switch (S29), a thirty-third switch (S30), a thirty-third switch (S31), and a seventh capacitor (C30)_sc21) An eighth capacitor (C)_sc22) A first Latch (Latch1), a second Latch (Latch 2).

The first Latch (Latch1), the second Latch (Latch2), and the first inter-stage ADC (sub _ ADC1) are shared. The right side of the twenty-eighth switch (S28) is connected with the right side of the twenty-ninth switch (S29) and is connected with the output end of the first operational amplifier (OPA), the left side of the twenty-eighth switch (S28), the upper side of the tenth switch (S10) and the seventh capacitor (C)_sc21) Right side connected to a seventh capacitor (C)_sc21) The left side is connected with the upper side of the thirtieth switch (S30) and the right side of the twelfth switch (S12), and the left side of the twelfth switch (S12) is connected with the input end of the first Latch (Latch 1). The left side of the twenty-ninth switch (S29), the upper side of the ninth switch (S9) and the eighth capacitor (C)_sc22) Right side connected to an eighth capacitor (C)_sc22) The left side is connected with the upper side of the thirty-first switch (S31) and the right side of the eleventh switch (S11), and the left side of the eleventh switch (S11) is connected with the input end of the second Latch (Latch 2).

FIG. 2 is a circuit diagram of a three-phase clock used in the embodiment of the present invention, in which Φ 1, Φ_a1Phi 2 is a three-phase clock, phi_aThe high level exists only before the rising edge of phi 2, which is used for resetting the operational amplifier and the capacitor_a1The high level exists before rising edges of phi 1 and phi 2 arrive, the high level is used for resetting Latch1 and Latch2, the falling edge of phi 1E is slightly ahead of the falling edge of phi 1, the falling edge of phi 2E is slightly ahead of the falling edge of phi 2, and the purpose is to realize lower-level board sampling to reduce the sampling frequency of the lower-level boardSmall charge injection and clock feedthrough effects.

Is the inverse clock phase of Φ 1.

In the circuit shown in FIG. 1, the switches S1-S4, S8-S14 are controlled by the clock phase phi 1, the switches S5-S7 are controlled by the clock phase phi 1E, and the switches S16-S19 are controlled by the clock phase phi_aControl, S20, S21 by clock phase phi_a1Control, S22 is clocked by the inverse of the clock phase Φ 1

The switches S24 to S29, S32, and S33 are controlled by the clock phase Φ 2, and the switches S30 and S31 are controlled by the clock phase Φ 2E.

The working process of the multi-module shared pipeline stage circuit structure comprises the following steps:

(1) when sampling phase phi 1, switches S1-S15 are closed, and sampling capacitor C of first multiplying digital-to-analog unit (MDAC1)_s1、C_sc2And a sampling capacitor C of the first inter-stage ADC (sub _ ADC1)_sc11、C_sc11For input signals V simultaneously_inSampling is carried out, when the falling edge of phi 1E arrives, the switches S5-S7 are turned off in advance, lower-level plate sampling is completed, and charge injection and clock feed-through effect introduced by the switches can be reduced. Meanwhile, Latch1, Latch2 and logic encoder 2 form a second inter-stage ADC (sub _ ADC2) to obtain the digital code of the second pipeline stage and the digital control signal of the second multiplying digital-to-analog unit (MDAC2), C_f1And a reference level V_dac2Are connected to each other, C_f2And as a feedback capacitor, a second multiplication digital-to-analog unit (MDAC2) is formed by the operational amplifier to amplify the redundant signals of the second stage pipeline stage. Reference level V_dac2Controlled by the digital output of clock phase phi 1 and the second stage ADC (sub _ ADC2), and respectively has a value of-V according to the different amplitudes of the input signals of the current stage pipeline stage_ref、V_cm、V_ref。

(2) When Φ a is high, the switches S16 to S22 are closed, and the sampling capacitor C of the first inter-stage ADC (sub _ ADC1)_sc11、C_sc12For comparison threshold voltage V_{thi,(i＝1,2)}Sampling is carried outAnd completing the differential voltage (V) pair through a pre-amplification stage_in-V_{thi,(i＝1,2)}) At this time, the operational amplifier and the capacitor C_f1、C_f2A reset operation is performed in order to eliminate the influence of the memory effect, and Latch1 and Latch2 are reset at Φ a1 clock phase.

(3) When the phi 2 clock phase is high, the switches S22-S33 are closed, the Latch1, the Latch2 and the logic coding circuit Decoder1 form a first inter-stage ADC (sub _ ADC1) which outputs a digital code of a first stage pipeline stage and a digital control signal of a first multiplication digital-to-analog unit (MDAC1), and the capacitor C_s1Connected to a common mode level, C_s2And a reference level V_dac1Are connected to each other, C_f1、C_f2For feedback capacitance, a first multiplication digital-to-analog unit (MDAC1) is formed with the operational amplifier to complete the amplification of the redundant signal of the first stage pipeline stage, and simultaneously, C_f1、C_f2The sampling capacitor of the second multiplying digital-to-analog unit (MDAC2) and the sampling capacitor of the second inter-stage ADC (sub _ ADC2) are used for realizing the sampling operation of the second stage pipeline. Wherein the reference level V_dac1Controlled by the clock phase phi 2 and the digital output of the sub _ ADC1 according to the input signal V_inThe amplitudes are different and are respectively-V_ref、V_cm、V_ref。

The above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, but equivalent modifications or changes made by those skilled in the art according to the present disclosure should be included in the scope of the present invention as set forth in the appended claims.

Claims (3)

1. The multi-module shared pipeline stage circuit structure for the low-power consumption pipeline ADC is characterized by comprising a first multiplying digital-to-analog unit (MDAC1), a first inter-stage ADC (sub _ ADC1), a second multiplying digital-to-analog unit (MDAC2) and a second inter-stage ADC (sub _ ADC 2); the first multiplying digital-to-analog unit (MDAC1) and the second multiplying digital-to-analog unit (MDAC2) time-division multiplex a third capacitor (C)_f1) A fourth capacitor (C)_f2) And a first operational amplifier (OPA); the first inter-stage ADC (sub _ ADC1) and the second inter-stage ADC (sub _ ADC2) time-division multiplex a first Latch (Latch1) and a second Latch (L)atch2)；

The third capacitor (C) is arranged when the clock phase phi 1 is at a high level_f1) For reference level V_dac2Sampling, fourth capacitance (C)_f2) The feedback capacitor and the first operational amplifier (OPA) are used as a module unit of a second multiplying digital-to-analog unit (MDAC2) to realize the functions of subtraction, remainder and redundant amplification of the second multiplying digital-to-analog unit (MDAC 2); the third capacitor (C) is at high level when the clock phase phi 2 is at high level_f1) And a fourth capacitance (C)_f2) The feedback capacitor of the first multiplying digital-to-analog unit (MDAC1) and the first operational amplifier (OPA) realize the functions of subtraction, remainder and redundancy amplification of the first multiplying digital-to-analog unit (MDAC1), and meanwhile, the third capacitor (C)_f1) And a fourth capacitance (C)_f2) As the sampling capacitance of the second multiplying digital-to-analog unit (MDAC2), completing the sampling operation of the second multiplying digital-to-analog unit (MDAC 2); when the clock phase phi a is in a high level, the third capacitor (Cf1), the fourth capacitor (Cf2) and the first operational amplifier (OPA) carry out reset operation so as to eliminate the memory effect;

the first Latch (Latch1) and the second Latch (Latch2) are used as a first inter-stage ADC (sub _ ADC1) comparator when the clock phase phi 1 is at a high level, so that comparison between an input signal and a reference threshold value is realized; when the clock phase Φ 2 is at a high level, the comparator is used as a second inter-stage ADC (sub _ ADC2) to realize comparison between the input signal and the reference threshold; when the clock phase Φ a1 is at a high level, a reset operation is performed;

the clock phase Φ a has a high level before the rising edge of the clock phase Φ 2 arrives, and the clock phase Φ a1 has a high level before the rising edges of the clock phase Φ 1 and the clock phase Φ 2 arrive.

2. The multi-module shared pipeline stage circuit architecture for low-power pipelined ADC of claim 1, wherein the first multiplying digital-to-analog unit (MDAC1) comprises a first capacitor (C)_s1) A second capacitor (C)_s2) A third capacitor (C)_f1) A fourth capacitor (C)_f2) A first switch (S1), a second switch (S2), a fifth switch (S5), a sixteenth switch (S16), a seventeenth switch (S17), a twenty-second switch (S22), a twenty-third switch (S23),A twenty-fourth switch (S24), a twenty-fifth switch (S25), a first encoder circuit (Decoder1), a thirty-second switch (S32), a thirty-third switch (S33), and a first operational amplifier (OPA);

the second multiplying digital-to-analog unit (MDAC2) comprises a third capacitor (C)_f1) A fourth capacitor (C)_f2) An eighth switch (S8), a thirteenth switch (S13), a fourteenth switch (S14), a fifteenth switch (S15), a twenty-second switch (S22), a second encoding circuit (Decoder2), and a first operational amplifier (OPA);

wherein the first capacitor (C)_s1) Right polar plate and second capacitor (C)_s2) The right pole plate is connected with the upper end of the fifth switch (S5) and the left end point of the twenty-fifth switch (S25), and the left pole plate is connected with the right end point of the first switch (S1) and the right end point of the twenty-fourth switch (S24); left terminal of first switch (S1) and input signal V_inConnected to a second switch (S2); the left side of the twenty-fourth switch (S24) is connected to ground; a second capacitance (C)_s2) The left side is connected with the right side of the second switch (S2), the right side of the twentieth switch (S23), and the left side of the twentieth switch (S23) is connected with the reference level V_dac1(ii) a Third capacitance (C)_f1) And a fourth capacitance (C)_f2) The left side of the first operational amplifier is connected with the upper side of a sixteenth switch (S16) and the right side of a twenty-fifth switch (S25), and is connected with the negative input end of the first operational amplifier (OPA); the lower side of the sixteenth switch (S16) is connected with the ground level and is connected with the positive input end of the first operational amplifier (OPA); third capacitance (C)_f1) The right side is connected with the left side of a twenty-second switch (S22) and the left side of a fifteenth switch (S15), and a fourth capacitor (C)_f2) The right side of the second switch is connected with the right side of a twenty-second switch (S22), the upper side of a seventeenth switch (S17) and the left side of an eighth switch (S8), and is also connected with the output end of a first operational amplifier (OPA); the output end of the first coding circuit (Decoder1) controls the state of the twentieth switch (S23); the working state of the first coding circuit (Decoder1) is controlled by a thirty-third switch (S33) and a thirty-second switch (S32);

the right side of the eighth switch (S8) is connected to the third stage input, and the right side of the fifteenth switch (S15) is connected to the reference level V_dac2The control end of the fifteenth switch (S15) is connected with the output of the second coding circuit (Decoder2), and the second coding circuit (Decoder2) is composed of a thirteenth switch (S13) and a fourteenth switchOff (S14) control;

the first switch (S1), the second switch (S2), the eighth switch (S8), the thirteenth switch (S13), and the fourteenth switch (S14) are controlled by the clock phase Φ 1, the twenty-second switch (S22) is controlled by the inverted clock of the clock phase Φ 1, the twenty-fourth switch (S24), the twenty-fifth switch (S25), the thirty-third switch (S33), and the thirty-twelfth switch (S32) are controlled by the clock phase Φ 2, and the sixteenth switch (S16) and the seventeenth switch (S17) are controlled by the clock phase Φ_aControlling, the fifth switch (S5) is controlled by the clock phase phi 1E; wherein the falling edge of the clock phase Φ 1E is earlier than the falling edge of the clock phase Φ 1.

3. The multi-module shared pipeline stage circuit structure of claim 1, wherein the first inter-stage ADC (sub _ ADC1) comprises a third switch (S3), a fourth switch (S4), a sixth switch (S6), a seventh switch (S7), an eighteenth switch (S18), a nineteenth switch (S19), a twentieth switch (S20), a twenty-first switch (S21), a twenty-sixth switch (S26), a twenty-seventh switch (S27), a fifth capacitor (C19)_sc11) A sixth capacitor (C)_sc12) A first Latch (Latch1) and a second Latch (Latch 2);

the second inter-stage ADC (sub _ ADC2) comprises a ninth switch (S9), a tenth switch (S10), an eleventh switch (S11), a twelfth switch (S12), a twenty-eighth switch (S28), a twenty-ninth switch (S29), a thirty-third switch (S30), a thirty-third switch (S31), and a seventh capacitor (C)_sc21) An eighth capacitor (C)_sc22) A first Latch (Latch1) and a second Latch (Latch 2);

fifth capacitance (C)_sc11) The left side is connected with the right side of the third switch (S3) and the upper side of the eighteenth switch (S18), and the lower side of the eighteenth switch (S18) is connected with the threshold voltage V_th1(ii) a The left side of the third switch (S3) is connected with the left side of the fourth switch (S4), and is connected with an input signal; fifth capacitance (C)_sc11) Is connected with the upper side of a sixth switch (S6) and is connected with the input end of a preventive amplifier 1(pre1), the output end of the preventive amplifier 1(pre1) is connected with the left side of a twenty-sixth switch (S26), the right side of the twenty-sixth switch (S26) is connected with the input end of a first Latch (Latch1), and the first Latch (Latch1) is reset by a second Latch (Latch1)Ten-switch (S20) control; sixth capacitance (C)_sc12) The left side is connected with the right side of the fourth switch (S4) and the upper side of the nineteenth switch (S19), and the lower side of the nineteenth switch (S19) is connected with the threshold voltage V_th2(ii) a Sixth capacitance (C)_sc12) The right side of the second switch (S7) is connected with the upper side of a seventh switch (S7) and is connected with the input end of a preventive amplifier 2(pre2), the output end of the preventive amplifier 2(pre2) is connected with the left side of a twenty-seventh switch (S27), the right side of the twenty-seventh switch (S27) is connected with the input end of a second Latch (Latch2), and the reset of the second Latch (Latch2) is controlled by the twenty-first switch (S21);

the right side of the twenty-eighth switch (S28) is connected with the right side of the twenty-ninth switch (S29) and is connected with the output end of the first operational amplifier (OPA), the left side of the twenty-eighth switch (S28), the upper side of the tenth switch (S10) and the seventh capacitor (C)_sc21) Right side connected to a seventh capacitor (C)_sc21) The left side of the switch is connected with the upper side of a thirtieth switch (S30) and the right side of a twelfth switch (S12), and the left side of the twelfth switch (S12) is connected with the input end of a first Latch (Latch 1); the left side of the twenty-ninth switch (S29), the upper side of the ninth switch (S9) and the eighth capacitor (C)_sc22) Right side connected to an eighth capacitor (C)_sc22) The left side of the second Latch (Latch2) is connected with the upper side of a thirty-one switch (S31) and the right side of an eleventh switch (S11), and the left side of the eleventh switch (S11) is connected with the input end of a second Latch (Latch 2);

a third switch (S3), a fourth switch (S4), a ninth switch (S9), a tenth switch (S10), an eleventh switch (S11) and a twelfth switch (S12) are controlled by the clock phase Φ 1, a twenty-sixth switch (S26), a twenty-seventh switch (S27), a twenty-eighteen switch (S28) and a twenty-ninth switch (S29) are controlled by the clock phase Φ 2, an eighteenth switch (S18) and a nineteenth switch (S19) are controlled by the clock phase Φ a, a sixth switch (S6) and a seventh switch (S7) are controlled by the clock phase Φ 1E, a thirtieth switch (S30) and a thirty-eleventh switch (S31) are controlled by the clock phase Φ 2E, and a twentieth switch (S20) and a twenty-first switch (S21) are controlled by the clock phase Φ a 1; the falling edge of the clock phase phi 1E is earlier than that of the clock phase phi 1, and the falling edge of the clock phase phi 2E is earlier than that of the clock phase phi 2.

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