CN102420612B - Time-interleaving analogue-to-digital converter capable of suppressing sampling time mismatching - Google Patents

Abstract

A time-interleaving analog-to-digital converter capable of suppressing sampling time mismatch relates to the technical field of microelectronics. Aiming at the influence of the sampling time mismatch on the time-interleaving analog-digital converter, the invention proposes a structure of the time-interleaving analog-digital converter capable of suppressing the sampling time mismatch. The analog-to-digital converter includes: a channel sampling and holding circuit, a sub-analog-to-digital converter and a multiplexer. The system master clock is introduced into the channel sample-and-hold circuit to determine the sampling time, thereby avoiding the mismatch of sampling time caused by the separate sampling of each channel, and effectively improving the dynamic performance of the time-interleaved ADC. This method does not require a pre-sampling and holding circuit, so it has no impact on the bandwidth of the input signal, and the channel sampling and holding circuit can use the bottom plate sampling technology to eliminate the influence of charge injection and improve the linearity of the system.

Description

A time-interleaved analog-to-digital converter capable of suppressing sampling time mismatch

technical field

The invention relates to an analog-to-digital converter in microelectronic technology, in particular to a structure design of a time-interleaved analog-to-digital converter capable of suppressing sampling time mismatch.

Background technique

Analog-to-digital converter is a tool that converts analog signals into digital signals. As an interface between analog technology and digital technology, it is widely used in industrial control, radar, communication, consumer electronics and other fields, and plays an important role in information technology. effect. With the continuous improvement of the integrated circuit manufacturing process and the introduction of new materials, the digital signal processing technology has been continuously improved, thus putting forward higher requirements for the speed of the analog-to-digital converter.

One of the most popular ways to increase the speed of an A/D converter is to use multiple A/D converters in parallel. The interleaved clock is used to make multiple ADCs work in turn, and the overall speed can be improved while maintaining the low-speed operation of a single ADC. This structure is called Time-interleaved ADC (Time-interleaved ADC).

Figure 1 shows the basic structure of a four-channel time-interleaved analog-to-digital converter, each channel consists of a sample-and-hold circuit (S/H) and a sub-analog-to-digital converter (ADC), so the entire four-channel time-interleaved analog-to-digital conversion The converter consists of four sample-and-hold circuits (S/H ₁ , S/H ₂ , S/H ₃ and S/H ₄ ), four sub-ADCs (ADC ₁ , ADC ₂ , ADC ₃ and ADC ₄ ) and a Multiplexer (MUX). The sub-analog-to-digital converters of each channel have an accuracy of N bits, a working speed of f _s /4, and work in four different phases respectively, and the clock phase difference of adjacent channels is 90°. The four channels sample and convert the input signal in turn, and output digital signals with a rate of f _s /4 and an accuracy of N bits respectively, and finally output a digital signal with a rate of f _s and an accuracy of N bits through a multiplexer signal, so that the operating rate of the overall analog-to-digital converter is increased to 4 times the rate of a single analog-to-digital converter. Figure 2 is a timing diagram of the four-channel time-interleaved analog-to-digital converter.

Theoretically, the higher the number of channels, the faster the time-interleaved ADC will work. However, in fact, there are non-ideal factors such as sampling time mismatch (Timingmismatch), gain mismatch (Gain mismatch), offset mismatch (Offset mismatch) and bandwidth mismatch (Bandwidth mismatch) among the sub-ADCs of each channel. Seriously affects the dynamic performance of the entire analog-to-digital converter.

Aiming at the sampling time mismatch, related papers and patents have proposed a solution, that is, the sampling switch front-end technology. The method pre-positions the sampling switch and controls the sampling time by the master clock, thereby avoiding the sampling time mismatch caused by the separate sampling of each channel clock, and can significantly improve the dynamic performance of the entire analog-to-digital converter. However, this method has two disadvantages:

1. The introduction of the front switch will increase the on-resistance and parasitic capacitance of the signal path, reduce the input signal bandwidth, increase the relative error of the signal bandwidth, and further intensify the impact of bandwidth mismatch.

2. The sampling time is determined by the main clock of the pre-sampling switch, so that the sampling and holding circuit of each channel cannot adopt the lower plate sampling technology, which will lead to the unavoidable nonlinearity such as charge injection introduced by the sampling switch, and deteriorate the performance of the entire analog-to-digital converter. linearity.

Contents of the invention

The purpose of the present invention is to provide a time-interleaved analog-to-digital converter structure that can suppress sampling time mismatch without affecting the input signal bandwidth and system linearity, thereby effectively avoiding the influence of sampling time mismatch and improving the overall analog-to-digital conversion the dynamic performance of the device.

In order to achieve the above object, the time-interleaved analog-to-digital converter provided by the present invention is shown in Figure 3, which includes four identical sample-and-hold circuits (S/H ₁ , S/H ₂ , S/H ₃ and S/H ₄ ) , four identical sub-ADCs (ADC ₁ , ADC ₂ , ADC ₃ and ADC ₄ ) and a multiplexer (MUX). The difference with the prior art (Fig. 5) is that the sample and hold circuit (Fig. 6) of the present invention adds switch S4, consists of four switches (S1, S2, S3 and S4), a sampling capacitor (C _sample ) and an operational amplifier (AMP) composition. The switch S4 is controlled by the main clock MCLK, so the sampling time of each channel is determined by the falling edge of MCLK, thereby suppressing the sampling time mismatch caused by the separate sampling of each channel clock.

The specific connection relationship of the sample-and-hold circuit shown in Figure 6 is as follows: the left terminal of the switch S1 is connected to the input signal Vin, the right terminal is connected to the left plate of the sampling capacitor (C _sample ) and the left terminal of the switch S2; the right terminal of the switch S2 is connected to the right terminal of the switch S4 and the output Vout of the operational amplifier (AMP); the right plate of the sampling capacitor is connected to the left end of the switch S3 and the positive end of the operational amplifier (AMP), the negative end of the operational amplifier (AMP) is grounded, and the right end of the switch S3 is connected to the left end of the switch S4 . Switches S1 and S3 have the same clock control signal CLKi (i represents different channels, i=1, 2, 3, 4), and switch S2 is controlled by a clock CLKib that is non-overlapping with CLKi (i represents different channels, i =1,2,3,4) control, the switch S4 is controlled by the main clock MCLK.

Description of drawings:

Figure 1 is a schematic diagram of a traditional four-channel time-interleaved analog-to-digital converter

Figure 2 is a timing diagram of a traditional four-channel time-interleaved analog-to-digital converter

Fig. 3 is the structural diagram of the four-channel time-interleaved analog-to-digital converter designed by the present invention

Fig. 4 is the timing diagram of the four-channel time-interleaving analog-to-digital converter structure designed by the present invention

Figure 5 is a traditional sample and hold circuit (S/H) structure

Fig. 6 is the sample and hold circuit (S/H) structure that the present invention designs

Fig. 7 is the sequence diagram of the sample and hold circuit (S/H) that the present invention designs

Detailed ways

The present invention is further described below in conjunction with the figures.

As shown in FIG. 3 , the four-channel time-interleaving analog-to-digital converter proposed by the present invention is shown, and its timing diagram is shown in FIG. 4 . In Figure 4, the duty cycle of each channel clock is 25%. In each sampling clock phase, only one channel is always sampled, thus reducing the input signal load and increasing the input bandwidth. Compared with the traditional time-interleaved analog-to-digital converter (as shown in Figure 1), the sample-and-hold circuit of each channel in Figure 3 is composed of the channel clock CLKi (i represents a different channel, i=1, 2, 3, 4) and the main clock MCLK is controlled together, and the sampling time of each channel is determined by MCLK. The specific working method takes channel 1 as an example, and the working methods of other channels are the same.

The sample and hold circuit structure of channel one is shown in Figure 6, and its working sequence is shown in Figure 7. Among them, MCLK is the main clock, and the operating frequency is f _s ; CLK1 and CLK1b are two-phase non-overlapping clocks, and the operating frequency is f _s /4. The control signals of the switches S1 and S3 are CLK1, the control signal of the switch S2 is CLK1b, and the control signal of the switch S4 is the main clock MCLK.

Step 1, at time _t1 , MCLK and CLK1 jump to high level at the same time, CLK1b jumps to low level, so switches S1, S3 and S4 are turned on, S2 is turned off, and the sampling capacitor C _sample tracks the input signal;

Step 2. At time _t2 , MCLK jumps to a low level, switch S4 is turned off, and the charge on the right plate of the sampling capacitor C _sample does not change;

Step 3. At time _t3 , CLK1 jumps to low level, CLK1b jumps to high level, so switches S1 and S3 are disconnected, S2 is turned on, the sampling capacitor is reversed, channel 1 enters the hold phase, and the sub-analog-to-digital converter ADC ₁ converts the sampled value and outputs an N-bit digital signal DIG ₁ .

Step 4, at time _t3 , CLK1 jumps to a low level, and as shown in FIG. 4 , CLK2 jumps to a high level. Therefore, when channel one enters the hold phase, channel two tracks the input and starts the sample and hold process (repeat steps 1 to 3).

Step 5. Similarly, when CLK2 transitions to a low level, channel 2 completes sampling and enters the control and hold phase. The sub-analog-to-digital converter ADC ₂ converts the sampled value and outputs an N-bit digital signal DIG ₂ . At this point, as shown in Figure 4, CLK3 jumps to a high level, channel three tracks the input, and starts the sample-and-hold process (repeat steps 1 to 3).

Step 6. Similarly, when CLK3 transitions to a low level, channel 3 completes sampling and enters a hold phase, and the sub-analog-to-digital converter ADC ₃ converts the sampled value and outputs an N-bit digital signal DIG ₃ . At this point, as shown in Figure 4, CLK4 jumps to a high level, channel four tracks the input, and starts the sample-and-hold process (repeat steps 1 to 3).

Step 7. Similarly, when CLK4 transitions to a low level, channel 4 completes sampling and enters a hold phase, and the sub-analog-to-digital converter ADC ₄ converts the sampled value and outputs an N-bit digital signal DIG ₄ . At this time, as shown in Figure 4, CLK1 jumps to a high level again, the channel pair inputs are tracked, and the sample-and-hold process begins (repeat steps 1 to 3).

According to steps 1 to 7, it can be seen that the four channels sequentially sample and hold the input signal and convert the data according to the clock relationship shown in Figure 4, and continue to cycle. The cycle period is 4*T _s (T _s is the period of the master clock MCLK , T _s =1/f _s ). The multiplexer (MUX) outputs the digital signals of each channel (DIG ₁ ~ DIG ₄ ) sequentially according to the phase relationship of the clock shown in Figure 4, thus realizing high-speed conversion with an accuracy of N bits and a speed of f _s . The number of channels of the time-interleaved analog-to-digital converter of the present invention may be an integer greater than or equal to two.

The time-interleaved analog-to-digital converter of the present invention has the following four advantages:

1. At time _t2 , MCLK jumps to low level, switch S4 is turned off, and the charge on the right plate of the sampling capacitor no longer follows the input change, so the sampling value is determined at this time. Then switch S3 is turned off half a master clock cycle (T _s ) later than S4, and has no contribution to the sampling value, so the phase deviation of the channel clock CLK1 has no influence on the sampling result. Similarly, the phase deviations of the other three channel clocks have no effect on the sampling The result has no effect.

2. At time _t2 , MCLK jumps to a low level, switch S4 is turned off, the charge on the right plate of the sampling capacitor no longer follows the input change, and the sampling of the lower plate is realized, which avoids the charge injection of the sampling switch S1 and eliminates the The resulting non-linear effects.

3. Because the sampling switch S4 controlled by the main clock MCLK is not placed on the input signal path, the on-resistance and parasitic capacitance of the switch will not increase the load of the input signal, so it will not have any impact on the bandwidth of the input signal.

4. In this example, MCLK and CLK1 jump at the same time, but in fact, as long as the high level of MCLK is covered by the high level of CLK1, the above functions can be realized, thus alleviating the delay time requirement of the main clock.

The above example is only a preferred example of the present invention, and the use of the present invention is not limited to this example. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention should be included in the present invention. within the scope of protection.

Claims (4)

1. A time-interleaved analog-to-digital converter capable of suppressing sampling time mismatch, including a sample-and-hold circuit (S/H), a sub-analog-to-digital converter (ADC) and a multiplexer (MUX), its characteristics It is: the sample and hold circuit (S/H) is connected to the main clock (MCLK), and the sampling time is controlled by the main clock (MCLK); The sample and hold circuit (S/H) is composed of four switches (S1, S2, S3 and S4), a sampling capacitor (C _sample ) and an operational amplifier (AMP). The specific connection relationship is as follows: the left end of the switch S1 is connected to Input signal Vin, the right end is connected to the left plate of the sampling capacitor (C _sample ) and the left end of the switch S2, the right end of the switch S2 is connected to the right end of the switch S4 and the output Vout of the operational amplifier (AMP), and the right plate of the sampling capacitor is connected to the switch S3 The left terminal of the operational amplifier (AMP) and the positive terminal of the operational amplifier (AMP), the negative terminal of the operational amplifier (AMP) is grounded, the right terminal of the switch S3 is connected to the left terminal of the switch S4, and the switches S1 and S3 have the same clock control signal CLKi (i indicates different channels, i=1,2,3,4), the switch S2 is controlled by the two-phase non-overlapping clock CLKib with the clock CLKi (i represents a different channel, i=1,2,3,4), the switch S4 is controlled by the main clock MCLK Control, the sampling time of each channel is determined by the falling edge of the main clock MCLK. 2. The time-interleaved analog-to-digital converter according to claim 1, characterized in that: the time-interleaved analog-to-digital converter consists of four sample-and-hold circuits (S/H ₁ , S/H ₂ , S/H ₃ and S/H 2 ) /H ₄ ), four sub-ADCs (ADC ₁ , ADC ₂ , ADC ₃ and ADC ₄ ) and a multiplexer (MUX), sample and hold circuit (S/H ₁ , S/H ₂ , S/H ₃ and S/H ₄ ) are respectively connected to the master clock (MCLK). 3. according to claim 1, or the time-interleaved analog-to-digital converter capable of suppressing sampling time mismatch described in claim 2, it is characterized in that: the process of channel one sampling and holding circuit S/H ₁ sampling and holding is as follows: Step 1: When the clock CLK1 and the main clock MCLK jump to high level at the same time, and the clock CLK1b jumps to low level, the switches S1, S3 and S4 are turned on, S2 is turned off, and the sampling capacitor C _sample tracks the input signal. The sample and hold circuit follows the input signal; Step 2: When the main clock MCLK jumps to a low level, the switch S4 is turned off, the charge on the right plate of the sampling capacitor C _sample does not change, and the sampling ends; Step 3: When the clock CLK1 transitions to a low level, the clock CLK1b transitions to a high level, so the switches S1 and S3 are disconnected, S2 is turned on, the sampling capacitor is flipped, channel 1 enters the hold phase, and the sub-analog-to-digital converter ( ADC ₁ ) converts the sampling value and outputs N-bit digital signal, DIG ₁ ; In the same way: the sample-and-hold circuits (S/H ₂ , S/H ₃ and S/H ₄ ) of the other channels perform sample-hold and data conversion on the input signal in sequence according to the clock relationship, and repeat the channel-1 sample-hold circuit (S/H ₁ ) sample-and-hold process, step 1 to step 3 as described above, the sampling values are converted by the sub-analog-to-digital converters (ADC ₂ , ADC ₃ and ADC ₄ ), respectively, and N-bit digital signals (DIG ₂ , DIG ₃ , DIG ₄ ), enter the multiplexer (MUX), and the multiplexer (MUX) outputs the digital signals of each channel (DIG ₁ ~ DIG ₄ ) sequentially according to the phase relationship of the clock, thus realizing the precision of N bits , The speed is a high-speed conversion with an operating frequency of f _s . 4. The time-interleaved analog-to-digital converter capable of suppressing sampling time mismatch according to claim 1, wherein the total number of channels of the analog-to-digital converter can be an integer greater than or equal to two.

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