CN107204755B - High-precision self-adaptive relaxation oscillator - Google Patents

Abstract

A high-precision adaptive relaxation oscillator, which utilizes the principle of capacitor pre-charging to offset the delay generated by a charge-discharge control circuit arranged in an oscillation circuit, comprising an oscillation circuit, a first capacitor pre-charge circuit and a second capacitor pre-charge circuit, The capacitor pre-charge circuit is used to pre-charge the oscillator charging and discharging capacitor. The oscillator circuit charges and discharges on the basis of the pre-charge level of the capacitor pre-charge circuit. The error delay caused by the two charging of the capacitor is cancelled, so that the oscillator works in pre-charge. At the set frequency, the frequency-control current linearity is significantly improved, and the present invention does not directly reduce the delay by increasing the speed of the comparator or the RS flip-flop, but offsets the delay generated by the control circuit through two charging processes. As well as the influence of the imbalance with the change of the external environment, the accuracy of the oscillator is significantly improved, and it has strong temperature stability and power supply voltage suppression, that is, self-adaptability.

Description

A High Precision Adaptive Relaxation Oscillator

technical field

The invention relates to a relaxation oscillator, in particular to a high-precision self-adaptive relaxation oscillator, belonging to the technical field of CMOS integrated circuits.

Background technique

In large-scale integrated circuits, the clock signal is generally generated by an oscillator. The relaxation oscillator has the advantages of simple structure, low cost, easy integration and relatively low power consumption. It is the most widely used clock generation circuit in the oscillator.

In applications such as signal modulation and demodulation, data recovery of storage systems, etc., the control current-frequency of the relaxation oscillator used is required to have high linearity, thereby reducing distortion and increasing the relaxation oscillation. frequency range of the device. In relaxation oscillators, the control current-frequency linearity is related to the delay of the control circuit for the oscillation amplitude of the charge and discharge capacitors. Therefore, in order to improve the linearity of the oscillator, maximizing the frequency of the oscillator must minimize the delay effect of the control circuit. In the clock recovery circuit, in order to obtain a larger dynamic range, the relaxation oscillator circuit is required to have a small jitter. The jitter of the relaxation oscillator circuit is a small perturbation at the flip threshold level caused by the noise of the circuit itself. The relaxation oscillator circuit with small jitter requires to increase the oscillation amplitude of its charge and discharge capacitors.

In the prior art, relaxation oscillators have many different structures, and the common requirements for relaxation oscillators with different structures are high precision and good linearity of the frequency-control current at high frequencies. But the existing relaxation oscillators still have some shortcomings.

Figure 1 shows a current-controlled relaxation oscillator with a single timing capacitor, including a charging current source I _charge , a discharging current source I _discharge , a PMOS transistor M1, an NMOS transistor M2, a timing capacitor C, two comparators COMP1 and COMP2, and RS triggering device. The output end Q of the RS flip-flop is connected to the gate ends of the PMOS transistor M1 and the NMOS transistor M2. According to different signals at the output Q of the RS flip-flop, the PMOS transistor M1 and the NMOS transistor M2 are turned on and off alternately, and the charging current source I _charge and the discharging current source I _discharge charge and discharge the capacitor C alternately for a given timing.

The current-controlled relaxation oscillator for a single timing capacitor operates as follows:

S1) When the output terminal Q of the RS flip-flop is at a low level, the PMOS transistor M1 is turned on, the NMOS transistor M2 is turned off, the charging current source I _charge is given and the capacitor C is charged. When the voltage on the timing capacitor C rises above the upper reference level When V _H , the comparator COMP1 outputs a high level, the RS flip-flop is in the set state, and the output terminal Q outputs a high level;

S2) When the output terminal Q of the RS flip-flop outputs a high level, the PMOS transistor M1 is turned off, the NMOS transistor M2 is turned on, and the discharge current source I _discharge begins to discharge the capacitor C at a given timing, and the voltage on C drops. When the voltage drops below the lower reference level _VL , the comparator COMP2 outputs a high level, the RS flip-flop is in a reset state, and the output terminal Q outputs a low level;

The output terminal Q of the RS flip-flop is at a low level, returning to the initial state, and then repeating the above two processes in turn.

The voltage on the capacitor of the current controlled relaxation oscillator of the single timing capacitor oscillates back and forth between the upper reference level _VH and the lower reference level _VL . If the delay of the control circuit (COMP1, COMP2 and RS flip-flops in Figure 1) can be ignored, and let I _charge =I _discharge =I, then the period and frequency of the oscillator are

It can be seen from Equation 2 that if the delay of the control circuit can be ignored, once the capacitor C, the upper reference level V _H and the lower reference level _VL are selected, the frequency of the current-controlled relaxation oscillator of a single timing capacitor is proportional to the control current I.

However, the delay of the control circuit of the current-controlled relaxation oscillator of a single timing capacitor shown in FIG. 1 cannot be ignored, and the actual waveform of the voltage on the timing capacitor C is shown in FIG. 2 . Due to the delay of the control circuit, when the voltage on the timing capacitor C reaches the upper reference level V _H , the PMOS tube M1 is not turned off immediately, and the NMOS tube M2 is not turned on immediately, resulting in the overcharge of the voltage on the capacitor. Due to the overcharge of the voltage on the capacitor, the same time is required to release the overcharged charge when the capacitor voltage drops (set I _charge =I _discharge ), in this process, the delay of the control circuit is 2td, when the timing capacitor When C is discharged close to the lower reference level _VL , an over-discharge phenomenon will also occur. Therefore, the total delay in one cycle is T _d =4td, so the frequency formula (Equation 2) is modified as

Where f _ideal is the ideal frequency in equation 1, and T _d is the delay 4td in one cycle of the oscillator. The relationship between the actual frequency f in formula 3 and the control current can be represented by FIG. 3 .

Therefore, in order to improve linearity and maximize the frequency of the oscillator, the delay _Td within one cycle in the relaxation oscillator must be reduced.

At the same time, the current-controlled relaxation oscillator with a single timing capacitor also has many other disadvantages, such as the need for two reference levels; and because of the existence of two reference levels, the oscillation amplitude of the timing capacitor is limited, which leads to the circuit itself. The noise of the charge and discharge capacitors has an effect on the threshold level, and this effect accumulates in each cycle, ultimately affecting the output frequency of the oscillator; finally, due to device mismatch, its charge and discharge currents cannot be completely accurate. are equal, therefore, it is difficult to obtain a 50% duty cycle. Therefore, it is necessary to improve the current-controlled relaxation oscillator of a single timing capacitor in view of the above shortcomings.

Aiming at the shortcomings of the current-controlled relaxation oscillator with a single timing capacitor, Figure 4 shows a current-controlled relaxation oscillator with dual timing capacitors that can reduce the delay T _d in one cycle, including current sources I ₁ and I ₂ , PMOS tube M3, NMOS tube M4, PMOS tube M5, NMOS tube M6, timing capacitors C01 and C02, two comparators COMP3 and COMP4, RS flip-flop, the non-inverting terminals of comparator COMP3 and comparator COMP4 are respectively connected to timing capacitor C01 , the timing capacitor C02, the inverting terminals of the comparator COMP3 and the comparator COMP4 are connected together to the reference level VR _.

The operation of a current controlled relaxation oscillator with dual timing capacitors is as follows:

S1) When the circuit starts to work, the output terminal Q of the RS flip-flop is at a low level, the output terminal Q is at a high level, the PMOS tube M3 is turned on, the NMOS tube M4 is turned off, the current source I _{charge1 is} given when the capacitor C01 is charged, and the PMOS tube is charged. The tube M5 is turned off, the NMOS tube M6 is turned on, and the timing capacitor C02 is discharged to the ground GND. When the voltage on the timing capacitor C01 rises to exceed the reference level VR, the comparator COMP3 outputs a high level, and the _RS flip-flop is in the set state. , the output terminal Q becomes a high level, and the output terminal Q becomes a low level;

S2) The output terminal Q of the RS flip-flop is high level, the output terminal Q is low level, the PMOS tube M3 is turned off, the NMOS tube M4 is turned on, the timing capacitor C01 is discharged to the ground GND, the PMOS tube M5 is turned on, and the NMOS tube M6 is turned off The current source I _{charge2 charges} the timing capacitor C02. When the voltage on the timing capacitor C02 exceeds the reference level VR, the comparator COMP4 outputs a high level, the _RS flip-flop is in the reset state, and the output terminal Q becomes a low level. , the output Q is high level;

S3) The output terminal Q of the RS flip-flop is at a low level, and the output terminal Q is at a high level, returning to the initial state S1).

Compared to the single timing capacitor current controlled relaxation oscillator of Figure 1, the current controlled relaxation oscillator with dual timing capacitors shown in Figure 4 has a significantly improved effect:

1) The amplitude of the charge and discharge capacitor of the dual timing capacitor relaxation oscillator is larger than the amplitude of the charge and discharge capacitor of a single timing capacitor relaxation oscillator, and it can oscillate between close to GND and close to the power supply voltage, thereby reducing the circuit itself. The effect of noise on the inversion level of charging and discharging capacitors.

2) A dual-timing capacitor relaxation oscillator requires only one reference level, while a relaxation oscillator based on a single timing capacitor requires two reference levels.

3) The period of the relaxation oscillator of the dual timing capacitors is determined only by the charging process of the capacitors C01 and C02. The charging time of the timing capacitor C02 determines the time when the oscillator output Q is at a high level, and the charging time of the timing capacitor C01 determines the time when the oscillator output Q is at a low level. The cycle of the current controlled relaxation oscillator of the dual timing capacitor is determined only by the charging process of the capacitor, and its waveform is shown in Figure 5. Therefore, only the control circuit during the charging process of the capacitor (COMP3, COMP4 and RS flip-flop in Figure 4) ) and the delay of PMOS tube M3, NMOS tube M4, PMOS tube M5, and NMOS tube M6 as control switches can affect the cycle of the oscillator, while the delay of the capacitor discharge process does not affect the cycle of the oscillator, so the entire cycle The delay of the single-time capacitor structure is reduced from 4td to 2td, which improves the control linearity of the oscillator circuit and increases the maximum frequency range of the circuit.

Although the current controlled relaxation oscillator with dual timing capacitors reduces the delay from 4td to 2td in one cycle, the output frequency of the oscillator is still subject to the control circuit of the oscillation amplitude of the timing capacitor and the PMOS transistor M3 as a control switch , The influence of the delay of 2td of NMOS tube M4, PMOS tube M5 and NMOS tube M6, especially at high frequency, the delay of 2td is even greater than the period of the oscillator output waveform, which not only reduces the frequency-control current linearity, Moreover, the maximum frequency range of the oscillator is limited, so it is necessary to further improve the current-controlled relaxation oscillator with dual timing capacitors to reduce the effect of delay.

Aiming at the shortcomings of the current-controlled relaxation oscillator with dual timing capacitors, Figure 6 shows a high-linearity relaxation oscillator with reference level self-regulation, including oscillation circuit, reference level self-regulation circuit and transmission gate selection signal generation circuit. By detecting the voltage peak value of the charging and discharging capacitor in the oscillation circuit, the overcharge of the capacitor voltage caused by the delay of the control circuit is obtained, so that the reference level of the comparator in the oscillation circuit is reduced by the corresponding amount as a new reference level In order to make the oscillation amplitude of the charge and discharge capacitor just the theoretical value, when the new reference level is greater than zero, the relaxation oscillator eliminates the effect of the overcharge of the capacitor voltage on the output frequency caused by the delay of the charge and discharge capacitor due to the delay of the control circuit. Significantly improves the linearity of the frequency-control circuit of the relaxation oscillator, the transmission gate selection signal generation circuit provides a starting reference level for the comparator by controlling the transmission gate, and after a new reference level is generated, it is transmitted to the comparator The inverting terminal of the comparator is isolated, and the initial reference level is isolated from the inverting terminal of the comparator.

The working process of the reference level self-adjusting high linearity relaxation oscillator is as follows:

为高电平，此时第一传输门TG1开启，起始参考电平V_ref传送到振荡电路中的第一比较器COMP5和第二比较器COMP6的反相端，当电路开启之后，传输门选择信号产生电路中PMOS管M7、M8给电容C3充完电后，V_φ为高电平，

为低电平，此时第一传输门TG1截止，第二传输门TG2开启，信号2V_ref-V_peak通过第二传输门TG2传送到第一比较器COMP5和第二比较器COMP6的反相端作为新的参考电平；S1) Assume that the output terminal Q of the RS flip-flop at the beginning is low level, the output terminal Q is high level, the control switch S01 is turned on, the control switch S02 is turned off, the current I flows to the charging and discharging capacitor C1, the control switch S03 is turned off, and the control switch S02 is turned off. The control switch S04 is turned on, and the charge and discharge capacitor C2 is discharged to the ground. When the potential on the charge and discharge capacitor C1 rises to exceed the initial reference level _Vref of the first comparator COMP5, the first comparator COMP5 outputs a high level, and RS The flip-flop is in the set state, the output terminal Q outputs a high level, and the output terminal Q is a low level. At the same time, the waveform peak V _peak on the charging and discharging capacitor C1 is detected and maintained by the peak detection and hold circuit, and then passed through the subtractor. The circuit subtracts twice the starting reference level 2V _ref to obtain 2V _ref -V _peak , which is sent to the input of the second transmission gate TG2. When the circuit is just turned on, V _φ in the transmission gate selection signal generation circuit is low level,

It is a high level, at this time the first transmission gate TG1 is turned on, and the initial reference level _Vref is transmitted to the inverting terminals of the first comparator COMP5 and the second comparator COMP6 in the oscillator circuit. When the circuit is turned on, the transmission gate After the PMOS transistors M7 and M8 in the selection signal generation circuit are charged to the capacitor C3, V _φ is a high level,

At this time, the first transmission gate TG1 is turned off, the second transmission gate TG2 is turned on, and the signal 2V _ref -V _peak is transmitted to the inverting terminals of the first comparator COMP5 and the second comparator COMP6 through the second transmission gate TG2 as the new reference level;

S2) The output terminal Q of the RS flip-flop outputs a high level, the output terminal Q is a low level, the charging control switch S01 is turned off, the control switch S02 is turned on, the charging and discharging capacitor C1 is discharged to the ground, the control switch S03 is turned on, and the control switch S04 Turn off, the current I flows to the charge and discharge capacitor C2, when the potential on the charge and discharge capacitor C2 rises to exceed the reference level of the second comparator COMP6 (starting at V _ref , the transmission gate selection signal generation circuit charges the capacitor C3 When it is 2V _ref -V _peak ), the second comparator COMP6 outputs a high level, the RS flip-flop is in a reset state, the output terminal Q outputs a low level, and the output terminal Q is a high level;

S3) The output terminal Q of the RS flip-flop is at a low level, and the output terminal Q is at a high level, returning to the initial state S1), and then cycling in turn.

It can be seen from the above working process that the amplitude of the charge and discharge capacitors in the relaxation oscillator is theoretically V _ref . Due to the delay of the control circuit, the voltages on the charge and discharge capacitors C1 and C2 are overcharged, and the voltage is overcharged. It will prolong the period of the oscillator and reduce the frequency. Therefore, in order to eliminate the influence of overcharge, the reference level of the comparator is reduced by adding a reference level self-adjusting circuit, so that the voltage amplitude on the charging and discharging capacitor is just the theoretical value V _ref , so that the output frequency of the oscillator is just the theoretical design value, and the linearity of the frequency-control current is improved. In order to make the voltage amplitude on the charging and discharging capacitor just the theoretical value V _ref , we use the peak detection and holding circuit to detect the peak value V _peak on the charging and discharging capacitor C1 , and then obtain the overcharge V _peak of the voltage on the charging and discharging capacitor C1 -V _ref , in order to make the charging amplitude on the capacitor C1 just the theoretical value V _ref , we subtract the overcharge from the reference level of the comparator as a new reference level, namely V _ref -(V _peak -V _ref ) =2V _ref -V _peak , the subtraction process of obtaining the signal 2V _ref -V _peak is realized by a subtractor. Since the delay time of the control circuit is fixed, and after a charging control current I is selected, the overcharge voltage on the charging and discharging capacitor is fixed. Therefore, the reference level of the comparator is reduced by an overcharge amount as a new reference. It is feasible to make the voltage amplitude on the charging and discharging capacitor just the theoretical design value. Therefore, when the reference level 2V _ref -V _peak is greater than 0, the influence of the delay of the control circuit on the output frequency of the relaxation oscillator is eliminated, and the linearity of the frequency of the oscillator and the control current is significantly improved. degrees, maximizing the frequency of the relaxation oscillator. Before adding the reference level automatic adjustment circuit and after adding the reference level automatic adjustment circuit, the waveform change on the capacitor C1 is shown in Figure 7. The amplitude of the charge and discharge capacitor in the relaxation oscillator is theoretically V _ref , due to the control The delay of the circuit causes the voltage on the charging and discharging capacitors C1 and C2 to be overcharged, and the overcharge of the voltage will prolong the period of the oscillator and reduce the frequency, which eliminates the influence of the overcharge of the capacitor voltage.

Although the high linearity relaxation oscillator with reference level self-regulation reduces the propagation delay through the reference level self-regulation circuit, it should be noted here that the delay of the control circuit will vary with temperature, offset and supply voltage. The change of the external environment will cause the peak voltage V _peak on the charge and discharge capacitors C1 and C2 to change, and the effect of the high-precision relaxation oscillator of the above method will become worse, because the reference level self-adjustment here reduces the is a fixed value propagation delay under a certain condition.

Aiming at the shortcomings of the current-controlled relaxation oscillator with dual timing capacitors, Figure 8 shows a relaxation oscillator with high linearity of error delay detection, including an oscillation circuit, a delay error detection circuit and a modulation current generation circuit. The time error detection circuit is used to detect the peak voltage of the charging and discharging capacitor in the oscillation circuit, and generate a delay error elimination signal according to the peak voltage, so that the oscillator oscillates at a preset frequency, and the modulation current generating circuit is based on the peak value of the charging and discharging capacitor. voltage, generate a corresponding additional control current, improve the charging rate of the charging and discharging capacitor, eliminate the influence of the delay of the oscillation circuit, and improve the linearity of the control current-frequency.

The working process of the relaxation oscillator with high linearity for error delay detection is as follows:

As shown in Figure 8, in the initial state, the output terminal Q of the RS flip-flop is low level, the output terminal Q is high level, the control switch S1 is turned on, the control switch S2 is turned off, the control current flows to the charge and discharge capacitor C1, and the control switch S3 is turned off, the control switch S4 is turned on, and the charge and discharge capacitor C2 is discharged to the ground. In theory, when the potential on the charge and discharge capacitor C1 rises to exceed the reference level _Vref , the comparator COMP7 outputs a high level, and the RS flip-flop is in In the set state, the output terminal Q outputs a high level, the output terminal Q is a low level, the control switch S1 is turned off, the control switch S2 is turned on, the charge and discharge capacitor C1 is discharged to the ground, the control switch S3 is turned on, and the control switch S4 is turned off, The control current flows to the charge and discharge capacitor C2. When the potential of the charge and discharge capacitor C2 rises to exceed the reference level V _ref , the output terminal Q of the RS flip-flop is at a low level, and the output terminal Q is at a high level. However, in fact, due to the delay of the oscillation circuit, the voltage peaks of the charging and discharging capacitors C1 and C2 will be greater than V _ref , resulting in the nonlinearity of the control current-frequency. The present invention adopts the peak detection and hold in the delay error detection circuit The circuit detects the peak voltage on the charging and discharging capacitors C1 and C2, and uses this peak signal as the control signal of the modulation current generation circuit. The greater the circuit delay, the greater the peak voltage V _peak , which makes the output current of the modulation current generation circuit It also increases accordingly, and the charging rate of the charging and discharging capacitors C1 and C2 increases. When the modulation current reaches the preset value, the output frequency of the oscillator is the preset frequency, which eliminates the influence of circuit delay.

Although the high linearity relaxation oscillator with error delay detection reduces the propagation delay, because the above circuit needs to detect the peak voltage on the charging and discharging capacitors C1 and C2 first, and then use the detected peak voltage as the modulation current The control signal of the generation circuit increases the output current of the modulation current generation circuit, and the frequency of the oscillator gradually increases. It takes a long time to wait until the frequency of the oscillator reaches the preset value, that is, the oscillator has a long start-up time. In addition, the delay of the control circuit will change with the temperature, offset and power supply voltage. Changes in the external environment will cause the peak voltage V _peak0 on the charge and discharge capacitors C1 and C2 to change. If the oscillator frequency stabilizes Previously, the delay of the control circuit changed due to changes in temperature, offset and power supply voltage, and it was difficult for the frequency of the oscillator to reach a stable value within a certain period of time, which would cause the oscillator to function abnormally. There are significant limitations on the performance stability of the relaxation oscillators described above.

SUMMARY OF THE INVENTION

Aiming at the problem that the relaxation oscillator can maintain high accuracy when the external environment changes, the invention proposes a method that uses the principle of capacitor pre-charging to offset the delay generated by the charging and discharging control circuit, so as to achieve a high frequency-control current linearity. Accuracy-adaptive relaxation oscillator, the relaxation oscillator can still maintain high accuracy with changes in the external environment.

In order to achieve the above purpose of the invention, the present invention adopts the following technical scheme: a high-precision self-adaptive relaxation oscillator, characterized in that: based on the oscillation circuit, two additional capacitor precharge circuits are added, and the capacitor precharge principle is used to offset the The delay generated by the charge and discharge control circuit in the oscillator circuit; including the oscillator circuit, the first capacitor precharge circuit and the second capacitor precharge circuit, the capacitor precharge circuit is used to precharge the oscillator charge and discharge capacitor, and the oscillator circuit is used in the capacitor The precharge circuit charges and discharges on the basis of the precharge level, and the error delay caused by the two charges of the capacitor is cancelled, so that the oscillator works at the preset frequency, and the frequency-control current linearity is significantly improved; among them:

The oscillation circuit includes current sources I ₀ , I ₁ , control switches S30 and S40 , charge and discharge capacitors C10 and C20 , comparators CMP1 and CMP2 , RS flip-flop RS1 and reference level V _X +V _ref , wherein the comparators CMP1, The CMP2 and the RS flip-flop RS1 constitute a charge and discharge control circuit; the negative pole of the current source I ₀ and the negative pole of the current source I ₁ are both connected to the power supply VDD, and the positive pole of the current source I ₀ and the positive pole of the current source I ₁ are respectively connected to one end of the control switch S30 and one end of the control switch S40, the other end of the control switch S30 is connected to one end of the charge and discharge capacitor C10 and the non-inverting input end of the comparator CMP1, the other end of the charge and discharge capacitor C10 is grounded, and the other end of the control switch S40 is connected to the charge and discharge capacitor C20. One end and the non-inverting input of the comparator CMP2, the other end of the charge and discharge capacitor C20 is grounded, the inverting input of the comparator CMP1 and the inverting input of the comparator CMP2 are interconnected and connected to the reference level V _X +V _ref , compare The output end of the device CMP1 and the output end of the comparator CMP2 are respectively connected to the set input end S and the reset input end R of the RS flip-flop RS1;

二输入与门AND1的输出端连接振荡电路中控制开关S30的控制端，RS触发器RS2的输出端

连接控制开关S10的控制端；The first capacitor precharge circuit includes control switches S10, S50, two-input AND gate AND1, a pulse generation circuit and a charge and discharge control circuit, wherein the charge and discharge control circuit includes comparators CMP3, CMP4, RS flip-flop RS2 and reference level V _X , VM, the inverting input terminal of the comparator _CMP3 is connected to the reference level V _X , the non-inverting input terminal of the comparator _CMP4 is connected to the reference level VM, the non-inverting input terminal of the comparator CMP3 and the inverting input terminal of the comparator CMP4 It is interconnected and connected with one end of the control switch S50, one end of the control switch S10 and the other end of the control switch S30 in the oscillating circuit, the other end of the control switch S10 is connected to the positive pole of the current source _I0 in the oscillating circuit, and the The other end is grounded, the control end of the control switch S50 is connected to the output signal of the pulse generation circuit, the input end of the pulse generation circuit is connected to the output end Q1 of the RS flip-flop RS1 in the oscillation circuit, the output end of the comparator CMP3 and the output end of the comparator CMP4 The set input terminal S and reset input terminal R of the RS flip-flop RS2 are respectively connected, the output terminal Q2 of the RS flip-flop RS2 is connected to one input terminal of the two-input AND gate AND1, and the other input terminal of the two-input AND gate AND1 is connected to the oscillator circuit. The output of the RS flip-flop RS1

The output end of the two-input AND gate AND1 is connected to the control end of the control switch S30 in the oscillator circuit, and the output end of the RS flip-flop RS2

Connect the control terminal of the control switch S10;

比较器CMP5的输出端和比较器CMP6的输出端分别连接RS触发器RS3的置位输入端S和复位输入端R，RS触发器RS3的输出端Q3连接二输入与门AND2的一个输入端，二输入与门AND2的另一个输入端连接振荡电路中RS触发器RS1的输出端Q1，二输入与门AND2的输出端连接振荡电路中控制开关S40的控制端，RS触发器RS3的输出端

连接控制开关S20的控制端；The second capacitor precharge circuit has the same structure as the first capacitor precharge circuit, including control switches S20, S60, two-input AND gate AND2, a pulse generation circuit and a charge and discharge control circuit, wherein the charge and discharge control circuit includes comparators CMP5, CMP6 and RS flip-flop RS3 and reference levels V _X , VM , the inverting input terminal of the comparator _CMP5 is connected to the reference level V _X , the non-inverting input terminal of the comparator CMP6 is connected to the reference level VM , and the non-inverting input terminal of the comparator _CMP5 is connected to the reference level VM The input terminal is interconnected with the inverting input terminal of the comparator CMP6 and is connected to one end of the control switch S60, one end of the control switch S20 and the other end of the control switch S40 in the oscillation circuit, and the other end of the control switch S20 is connected to the oscillation circuit. The positive pole of the current source _I1 , the other end of the control switch S60 is grounded, the control end of the control switch S60 is connected to the output signal of the pulse generating circuit, and the input end of the pulse generating circuit is connected to the output end of the RS flip-flop RS1 in the oscillation circuit

The output end of the comparator CMP5 and the output end of the comparator CMP6 are respectively connected to the set input end S and the reset input end R of the RS flip-flop RS3, and the output end Q3 of the RS flip-flop RS3 is connected to an input end of the two-input AND gate AND2, The other input terminal of the two-input AND gate AND2 is connected to the output terminal Q1 of the RS flip-flop RS1 in the oscillator circuit, the output terminal of the two-input AND gate AND2 is connected to the control terminal of the control switch S40 in the oscillator circuit, and the output terminal of the RS flip-flop RS3

Connect the control terminal of the control switch S20;

The above circuit detects the voltage on the charge and discharge capacitors C10 and C20 by the charge and discharge control circuit in the two capacitor precharge circuits to control the control switches S10 and S20 to precharge the charge and discharge capacitors C10 and C20, and then control the switches S30 and S40 to The charging and discharging capacitors C10 and C20 are charged, and the narrow pulse output generated by the pulse generating circuit is used to discharge the charging and discharging capacitors C10 and C20. The error delays affected by the voltage factor are cancelled out to realize a relaxation oscillator with high precision and self-adaptation.

The structures of the charging and discharging capacitors C10 and C20 are exactly the same as the capacitance values; the structures of the comparators CMP1, CMP2, CMP3, CMP4, CMP5 and CMP6 are exactly the same; the structures of the RS flip-flops RS1, RS2 and RS3 are exactly the same; The structure of gate AND1 and gate AND2 is exactly the same; the set reference level threshold voltage should satisfy VM _{≤V X} +ΔV≤V _X +V _ref , where ΔV is the charge and discharge capacitors of the flip-flops RS1, RS2 and RS3. The voltage overshoot generated on C10 and C20.

In the process of generating oscillation, the pulse width of the pulse generating circuit is not less than the time for the charge and discharge capacitors C10 and C20 to discharge from the level V _X +V _ref to V _M , and is not greater than the time for the charge and discharge capacitors C10 and C20 to discharge from the level V _X +V The time for _ref to discharge to zero potential avoids that the pulse width is too wide and the control switch S50 and the control switch S60 are still open during the charging process of the charging and discharging capacitors C10 and C20, resulting in abnormal operation of the oscillator.

The pulse generating circuits in the first and second capacitor precharging circuits include PMOS transistors MP1-MP6, NMOS transistors MN1-MN6, capacitors C _P and resistors R _P , and the sources of the PMOS transistors MP1-MP6 are all connected to the power supply VCC, the sources of NMOS transistors MN1-MN3, the sources of NMOS transistors MN5 and MN6, and one end of capacitor C _P are all grounded. The gate of PMOS transistor MP1 is interconnected with the gate of NMOS transistor MN1 and serves as the input of the pulse generating circuit terminal, the drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1 and is connected to the gate of the PMOS transistor MP2 and the gate of the NMOS transistor MN2, and the drain of the PMOS transistor MP2 is interconnected with the drain of the NMOS transistor MN2. One end of the resistor R _P is connected, the other end of the resistor R _P is connected to the other end of the capacitor C _P , the gate of the PMOS transistor MP3 and the gate of the NMOS transistor MN3 are connected together, and the drain of the PMOS transistor MP3 is connected to the NMOS transistor MN3. The drain is interconnected and connected to the gate of the PMOS transistor MP4 and the gate of the NMOS transistor MN5, the drain of the PMOS transistor MP4 is connected to the drain of the PMOS transistor MP5, the drain of the NMOS transistor MN4 and the gate of the PMOS transistor MP6 It is connected with the gate of the NMOS transistor MN6, the gate of the PMOS transistor MP5 is interconnected with the gate of the NMOS transistor MN4 and is connected to the interconnection end of the gate of the PMOS transistor MP1 and the gate of the NMOS transistor MN1, and the gate of the NMOS transistor MN4 is connected. The source is connected to the drain of the NMOS transistor MN5, and the drain of the PMOS transistor MP6 is interconnected with the drain of the NMOS transistor MN6 and serves as an output terminal of the pulse generating circuit.

The circuit structure of the comparators CMP1-CMP6 includes PMOS transistors MP7-MP9 and NMOS transistors MN7-MN10. The sources of the PMOS transistors MP7-MP9 are connected to the power supply VCC, and the gate of the PMOS transistor MP7 and the gate of the PMOS transistor MP8 are mutually connected. Connect and connect the drain of the PMOS transistor MP7 and the drain of the NMOS transistor MN7. The source of the NMOS transistor MN7 is interconnected with the source of the NMOS transistor MN8 and connected to the drain of the NMOS transistor MN9. The gate of the NMOS transistor MN9 is connected to the NMOS transistor. The gate of MN10 is interconnected and connected to the bias voltage V _BIAS , the source of the NMOS transistor MN9 and the source of the NMOS transistor MN10 are both grounded, and the drain of the NMOS transistor MN10 is interconnected with the drain of the PMOS transistor MP9 and serves as a comparator. The output terminal, the gate of the NMOS transistor MN8 is the non-inverting input terminal of the comparator, and the gate of the NMOS transistor MN7 is the inverting input terminal of the comparator.

The circuit structure of the RS flip-flops RS1-RS3 includes PMOS transistors MP10-MP13 and NMOS transistors MN11-MN14, the source of the PMOS transistor MP10 and the source of the PMOS transistor MP12 are connected to the source VCC, and the drain of the PMOS transistor MP10 is connected to the PMOS The source of the tube MP11, the drain of the PMOS tube MP12 is connected to the source of the PMOS tube MP13, the sources of the NMOS tubes MN11-MN14 are all grounded, and the gate of the NMOS tube MN11 is interconnected with the gate of the PMOS tube MP10 and acts as an RS trigger The set input terminal S of the device, the gate of the NMOS transistor MN14 is interconnected with the gate of the PMOS transistor MP13 and serves as the reset input terminal R of the RS flip-flop, and the gate of the NMOS transistor MN12 is interconnected with the gate of the PMOS transistor MP11 and is It is connected with the drain of the NMOS transistor MN14, the drain of the NMOS transistor MN13 and the drain of the PMOS transistor MP13 as the output Q of the RS flip-flop, the drain of the NMOS transistor MN12 and the drain of the PMOS transistor MP11. The electrodes are interconnected and connected with the drain of the NMOS transistor MN11, the gate of the NMOS transistor MN13 and the gate of the PMOS transistor MP12 as the output terminal Q of the RS flip-flop.

Compared with the prior art, the advantages and beneficial effects of the present invention are:

(1) The high-precision adaptive relaxation oscillator of the present invention pre-charges the charging and discharging capacitors C10 and C20, and the delay of the control circuit caused by charging can be offset by two charging, so that the oscillator frequency has a very high frequency. Accuracy and Frequency - Controls current linearity.

(2) The high-precision adaptive relaxation oscillator of the present invention has self-adaptability under the change of the external environment of the circuit, because the delay of the control circuit will change with the change of temperature, offset and power supply voltage, the present invention is not directly By increasing the speed of the comparator or the RS flip-flop to reduce the delay, the delay generated by the control circuit and the influence of the offset with the change of the external environment are offset by the two charging processes, which significantly improves the accuracy of the oscillator, and It has strong temperature stability and power supply voltage suppression that is adaptive.

(3) The high-precision adaptive relaxation oscillator of the present invention has a very short start-up time, and can output a stable oscillator frequency signal after one oscillation period.

(4) The high-precision adaptive relaxation oscillator of the present invention has a large amplitude, which can be from a potential close to the ground to a power supply voltage, thereby reducing the influence of jitter on the oscillator cycle.

Description of drawings

1 is a current-controlled relaxation oscillator based on a single grounded timing capacitor in the prior art;

Fig. 2 is the voltage waveform on the charging and discharging capacitor C in Fig. 1;

FIG. 3 is a graph of the effect of propagation delay in the frequency-control current relationship in the relaxation oscillator of FIG. 1;

4 is a current-controlled relaxation oscillator with dual ground timing capacitors in the prior art;

的波形；Figure 5 shows the charging and discharging capacitors C1, C2 and the oscillator output Q and

waveform;

Fig. 6 is the relaxation oscillator with reference level automatic adjustment in the prior art;

Fig. 7 is the waveform of charging and discharging capacitor C1 and oscillator output Q in Fig. 6;

8 is a relaxation oscillator with an error delay detection circuit in the prior art;

Fig. 9 is the waveform of charging and discharging capacitor C1 and oscillator output Q in Fig. 6;

Fig. 10 is the basic structure block diagram of the high-precision adaptive relaxation oscillator of the present invention;

Fig. 11 is the waveform change on the charging and discharging capacitor C10 after the high-precision adaptive relaxation oscillator of the present invention is powered on;

Fig. 12 is the working flow chart of the high-precision adaptive relaxation oscillator of the present invention;

13 is the waveform of the high-precision adaptive relaxation oscillator control switches S10, S20, S30, S40, charge and discharge capacitors C10, C20 and the oscillator output Q of the present invention;

14 is a circuit diagram of an implementation of the high-precision adaptive relaxation oscillator of the present invention;

Fig. 15 is the implementation circuit diagram of the pulse generation circuit adopted by the high-precision adaptive relaxation oscillator of the present invention;

Fig. 16 is the implementation circuit of the comparator adopted by the high-precision adaptive relaxation oscillator of the present invention;

FIG. 17 is the implementation circuit of the RS flip-flop adopted by the high-precision adaptive relaxation oscillator of the present invention.

Detailed ways

The principles and features of the present invention will be described below with reference to the accompanying drawings, and the examples are only used to explain the present invention, but not to limit the scope of the present invention.

Referring to FIG. 10 and FIG. 14 , the present invention adds a first capacitor precharge circuit 2 and a second capacitor precharge circuit 3 that can precharge the charge and discharge capacitors on the basis of the oscillator circuit 1 . The oscillator circuit 1 , the first capacitor precharge circuit 2 and the second capacitor precharge circuit 3 all include charge and discharge control circuits with the same structure.

The oscillator circuit 1 includes current sources I ₀ and I ₁ , control switches S30 and S40 , charge and discharge capacitors C10 and C20 , comparators CMP1 and CMP2 , RS flip-flop RS1 and reference level V _X +V _ref , wherein the comparators CMP1, CMP2 and RS flip-flop RS1 constitute a charge and discharge control circuit. The negative electrode of the current source I ₀ is connected to the power supply VDD, the positive electrode is connected to the control switches S10 and S30, the other end of the control switch S30 is connected to one end of the charge and discharge capacitor C10 and the non-inverting input end of the comparator CMP1, the other end of the charge and discharge capacitor C10 is grounded, and the current The negative pole of the source I ₁ is connected to the power supply VDD, the positive pole is connected to the control switches S20 and S40, the other end of the control switch S40 is connected to one end of the charge and discharge capacitor C20 and the non-inverting input end of the comparator CMP2, the other end of the charge and discharge capacitor C20 is grounded, the comparator The inverting input terminals of CMP1 and CMP2 are interconnected and connected to the reference level V _X +V _ref , the output terminal of CMP1 is connected to the set input terminal S of the RS flip-flop RS1, and the output terminal of CMP2 is connected to the reset input terminal of the RS flip-flop RS1. R.

高电平可直接使控制开关S10闭合，输出Q2和RS触发器RS1的

分别接到二输入与门AND1的两个输入端，二输入与门AND1的输出端高电平可直接使控制开关S30闭合。The first capacitor precharging circuit 2 includes control switches S10, S50, a pulse generating circuit, a two-input AND gate AND1, a charging and discharging control circuit composed of comparators CMP3, _CMP4 , RS flip-flop RS2 and reference levels V _X , VM. One end of the control switch S10 is connected to the positive pole of the current source _I0 , the other end of the control switch S10 is connected to one end of the charge and discharge capacitor C10, one end of the control switch S50, the non-inverting input end of the comparator CMP3 and the inverting input end of the comparator CMP4, The other end of the control switch S50 is grounded, the inverting input end of the comparator CMP3 is connected to the reference level V _X , the non-inverting input end of the comparator _CMP4 is connected to the reference level VM , and the output end of the comparator CMP3 is connected to the setting of the RS flip-flop RS2. Bit input S, the output of the comparator CMP4 is connected to the reset input R of the RS flip-flop RS2, and the output of the RS flip-flop RS2

The high level can directly close the control switch S10, output Q2 and RS flip-flop RS1

They are respectively connected to the two input terminals of the two-input AND gate AND1, and the high level of the output terminal of the two-input AND gate AND1 can directly close the control switch S30.

高电平可直接使控制开关S20闭合，输出Q3和RS触发器RS1的Q1分别接到二输入与门AND2的两个输入端，二输入与门AND2的输出端高电平可直接使控制开关S40闭合。The second capacitor precharge circuit 3 has the same structure as the first capacitor precharge circuit 2, including control switches S20, S60, a pulse generating circuit, a two-input AND gate AND2, comparators CMP5, CMP6, RS flip-flops RS3, and a reference level V The capacitor _precharge control circuit composed of _X and VM. One end of the control switch S20 is connected to the positive pole of the current source _I1 , the other end of the control switch S20 is connected to one end of the charge and discharge capacitor C20, one end of the control switch S60, the non-inverting input end of the comparator CMP5 and the inverting input end of the comparator CMP6, The other end of the control switch S60 is grounded, the inverting input terminal of the comparator CMP5 is connected to the reference level V _X , the non-inverting input terminal of the comparator CMP6 is connected to the reference level V _M , and the output terminal of the comparator CMP5 is connected to the setting of the RS flip-flop RS3. Bit input S, the output of the comparator CMP6 is connected to the reset input R of the RS flip-flop RS3, and the output of the RS flip-flop RS3

The high level can directly close the control switch S20, the output Q3 and the Q1 of the RS flip-flop RS1 are respectively connected to the two input terminals of the two-input AND gate AND2, and the high level of the output terminal of the two-input AND gate AND2 can directly make the control switch S40 is closed.

The structure and capacitance value of the above-mentioned charge and discharge capacitor C10 and charge and discharge capacitor C20 are exactly the same, the structure and current value of the current source I ₀ and the current source I ₁ are exactly the same, the circuit structure of the comparators CMP1, CMP2, CMP3, CMP4, CMP5 and CMP6 The same, the RS flip-flops RS1, RS2 and RS3 are exactly the same, the two input AND gates AND1, AND2 have the same circuit structure, and the pulse generating circuits in the two capacitor precharge circuits are the same.

As shown in Figure 10, in the initial state, the output terminal Q1 of the RS flip-flop RS1 is at a low level, the capacitor precharge control circuit controls the control switch S10 to turn on, S50 turns off, and the current source I ₀ charges the charge and discharge capacitor C10, while the capacitor The precharge control circuit controls the control switch S20 to be turned on, and the control switch S60 to be turned off, and the current source _I1 charges the charge and discharge capacitor C20. When the potential on the charge and discharge capacitor C10 rises to exceed the reference level V _X , the control switch S10 is turned off, and the control The switch S30 is turned on, the current source I ₀ continues to charge the charge and discharge capacitor C10, while the control switch S20 is turned off, the control switch S60 is turned off, the current source I ₁ stops charging the charge and discharge capacitor C20, and the voltage across the charge and discharge capacitor remains unchanged. , when the potential on the charge and discharge capacitor C10 rises to exceed the reference level V _X +V _ref , the control switch S10 and the control switch S30 are turned off, the control switch S50 is turned on under a pulse generated by the pulse generating circuit, and the charge and discharge capacitor C10 Discharge begins, and at the same time, the control switch S40 is turned on, the control switch S60 is turned off, and the current source I ₁ continues to charge the charge and discharge capacitor C20. In the process of the potential on the charge and discharge capacitor C20 rising to exceed the reference level V _X +V _ref , When the potential on the charge and discharge capacitor C10 drops below the reference level _VM , the control switch S10 is turned on, the control switch S50 is turned off after the pulse width, and the current source I ₀ charges the charge and discharge capacitor C10. When the potential of the charging and discharging capacitor C10 rises to exceed the reference level V _X , the control switch S10 is turned off, and the potential on the charging and discharging capacitor C10 remains unchanged. When the potential on the charging and discharging capacitor C20 rises to exceed the reference level V _X +V _ref , The control switch S30 is turned on, the current source I ₀ charges the charging and discharging capacitor C10, and at the same time, the control switch S60 is turned on under a pulse generated by the pulse generating circuit, and the charging and discharging capacitor C20 begins to discharge. Figure 12.

In the present invention, after adding the charging and discharging capacitor pre-charging circuit, the waveform change on the charging and discharging capacitor C10 is shown in FIG. 11 . In the process of generating oscillation, the pulse width of the pulse generating circuit should be designed to satisfy: the pulse width is not less than the time for the charging and discharging capacitors C10 and C20 to discharge from the level V _X +V _ref to V _M , and is not greater than the charging and discharging capacitors C10 and C20 from The time when the level V _X +V _ref is discharged to zero potential prevents the control switch S50 and the control switch S60 from being turned on during the charging process of the charging and discharging capacitors C10 and C20 due to the excessively wide pulse width, resulting in abnormal operation of the oscillator.

The discharge time marked in Figure 13 is the pulse width of the pulse generating circuit. The cycle of the relaxation oscillator is twice the charging time of the charging and discharging capacitors C10 and C20 from pre-charging to exceeding the reference level V _X when the potential starts to charge to exceeding the reference level V _X +V _ref , and the charging and discharging capacitors C10 and C20 are charged. After reaching the reference level V _X or V _X +V _ref , the overcharge caused by the delay of the control circuit is offset in the same environment, and the offset effect of the circuit is also offset, thus ensuring the relaxation oscillator has high precision and accuracy. Frequency - Controls current linearity.

As shown in Figure 11(a), when the reference level is V _ref , before adding the capacitor precharge circuit, when the oscillator starts to power on, due to the influence of the circuit delay td (td and temperature T, offset OS and power supply voltage) It is related to VDD, etc., which can be expressed as td(T, OS, VDD)), the voltage of capacitor C10 is overcharged during the rising process and rises to the initial peak voltage V _peak0 , the output of the oscillator (RS flip-flop output Q signal) frequency is greater than the preset value; after adding the capacitor pre-charging circuit, the two charging processes of the charging and discharging capacitor will cause overcharge due to the circuit delay, because the structure and capacitance value of the charging and discharging capacitors C10 and C20 are exactly the same, the current source The structures and current values of I ₀ and I ₁ are exactly the same, then in any environment where the oscillator is located, the effects of overcharge and offset due to circuit delay can be canceled out. The relaxation oscillator has high precision and frequency- Controls current linearity and adaptability not affected by external environment and offsets.

The working process of Figure 14 is as follows:

1) Assume that the initial states of the RS flip-flop output terminals Q1, Q2 and Q3 are all low levels, the capacitors C10 and C20 are equal in size and both are C and the initial voltage is 0, and the current sources I ₀ and I ₁ are both I _REF , the threshold voltage of the comparator V _X +V _ref >V _X >V _M ;

2) At the beginning, switches S10 and S20 are closed, S30, S40, S50 and S60 are open, and the current source I ₀ and the current source I ₁ charge the capacitors C10 and C20 respectively. When the capacitors C10 and C20 are charged to V _X , Q2 and The output level of Q3 jumps to output a high level, and the charging time

In the formula, C is the same capacitance value of capacitors C10 and C20, I _REF is the value of charging current I ₀ and I ₁ , td(T, OS, VDD) is related to temperature T, offset OS and power supply voltage VDD, etc. circuit delay.

3) After Q2 and Q3 output a high level, switches S10, S20, S40, S50 and S60 are disconnected, S30 is closed, the voltage across capacitor C20 remains unchanged at V _X , and the current source I ₀ continues to charge capacitor C10. When charging to V _X +V _ref , the Q1 level jumps to output a high level, and the charging time

In the formula, C is the same capacitance value of capacitors C10 and C20, I _REF is the value of charging current I ₀ and I ₁ , td(T, OS, VDD) is related to temperature T, offset OS and power supply voltage VDD, etc. circuit delay.

4) After Q1 outputs a high level, the switches S10, S20, S30 and S60 are disconnected, S40 and S50 are closed, the current source _I1 charges the capacitor C20, and the capacitor C10 discharges. When the capacitor C10 discharges to V _M , Q2 outputs the level A transition occurs and outputs a low level;

5) After Q2 outputs a low level, the switch S10 is closed, S50 is disconnected, the current source I ₀ charges the capacitor C10, and after the capacitor C10 is charged to V _X , the output level of Q2 jumps and outputs a high level;

6) After Q2 outputs a high level, the switch S10 is turned off. At this time, the voltage on the capacitor C10 keeps V _X unchanged. When the capacitor C20 is charged to V _X +V _ref , the output level of Q1 jumps and outputs a low level. , the charging time

In the formula, C is the same capacitance value of capacitors C10 and C20, I _REF is the value of charging current I ₀ and I ₁ , td(T, OS, VDD) is related to temperature T, offset OS and power supply voltage VDD, etc. circuit delay.

7) After the output level of Q1 becomes low, S40 is disconnected, S30 is closed, the current source I ₀ charges the capacitor C10, and the capacitor C20 discharges. When the capacitor C20 discharges to V _M , the output level of Q3 jumps and the output is high. level;

8) After Q3 outputs a high level, the switch S60 is disconnected after the pulse ends, S20 is closed, and the current source I ₁ charges the capacitor C20. After the capacitor C20 is charged to V _X , the output level of Q3 jumps and outputs a low level;

9) After Q3 outputs a low level, the switch S20 is turned off. At this time, the voltage on the capacitor C20 keeps V _X unchanged. When the capacitor C10 is charged to V _X +V _ref , the output level of Q1 jumps and outputs a high level. , the charging time

In the formula, C is the same capacitance value of capacitors C10 and C20, I _REF is the value of charging current I ₀ and I ₁ , td(T, OS, VDD) is related to temperature T, offset OS and power supply voltage VDD, etc. circuit delay.

10) Repeat the above steps 4 to 9 to form oscillation.

Assuming that the voltage overshoot on the capacitor due to the delay of the RS trigger of the control circuit is ΔV, then if the circuit works normally, the set reference level (threshold voltage) should satisfy the following relationship

V _M ≤V _X +ΔV≤V _X +V _ref formula 8

According to the working principle of the circuit, referring to Fig. 13 for the working process of the circuit, it can be seen that the period of the capacitor pre-charging circuit depends on the time when the capacitors C10 and C20 are charged from the voltage V _X +ΔV to the voltage V _X +V _ref +ΔV, and the period is

Among them, C is the same capacitance value of capacitors C10 and C20, and I _REF is the value of charging currents I ₀ and I ₁ .

The frequency of the oscillator is

Among them, C is the same capacitance value of capacitors C10 and C20, and I _REF is the value of charging currents I ₀ and I ₁ .

FIG. 15 is an implementation circuit of the pulse generating circuit used in the high-precision adaptive relaxation oscillator of the present invention. In this embodiment, the output of RS1 is used to pass through the pulse generating circuit, and a narrow pulse signal is generated at the rising edge of the input signal to control the closing of switches S50 and S60, so that the potential on the charging and discharging capacitors C10 and C20 can be discharged to _VM , where the The pulse width can be determined by calculating the discharge voltage and capacitance value on the charging and discharging capacitor. The pulse width is shown in the waveform diagram as shown in Figure 13.

FIG. 16 is an implementation circuit of the comparator used in the high-precision adaptive relaxation oscillator of the present invention. MP7, MP8, MN7, MN8 and MN9 form a five-tube differential input stage, MP9 and MN10 form a two-stage open-loop op amp of the second gain stage as a comparator, so that the comparator compares the two input voltages and outputs a high level or low level.

FIG. 17 is an implementation circuit of the RS flip-flop adopted by the high-precision adaptive relaxation oscillator of the present invention. In the embodiment, the RS flip-flop is based on two NAND gates.

In the embodiment shown, other modifications and combinations are possible, and the invention is not limited to the few examples shown. Although the invention has been described above using specific embodiments, various modifications may be made by those skilled in the art within the scope of the claims. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (6)

1. A high-precision adaptive relaxation oscillator, characterized by: based on the oscillation circuit, two capacitor pre-charging circuits are additionally arranged, and the delay generated by a charge and discharge control circuit arranged in the oscillation circuit is offset by utilizing the capacitor pre-charging principle; the oscillator comprises an oscillating circuit, a first capacitor pre-charging circuit and a second capacitor pre-charging circuit, wherein the capacitor pre-charging circuit is used for pre-charging a charging and discharging capacitor of the oscillator, the oscillating circuit performs charging and discharging on the basis of the pre-charging level of the capacitor pre-charging circuit, and the error generated by twice charging of the capacitor is delayed and offset, so that the oscillator works at a preset frequency, and the frequency-control current linearity is remarkably improved; wherein:

the oscillating circuit comprises a current source I₀、I₁Control switches S30 and S40, charging and discharging capacitors C10 and C20, comparators CMP1 and CMP2, RS trigger RS1 and reference level V_X+V_refThe comparators CMP1, CMP2 and RS1 form a charge-discharge control circuit; current source I₀Negative pole and current source I₁The negative electrodes of the two-phase current source are connected with a power supply VDD and a current source I₀Positive pole of (1) and current source I₁Respectively connected with one end of a control switch S30 and one end of a control switch S40, the other end of the control switch S30 is connected with one end of a charging and discharging capacitor C10 and the non-inverting input end of a comparator CMP1, the other end of the charging and discharging capacitor C10 is grounded, the other end of the control switch S40 is connected with one end of a charging and discharging capacitor C20 and the non-inverting input end of the comparator CMP2, the other end of the charging and discharging capacitor C20 is grounded, the inverting input end of the comparator CMP1 and the inverting input end of the comparator CMP2 are interconnected and connected with a reference level V_X+V_refThe output end of the comparator CMP1 and the output end of the comparator CMP2 are respectively connected with the set input end S and the reset input end R of the RS trigger RS 1;

the first capacitor pre-charging circuit comprises control switches S10 AND S50, a two-input AND gate AND1, a pulse generation circuit AND a charge AND discharge control circuit, wherein the charge AND discharge control circuit comprises comparators CMP3 AND CMP4, an RS trigger RS2 AND a reference level V_X、V_MThe inverting input terminal of the comparator CMP3 is connected to the reference level V_XThe non-inverting input terminal of the comparator CMP4 is connected to the reference level V_MA non-inverting input terminal of the comparator CMP3 is connected to an inverting input terminal of the comparator CMP4, and is connected to one terminal of the control switch S50, one terminal of the control switch S10, and the other terminal of the control switch S30 in the oscillation circuit, and the other terminal of the control switch S10 is connected to the current source I in the oscillation circuit₀The other end of the control switch S50 is grounded, the control end of the control switch S50 is connected with the output signal of the pulse generating circuit, the input end of the pulse generating circuit is connected with the output end Q1 of an RS trigger RS1 in the oscillating circuit, the output end of the comparator CMP3 AND the output end of the comparator CMP4 are respectively connected with the set input end S AND the reset input end R of the RS trigger RS2, the output end Q2 of the RS trigger RS2 is connected with one input end of a two-input AND gate 1, AND the other input end of the two-input AND gate AND1 is connected with the output end of an RS trigger RS1 in the oscillating circuit

The output end of the two-input AND gate AND1 is connected with the control of a control switch S30 in the oscillating circuitTerminal, output terminal of RS2 flip-flop

The control end of the control switch S10 is connected;

the second capacitor pre-charging circuit has the same structure as the first capacitor pre-charging circuit, AND comprises control switches S20 AND S60, a two-input AND gate AND2, a pulse generation circuit AND a charge AND discharge control circuit, wherein the charge AND discharge control circuit comprises comparators CMP5 AND CMP6, an RS trigger RS3 AND a reference level V_X、V_MThe inverting input terminal of the comparator CMP5 is connected to the reference level V_XThe non-inverting input terminal of the comparator CMP6 is connected to the reference level V_MA non-inverting input terminal of the comparator CMP5 is connected to an inverting input terminal of the comparator CMP6, and is connected to one terminal of the control switch S60, one terminal of the control switch S20, and the other terminal of the control switch S40 in the oscillation circuit, and the other terminal of the control switch S20 is connected to the current source I in the oscillation circuit₁The other end of the control switch S60 is grounded, the control end of the control switch S60 is connected with the output signal of the pulse generating circuit, and the input end of the pulse generating circuit is connected with the output end of the RS trigger RS1 in the oscillating circuit

The output end of the comparator CMP5 AND the output end of the comparator CMP6 are respectively connected with a set input end S AND a reset input end R of an RS flip-flop RS3, the output end Q3 of the RS flip-flop RS3 is connected with one input end of a two-input AND gate AND2, the other input end of the two-input AND gate AND2 is connected with the output end Q1 of the RS flip-flop RS1 in the oscillating circuit, the output end of the two-input AND gate AND2 is connected with the control end of a control switch S40 in the oscillating circuit, AND the output end of the RS flip-flop RS3

The control end of the control switch S20 is connected;

in the oscillation circuit, the first capacitor pre-charging circuit and the second capacitor pre-charging circuit, the charge and discharge control circuit in the first capacitor pre-charging circuit and the second capacitor pre-charging circuit detects the voltage on the charge and discharge capacitors C10 and C20 to control the control switches S10 and S20 to pre-charge the charge and discharge capacitors C10 and C20, and then controls the switches S30 and S40 to charge the charge and discharge capacitors C10 and C20, and the narrow pulse output generated by the pulse generating circuit discharges the charge and discharge capacitors C10 and C20, so that the high-precision self-adaptive relaxation oscillator is realized by offsetting the error delay caused by temperature, imbalance and power supply voltage factors in the two charging processes of the charge and discharge capacitors C10 and C20.

2. A high accuracy adaptive relaxation oscillator as claimed in claim 1, characterized in that: the structures and capacitance values of the charge and discharge capacitors C10 and C20 are completely the same; the structures of the comparators CMP1, CMP2, CMP3, CMP4, CMP5, and CMP6 are identical; the RS triggers RS1, RS2 and RS3 are completely the same in structure; the two-input AND gate AND1 AND the two-input AND gate AND2 have the same structure; the threshold voltage of the reference level is set to satisfy V_M≤V_X+ΔV≤V_X+V_refAnd Δ V is the voltage overshoot generated by the flip-flops RS1, RS2 and RS3 on the charging and discharging capacitors C10 and C20.

3. A high precision adaptive relaxation oscillator as claimed in claim 1 or 2, characterized in that: in the process of generating oscillation, the pulse width of the pulse generating circuit is not less than the pulse width of the charging and discharging capacitors C10 and C20 from the level V_X+V_refDischarge to V_MIs not more than the time from the level V of the charging and discharging capacitors C10 and C20_X+V_refThe time of discharging to the zero potential avoids the control switch S50 and the control switch S60 from being still opened in the process of charging the charging and discharging capacitors C10 and C20 due to the excessively wide pulse width, so that the oscillator works abnormally.

4. A high accuracy adaptive relaxation oscillator as claimed in claim 3, characterized in that: the pulse generating circuit in the first and second capacitor pre-charging circuits comprises PMOS tubes MP 1-MP 6, NMOS tubes MN 1-MN 6, and a capacitor C_PAnd a resistance R_PThe sources of the PMOS tubes MP 1-MP 6 are all connected with a power supply VCC,the source electrodes of the NMOS transistors MN 1-MN 3, the source electrodes of the NMOS transistors MN5 and MN6 and the capacitor C_POne end of the PMOS transistor MP1 is grounded, the grid of the PMOS transistor MP1 is connected with the grid of the NMOS transistor MN1 and is used as the input end of the pulse generation circuit, the drain of the PMOS transistor MP1 is connected with the drain of the NMOS transistor MN1, the grid of the PMOS transistor MP2 and the grid of the NMOS transistor MN2, the drain of the PMOS transistor MP2 is connected with the drain of the NMOS transistor MN2 and is connected with a resistor R_POne terminal of (1), resistance R_PIs connected with the capacitor C at the other end_PThe other end of the PMOS tube MP3 and the grid of the PMOS tube MP3 are connected with the grid of the NMOS tube MN3, the drain of the PMOS tube MP3 is connected with the drain of the NMOS tube MN3 and is connected with the grid of the PMOS tube MP4 and the grid of the NMOS tube MN5, the drain of the PMOS tube MP4 is connected with the drain of the PMOS tube MP5, the drain of the NMOS tube MN4 and the grid of the PMOS tube MP6 are connected with the grid of the NMOS tube MN6, the grid of the PMOS tube MP5 is connected with the grid of the NMOS tube MN4 and is connected with the grid of the PMOS tube MP1 and the interconnection end of the grid of the NMOS tube MN1, the source of the NMOS tube MN4 is connected with the drain of the NMOS tube MN5, and the drain of the PMOS tube MP6 is connected with the drain of the NMOS tube MN6 and.

5. A high accuracy adaptive relaxation oscillator as claimed in claim 2, characterized in that: the circuit structure of the comparators CMP 1-CMP 6 comprises PMOS tubes MP 7-MP 9 and NMOS tubes MN 7-MN 10, the sources of the PMOS tubes MP 7-MP 9 are all connected with a power supply VCC, the grid of the PMOS tube MP7 is interconnected with the grid of the PMOS tube MP8 and connected with the drain of the PMOS tube MP7 and the drain of the NMOS tube MN7, the source of the NMOS tube MN7 is interconnected with the source of the NMOS tube MN8 and connected with the drain of the NMOS tube MN9, the grid of the NMOS tube MN9 is interconnected with the grid of the NMOS tube MN10 and connected with a bias voltage V_BIASThe source of the NMOS transistor MN9 and the source of the NMOS transistor MN10 are both grounded, the drain of the NMOS transistor MN10 is interconnected with the drain of the PMOS transistor MP9 and serves as the output terminal of the comparator, the gate of the NMOS transistor MN8 serves as the non-inverting input terminal of the comparator, and the gate of the NMOS transistor MN7 serves as the inverting input terminal of the comparator.

6. A high accuracy adaptive relaxation oscillator as claimed in claim 2, characterized in that: the circuit structure of the RS trigger RS 1-RS 3 comprises a PMOS tube MP10 ℃MP13 and NMOS tubes MN 11-MN 14, the source of PMOS tube MP10 and the source of PMOS tube MP12 are all connected with VCC, the drain of PMOS tube MP10 is connected with the source of PMOS tube MP11, the drain of PMOS tube MP12 is connected with the source of PMOS tube MP13, the sources of NMOS tubes MN 11-MN 14 are all grounded, the gate of NMOS tube MN11 and the gate of PMOS tube MP10 are connected with each other and serve as the set input S of the RS trigger, the gate of NMOS tube MN14 and the gate of PMOS tube MP13 are connected with each other and serve as the reset input R of the RS trigger, the gate of NMOS tube MN12 and the gate of PMOS tube 11 are connected with the drain of NMOS tube MN14, the drain of NMOS tube MN13 and the drain of PMOS tube MP13 and serve as the output Q of the RS trigger, the drain of NMOS tube MN12 and the drain of PMOS tube MP11 are connected with each other and the drain of NMOS tube MN11, the gate of NMOS tube MP 3687458 and the gate of PMOS tube MP12 are connected together and serve as the output end R of the output of the RS trigger

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