CN103346784B - A kind of matching type charge pump circuit for phase-locked loop - Google Patents
A kind of matching type charge pump circuit for phase-locked loop Download PDFInfo
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Abstract
The invention discloses a kind of matching type charge pump circuit for phase-locked loop, its structure comprises biasing circuit, current replication circuit, sinking constant-current source circuit, pull-up constant-current source circuit and switching circuit in proportion; Outside reference electric current scales up by biasing circuit in proportion; Current replication circuit is strictly copied to PMOS current mirror the electric current in NMOS current mirror; Sinking constant-current source circuit is used for for successive load electric discharge; Pull-up constant-current source circuit is used for for successive load charging; Switching circuit is for controlling opening and cutting off of charging and discharging currents source.Matching type charge pump circuit for phase-locked loop provided by the invention, in proportion the bias current mirroring ratios of biasing circuit, depend on the ratio of the resistance value between resistance R0, R1, and relative traditional structure is more accurately reliable; And be not subject to the impact of process corner and variations in temperature, accurately control the loop parameter of charge pump phase lock loop; Eliminate the electric charge existed in general charge pump design preferably and share effect.
Description
Technical Field
The invention relates to a charge pump phase-locked loop (CPPLL), in particular to a matching type charge pump circuit for the phase-locked loop, which realizes high matching of the circuit and can obviously reduce the phase noise of a phase-locked loop system.
Background
A CMOS charge pump phase-locked loop (CPPLL) has the advantages of high speed, low power consumption, low jitter, low cost, and easy integration, and is widely used in circuits such as frequency synthesis and clock recovery. As a key module in the charge pump phase locked loop, the current matching characteristic of the charge pump circuit is directly related to the near-end phase noise performance of the CPPLL. How to further improve the current matching characteristic of the charge pump is always the focus of charge pump design and research.
An ideal charge pump configuration is shown in fig. 1, and functions to convert the UP and DOWN signals output by a Phase Frequency Detector (PFD) into analog continuously varying voltage signals for tuning the oscillation skin rate of a control Voltage Controlled Oscillator (VCO). When the UP output signal of the PFD output is dominant, the current source I in the charge pumpupCharging the loop filter, increasing the voltage-controlled end voltage of the VCO, and correspondingly changing the oscillation frequency of the VCO; on the contrary, when the DOWN signal is dominant, the current source I in the charge pumpdownThe loop filter is discharged and the voltage controlled voltage signal of the VCO decreases. Compared with the first case, the output signal of the ideal charge pump should be kept at a fixed dc potential, the oscillation frequency of the VCO should not change, and the ideal charge pump circuit should have perfect charge-discharge current matching characteristics.
However, the common actual structure of the charge pump circuit has various non-ideal effects such as clock feed-through, charge sharing and the like, perfect matching under an ideal condition is difficult to achieve between the pull-up current and the sink current of the charge pump, and the matching characteristic of the circuit is far from reaching the matching state in the ideal condition.
Disclosure of Invention
The invention aims to solve the problems, and provides a novel charge pump circuit for a matching type charge pump circuit of a phase-locked loop, which can accurately control the proportion of current mirror images by adding a feedback auxiliary circuit, enables the pull-up and sink currents of charges to be accurately matched and can greatly reduce the non-ideal effect in the circuit. The circuit structure can reduce the non-ideal effect in the charge pump circuit by improving the current matching characteristic of the charge pump, remarkably inhibit the generation of phase noise (the ratio of signal power at a given frequency offset to the total signal power) and spurious (useless signals in a useful frequency band) in the CPPLL, improve the phase noise performance of the charge pump phase-locked loop, and finally enable the CPPLL to obtain an output signal with lower harmonic component.
In order to achieve the purpose, the invention adopts the technical scheme that: there is provided a matching type charge pump circuit for a phase locked loop, characterized in that: the circuit comprises a proportional bias circuit, a current copy circuit, a sinking constant current source circuit, a pull-up constant current source circuit and a switch circuit; wherein,
the proportional bias circuit amplifies the external reference current in proportion to generate bias current required by the charge pump circuit; the proportional bias circuit consists of a first operational amplifier OPA1 and a negative feedback circuit; the input end of the proportional bias circuit is connected with an external reference current source; the output end of the proportional bias circuit is connected with the input end of the current copying circuit; the positive input end and the negative input end of the first operational amplifier OPA1 are respectively connected with resistors R0 and R1 of a negative feedback circuit;
the current copying circuit strictly copies the current in the sinking constant current source circuit to the pull-up constant current source circuit, so that the current copying accuracy is ensured; the current replication circuit consists of a second operational amplifier OPA2 and a voltage clamp feedback circuit; the output end of the current copying circuit is connected with the output end of the charge pump circuit;
the sinking constant current source circuit is used for discharging for a rear-stage load; the gate end input of the sinking constant current source circuit is connected with the output end of a first operational amplifier OPA1 in the proportional bias circuit; the output end of the sinking constant current source circuit is connected with the output end of the charge pump circuit;
the pull-up constant current source circuit is used for charging a rear-stage load; the input end of the pull-up constant current source circuit is connected with the output end of a second operational amplifier OPA2 in the current replication circuit; the output end of the pull-up constant current source circuit is connected with the output end of the charge pump circuit;
the switch circuit is used for controlling the on and off of the charge and discharge current source.
The negative feedback circuit also comprises MOS tubes MN0, MN1, MN2 and a referenceTest current source Icp(ii) a (ii) a The reference current source IcpThe input end of the power supply is connected with a power supply; the reference current source IcpThe output end of the resistor R0 and the drain end of the MOS tube MN0 are connected in sequence; the source ends of the MOS tubes MN0 and MN2 are grounded; the gate ends of the MOS tubes MN0 and MN2 are connected with a high level; the drain end of the MOS transistor MN2, the resistor R1 and the source end of the MOS transistor MN1 are sequentially connected; the output end of the first operational amplifier OPA1 is connected with the gate end of a MOS tube MN 1; the drain terminal of the MOS transistor MN1 is the output terminal of the proportional bias circuit.
The first operational amplifier OPA1 is a PMOS input based operational amplifier.
The voltage clamping feedback circuit comprises resistors R2 and R3, a capacitor C0, MOS (metal oxide semiconductor) tubes MP0, MP1, MP2 and MP 3; the drain end of the MOS tube MP1 is connected with the drain end of the MOS tube MN 1; the source end of the MOS tube MP1 is connected with the drain end of the MOS tube MP 0; the gate end of the MOS transistor MP0 is connected with low level; the source ends of the MOS tubes MP0 and MP2 are connected with a power supply; the gate end of the MOS tube MP2 is connected with a switch input signal UP 1; the drain end of the MOS tube MP2 is connected with the source end of the MOS tube MP 3; the drain terminal of the MOS tube MP3 is connected with the output terminal OUT of the charge pump; the positive input end of the second operational amplifier OPA2 is connected with the drain end of the MOS tube MP 1; the negative input end of the second operational amplifier OPA2 is connected with one end of a resistor R3; the other end of the resistor R3 is connected with the output end OUT of the charge pump; the output end of the second operational amplifier OPA2 is simultaneously connected with the gate ends of MOS tubes MP1 and MP 3; one end of the capacitor C0 is connected with the output end of the second operational amplifier OPA2, and the other end of the capacitor C0 is connected with one end of the resistor R2; the other end of the resistor R2 is connected to the positive input of a second operational amplifier OPA 2.
The second operational amplifier OPA2 is a rail-to-rail operational amplifier.
The sinking constant current source circuit is composed of N NMOS current mirrors, wherein N is more than or equal to 1; the Nth NMOS current mirror comprises a resistor RN+3And MOS transistor MN2N+1(ii) a MOS manages MN2N+1Source terminal and resistor RN+3Is connected with one end of the connecting rod; the drain terminal of the MOS tube is connected with the output terminal OUT of the charge pumpConnecting; the resistor RN+3And the other end of the MOS transistor MN is connected with the MOS transistor MN in the switch circuit2N+2The drain terminal of (1) is connected.
The pull-up constant current source circuit is composed of N PMOS current mirrors, wherein N is more than or equal to 1; the Nth PMOS current mirror comprises an MOS (metal oxide semiconductor) transistor MP2N+1(ii) a The MOS tube MP2N+1Source end of and MOS tube MP in switch circuit2NThe drain end of the first transistor is connected; the MOS tube MP2N+1Is connected to the output OUT of the charge pump.
The switching circuit is composed of N NMOS switching tubes and N PMOS switching tubes, wherein N is more than or equal to 1; the Nth NMOS switching tube comprises a MOS tube MN2N+2(ii) a The Nth PMOS switching tube comprises an MOS tube MP2N(ii) a The MOS tube MP2NThe source end of the power supply is connected with a power supply; MOS manages MN2N+2The source terminal of which is grounded.
The matching type charge pump circuit for the phase-locked loop has the following beneficial effects:
1. the bias current mirror ratio of the proportional bias circuit depends on the ratio of the resistance values between the resistors R0, R1; in the design of a chip physical layout, the matching between resistors is more accurate and reliable than the width-length ratio matching of an MOS, and is not influenced by the process angle and the temperature change; the design is favorable for accurately controlling the magnitude of the pull-up and sink currents of the charge pump, so that the loop parameters of the CPPLL can be accurately controlled;
2. the current copy circuit clamps the output point voltage of the charge pump and the input node voltage of the copy circuit in a consistent manner by adopting a feedback structure formed by an operational amplifier, so that a pull-up constant current source circuit formed by a PMOS current mirror and a sink constant current source circuit formed by an NMOS current mirror are ensured that a plurality of paths of current mirror MOS (metal oxide semiconductor) tubes in the sink constant current source circuit are in the same bias state. The mirror proportion of each path of current meets the strict matching characteristic. The charge sharing effect existing in the common charge pump design is well eliminated;
3. the mirror image MOS tubes in the pull-up constant current source circuit and the sink constant current source circuit avoid adopting a common structure of a cascode current mirror under a common bias state, so that the voltage output of the charge pump obtains a wider swing range;
4. the switch circuit is designed at the source end of the current mirror MOS tube, so that the output impedance of the charge pump can be improved, and the current burr effect of the switch can be reduced.
Drawings
FIG. 1 is a schematic diagram of a conventional charge pump circuit;
fig. 2 is a circuit configuration of a matching type charge pump for a phase locked loop;
fig. 3 is a circuit configuration of a first operational amplifier in a matching type charge pump circuit for a phase locked loop;
fig. 4 is a circuit configuration of a second operational amplifier in the matching type charge pump circuit for the phase locked loop.
Detailed Description
The invention is described in detail below with reference to the figures and examples, which are not intended to limit the invention further.
As shown in fig. 2, the matching type charge pump circuit for phase-locked loop disclosed in the present invention includes a proportional bias circuit, a current replica circuit, a sinking constant current source circuit, a pulling-up constant current source circuit, and a switch circuit; wherein,
the proportional bias circuit is used for amplifying an external reference current in proportion and generating a bias current required by the charge pump circuit, and consists of a first operational amplifier OPA1 and a negative feedback circuit; the input end of the proportional bias circuit is connected with a power supply; the output end of the proportional bias circuit is connected with the input end of the current copying circuit; the negative feedback circuit comprises resistors R0 and R1; the positive input end and the negative input end of the first operational amplifier OPA1 are respectively connected with the resistors R0 and R1 to form a node 1 and a node 2; the negative feedback circuit also comprises MOS tubes MN0, MN1,MN2 and reference current source Icp(ii) a Reference current source IcpThe input end of the power supply is connected with a power supply; reference current source IcpThe output end of the resistor R0 and the drain end of the MOS tube MN0 are connected in sequence; the source ends of the MOS tubes MN0 and MN2 are grounded; the gate ends of the MOS tubes MN0 and MN2 are connected with high level; the drain end of the MOS transistor MN2, the resistor R1 and the source end of the MOS transistor MN1 are sequentially connected; the output end of the first operational amplifier OPA1 is connected with the gate end of the MOS transistor MN1 to form a node 3; the drain terminal of the MOS transistor MN1 is the output terminal of the proportional bias circuit.
The first operational amplifier OPA1 is an operational amplifier based on PMOS inputs. As shown in fig. 3, the first operational amplifier OPA1 includes an input bias current Ib, and inputs the differential pair PMOS transistors MP0 ', MP 1', the cascode output stages MP2 ', MP 3', MP4 ', MP 5', MN0 ', MN 1', MN2 ', and MN 3'. In this embodiment, the MOS transistors MN0 and MN2 in the proportional bias circuit have the same device size, are NMOS switching transistors in a normally open state, are the same size as the NMOS switching transistors in the NMOS switching circuit that controls the sinking constant current source, maintain good circuit matching characteristics, and have a very small on-resistance; the first OPA1 and the NMOS transistor MN1 form a negative feedback loop to clamp the voltages at the nodes 1 and 2 to the same dc level, so that the ratio of the currents flowing through the resistors R0 and R1 is completely determined by the ratio of the resistances of the resistors R0 and R1. Compared with a bias mode adopting a proportional mirror current source in a general design, the bias mode sacrifices the complexity of circuit design, and obtains a proportional bias circuit with better matching performance and proportional relation which does not change along with the process and temperature.
It is worth noting that the device model selection of the resistors R0 and R1 should select a low-value resistor with a large physical layout size in a process library, so as to improve matching accuracy, reduce the influence of resistance thermal noise on circuit noise performance, and further improve the output swing of the charge pump circuit. The first operational amplifier OPA1 in the proportional bias circuit can be chosen to have a variety of configurations, but its input amplitude range must be sufficient for low voltage requirements and the output voltage amplitude must be sufficient to operate the mirror in the NMOS mirror constant current source in the saturation region. According to the above requirements, as shown in fig. 3, the sleeve type operational amplifier using PMOS transistor input is a structure choice that is relatively in accordance with design requirements, and the high dc gain caused by the sleeve type structure can help the operational amplifier to better implement voltage clamping.
The current copying circuit strictly copies the current in the sinking constant current source circuit to the pull-up constant current source circuit, so that the current copying accuracy is ensured; the current copying circuit consists of a second operational amplifier OPA2 and a voltage clamping feedback circuit; the output end of the current copying circuit is connected with the output end of the charge pump circuit; the voltage clamping feedback circuit comprises resistors R2 and R3, a capacitor C0, MOS tubes MP0, MP1, MP2 and MP 3; the drain terminal of the MOS tube MP1 is connected with the drain terminal of the MOS tube MN 1; the source end of the MOS tube MP1 is connected with the drain end of the MOS tube MP 0; the gate terminal of the MOS transistor MP0 is connected with low level; the source ends of the MOS tubes MP0 and MP2 are connected with a power supply; the gate terminal of the MOS transistor MP2 is connected with a switch input signal UP 1; the drain end of the MOS tube MP2 is connected with the source end of the MOS tube MP 3; the drain terminal of the MOS tube MP3 is connected with the output terminal OUT of the charge pump; the positive input end of the second operational amplifier OPA2 is connected with the drain end of the MOS tube MP 1; the negative input end of the second operational amplifier OPA2 is connected with one end of a resistor R3; the other end of the resistor R3 is connected with the output end OUT of the charge pump; the output end of the second operational amplifier OPA2 is simultaneously connected with the gate ends of the MOS tubes MP1 and MP3 to form a node 4; one end of the capacitor C0 is connected to the output end of the second operational amplifier OPA2, and the other end is connected to one end of the resistor R2; the other end of the resistor R2 is connected to the positive input of a second operational amplifier OPA 2.
MOS tubes MP0 and MP2 in the current copy circuit are PMOS switching tubes with the same size, and MP0 is in a normally open conducting state, so that absolute values of the current flowing through the source and drain terminals of the MOS tubes MN1 and MP1 are kept consistent. MP1 and MP3 have the same device size, keeping 1: 1, the second operational amplifier OPA2 and the MOS tube MP1 form a negative feedback loop, the voltages of the positive and negative input ends of the second operational amplifier OPA2 are clamped on the same direct current level, namely, the gate ends of the MOS tube MP1 and the MP3 are directly connected, the voltages of the drain ends are clamped uniformly, and the switching tubes connected with the source ends have the same device type and specific size. Therefore, when the gate end signal of the MOS transistor MP2 is at a high level, the branch is turned off, and almost no current flows through the MOS transistor MP 3; when the gate signal of the MOS transistor MP2 is at a low level, the MOS transistors MP2 and MP0 are turned on simultaneously, and the mirror current sources formed by the MOS transistors MP1 and MP3 are strictly matched, that is, the absolute values of the magnitudes of the currents flowing through the sources and the drains of the MOS transistors MN1 and MP3 are also kept consistent, so that the current copying is accurately completed.
The loop feedback in the current replica circuit is complex, the second operational amplifier OPA2 and the MOS transistor MP1 form a negative feedback loop, and the second operational amplifier OPA2 and the MOS transistor MP3 form a positive feedback loop. Since the negative feedback loop is always in the conducting state, and the positive feedback loop starts the positive feedback only when the switch MP2 is in the conducting state, the whole circuit will not oscillate after the loop compensation is added. The capacitor C0 and the resistor R2 function as loop compensation. The resistor R3 has almost no current flowing through, the voltage at two ends is kept consistent, and R3 has certain filtering function relative to the output of the charge pump.
The second operational amplifier OPA2 is a rail-to-rail operational amplifier, the detailed circuit of which is shown in fig. 4. Compared with the first operational amplifier OPA1, the structure is added with an input bias current Ib2 ' and input differential pair NMOS transistors MN0 ' and MN1 '; in performance, the second operational amplifier OPA2 achieves a rail-to-rail voltage input range to meet the large swing requirement of the charge pump circuit output at the cost of increased current consumption and circuit complexity.
The sinking constant current source circuit is used for discharging for the rear-stage load; the gate terminal input of the sinking constant current source circuit is connected with a node 3 (namely, a first operational amplifier OPA 1) in the proportional bias circuit; the output end of the sinking constant current source circuit is connected with the output end of the charge pump circuit; the sinking constant current source circuit is composed of N NMOS current mirrors, wherein N is more than or equal to 1; the Nth NMOS current mirror comprises a resistor RN+3And MOS transistor MN2N+1(ii) a MOS manages MN2N+1Source terminal and resistor RN+3Is connected with one end of the connecting rod; the drain terminal of the MOS tube is connected with the output terminal OUT of the charge pump; the resistor RN+3And the other end of the MOS transistor MN is connected with the MOS transistor MN in the switch circuit2N+2The drain end of the first transistor is connected; NMOS tubeMN3、MN5、MN7…MN2N+1Is terminated to node 3. MN3, MN5 and MN7 … MN of N-path NMOS current mirror2N+1The size of the MOS transistor MN1 is the same, the same grid terminal voltage is obtained from the node 3, the source terminal is connected with the same load and then controlled by the switch tube, and the drain terminal outputs.
The pull-up constant current source circuit is used for charging a rear-stage load; the input end of the pull-up constant current source circuit is connected with a node 4 (namely, the output end of the second operational amplifier OPA 2) in the current replication circuit; the output end of the pull-up constant current source circuit is connected with the output end of the charge pump circuit; (ii) a The pull-up constant current source circuit is composed of N PMOS current mirrors, wherein N is more than or equal to 1; the Nth PMOS current mirror comprises an MOS transistor MP2N+1(ii) a MOS tube MP2N+1Source end of and MOS tube MP in switch circuit2NThe drain end of the first transistor is connected; MOS tube MP2N+1The drain terminal of the charge pump is connected with the output terminal OUT of the charge pump; PMOS tubes MP3, MP5 and MP7 … MP2N+1Is terminated to node 4. MP3, MP5 and MP7 … MP of N-path PMOS current mirror2N+1The same size as that of the MOS transistor MP1, the same gate terminal voltage is obtained from the node 4, the source terminal is controlled by the switch tube, and the drain terminal outputs.
The current mirror preferably maintains a 1: 1, optimal mirror ratio. The current value of each constant current source is not suitable for being too small, when the value is too small, a plurality of current mirrors are required to be connected in parallel to meet the current size of the charge pump required by a loop, the actual layout of each constant current source needs to occupy a certain area, and the gate end voltage control signals from the nodes 3 and 4 are likely to be lost in a longer transmission path, so that the current mirror ratio mismatch is caused, and the difference between the actual size of the charge pump current and the design value is also caused; the current value of each constant current source is not too large, and when the value is too large, the invention loses the significance of designing a plurality of paths of constant current sources. The reason is that random factors influencing the matching characteristic of the circuit exist in each link of process, temperature, layout, processing and the like, and the matching characteristic of the charge pump obtained through actual test is often lower than a simulation value. The simulation condition of a charge pump circuit meeting the mismatch of about 1% in a general design is generally about 10% in an actual test, and the phase of the CPPLL is seriously influencedNoise and spurious performance. The design of multi-path constant current source provides possibility for controlling the random factors, NMOS current mirror and PMOS current mirror no longer have to obey one-to-one design rule, and designers can use control signals UP1, UP2 and UP3 … UP from the front-stage phase frequency detectorNAnd DN1, DN2, DN3 … DNNWhether to conduct or not to control whether a branch has either a pull-up current or a sink current only or both. Through the method, the mismatching of the actually tested charge pump can be controlled within 1/N, and the value of N is more suitable between 8 and 16 generally according to design experience.
The switching circuit is used for controlling the on and off of the charge and discharge current source; the switching circuit is composed of N NMOS switching tubes and N PMOS switching tubes, wherein N is more than or equal to 1; the Nth NMOS switching tube comprises a MOS tube MN2N+2(ii) a The Nth PMOS switching tube comprises an MOS tube MP2N(ii) a The MOS tube MP2NThe source end of the power supply is connected with a power supply; MOS manages MN2N+2The source terminal of which is grounded.
The current mirror and the switch tube are important noise sources in the charge pump circuit, so the current mirror image tube is often larger in device size and keeps 1: 1, optimal mirror ratio. And switching tubes MP2, MP4 and MP6 … MP2NThe device types are selected and the device sizes are consistent, namely MN4, MN6 and MN8 …2N+2The device selection and the device size are consistent, so that all the image tubes are ensured to be in the same bias state under the conduction condition.
Claims (8)
1. A matching type charge pump circuit for a phase locked loop, characterized by: the circuit comprises a proportional bias circuit, a current copy circuit, a sinking constant current source circuit, a pull-up constant current source circuit and a switch circuit; wherein,
the proportional bias circuit amplifies the external reference current in proportion to generate bias current required by the charge pump circuit; the proportional bias circuit consists of a first operational amplifier OPA1 and a negative feedback circuit; the input end of the proportional bias circuit is connected with an external reference current source; the output end of the proportional bias circuit is connected with the input end of the current copying circuit; the positive input end and the negative input end of the first operational amplifier OPA1 are respectively connected with resistors R0 and R1 of a negative feedback circuit;
the current copying circuit strictly copies the current in the sinking constant current source circuit to the pull-up constant current source circuit; the current replication circuit consists of a second operational amplifier OPA2 and a voltage clamp feedback circuit; the output end of the current copying circuit is connected with the output end of the charge pump circuit;
the sinking constant current source circuit is used for discharging for a rear-stage load; the sinking constant current source circuit is composed of N NMOS current mirrors, wherein N is more than or equal to 1; the gate end input of the sinking constant current source circuit is connected with the output end of a first operational amplifier OPA1 in the proportional bias circuit; the output end of the sinking constant current source circuit is connected with the output end of the charge pump circuit;
the pull-up constant current source circuit is used for charging a rear-stage load; the pull-up constant current source circuit is composed of N PMOS current mirrors, wherein N is more than or equal to 1; the input end of the pull-up constant current source circuit is connected with the output end of a second operational amplifier OPA2 in the current replication circuit; the output end of the pull-up constant current source circuit is connected with the output end of the charge pump circuit;
the switch circuit is used for controlling the on and off of the charge and discharge current source.
2. The matching type charge pump circuit for phase locked loop according to claim 1, wherein: the negative feedback circuit also comprises MOS tubes MN0, MN1, MN2 and a reference current source Icp(ii) a The reference current source IcpThe input end of the power supply is connected with a power supply; the reference current source IcpThe output end of the resistor R0 and the drain end of the MOS tube MN0 are connected in sequence; the source ends of the MOS tubes MN0 and MN2 are grounded; the gate ends of the MOS tubes MN0 and MN2 are connected with a high level; the drain end of the MOS transistor MN2, the resistor R1 and the source end of the MOS transistor MN1 are sequentially connected; the output end of the first operational amplifier OPA1 is connected with the gate end of a MOS tube MN 1; the drain terminal of the MOS transistor MN1 is the output terminal of the proportional bias circuit.
3. The matching type charge pump circuit for phase locked loop according to claim 1 or 2, characterized in that: the first operational amplifier OPA1 is a PMOS input based operational amplifier.
4. The matching type charge pump circuit for phase locked loop according to claim 1, wherein: the voltage clamping feedback circuit comprises resistors R2 and R3, a capacitor C0, MOS (metal oxide semiconductor) tubes MP0, MP1, MP2 and MP 3; the drain end of the MOS tube MP1 is connected with the drain end of the MOS tube MN 1; the source end of the MOS tube MP1 is connected with the drain end of the MOS tube MP 0; the gate end of the MOS transistor MP0 is connected with low level; the source ends of the MOS tubes MP0 and MP2 are connected with a power supply; the gate end of the MOS tube MP2 is connected with a switch input signal UP 1; the drain end of the MOS tube MP2 is connected with the source end of the MOS tube MP 3; the drain terminal of the MOS tube MP3 is connected with the output terminal OUT of the charge pump; the positive input end of the second operational amplifier OPA2 is connected with the drain end of the MOS tube MP 1; the negative input end of the second operational amplifier OPA2 is connected with one end of a resistor R3; the other end of the resistor R3 is connected with the output end OUT of the charge pump; the output end of the second operational amplifier OPA2 is simultaneously connected with the gate ends of MOS tubes MP1 and MP 3; one end of the capacitor C0 is connected with the output end of the second operational amplifier OPA2, and the other end of the capacitor C0 is connected with one end of the resistor R2; the other end of the resistor R2 is connected to the positive input of a second operational amplifier OPA 2.
5. The matching type charge pump circuit for phase locked loop according to claim 1 or 4, characterized in that: the second operational amplifier OPA2 is a rail-to-rail operational amplifier.
6. The matching type charge pump circuit for phase locked loop according to claim 1, wherein: the Nth NMOS current mirror comprises a resistor RN+3And MOS transistor MN2N+1(ii) a MOS manages MN2N+1Source terminal and resistor RN+3Is connected with one end of the connecting rod; the drain terminal of the MOS tube is connected with the output terminal OUT of the charge pump; the resistor RN+3And the other end of the switch circuitMOS tube MN in2N+2The drain terminal of (1) is connected.
7. The matching type charge pump circuit for phase locked loop according to claim 1, wherein: the Nth PMOS current mirror comprises an MOS (metal oxide semiconductor) transistor MP2N+1(ii) a The MOS tube MP2N+1Source end of and MOS tube MP in switch circuit2NThe drain end of the first transistor is connected; the MOS tube MP2N+1Is connected to the output OUT of the charge pump.
8. The matching type charge pump circuit for phase locked loop according to claim 1, 6 or 7, characterized in that: the switching circuit is composed of N NMOS switching tubes and N PMOS switching tubes, wherein N is more than or equal to 1; the Nth NMOS switching tube comprises a MOS tube MN2N+2(ii) a The Nth PMOS switching tube comprises an MOS tube MP2N(ii) a The MOS tube MP2NThe source end of the power supply is connected with a power supply; MOS manages MN2N+2The source terminal of which is grounded.
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| CN104811189A (en) * | 2015-05-14 | 2015-07-29 | 东南大学 | Charge pump circuit in charge pump phase-locked loop |
| US9444406B1 (en) * | 2015-06-29 | 2016-09-13 | Silicon Laboratories Inc. | Amplifier topology achieving high DC gain and wide output voltage range |
| CN106849646B (en) * | 2017-03-30 | 2019-09-10 | 中国人民解放军国防科学技术大学 | A kind of low jitter charge pump with radiation-resisting performance |
| CN107896108B (en) * | 2017-12-07 | 2020-11-17 | 西安电子科技大学 | Charge pump circuit for phase locked loop |
| CN109917842B (en) * | 2019-04-16 | 2021-11-02 | 卓捷创芯科技（深圳）有限公司 | Clamp feedback starting circuit for eliminating self-biased bandgap reference degeneration metastable state |
| WO2020232726A1 (en) * | 2019-05-23 | 2020-11-26 | 华为技术有限公司 | Phase locked loop |
| CN113534883B (en) * | 2021-04-26 | 2022-10-25 | 西安交通大学 | A charge pump circuit with current source and compensation function |
| CN114167125B (en) * | 2021-07-29 | 2023-12-12 | 沈阳工业大学 | Current detection circuit |
| CN115118277B (en) * | 2022-08-29 | 2022-11-18 | 成都芯矩阵科技有限公司 | Charge pump, phase-locked loop and method for improving reference stray of phase-locked loop |
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