CN107204755A - A kind of relaxor of high-accuracy self-adaptation - Google Patents

Abstract

A high-precision self-adaptive relaxation oscillator, using the principle of capacitor pre-charging to offset the delay generated by the charging and discharging control circuit in the oscillating circuit, including an oscillating circuit, a first capacitor pre-charging circuit and a second capacitor pre-charging circuit, The capacitor pre-charging circuit is used to pre-charge the capacitor for charging and discharging the oscillator. The oscillating circuit charges and discharges on the basis of the pre-charging level of the capacitor pre-charging circuit. At the set frequency, the linearity of the frequency-control current can be significantly improved, and the present invention does not directly reduce the delay by increasing the speed of the comparator or the RS flip-flop, but cancels the delay generated by the control circuit through two charging processes As well as the influence of the offset that changes with the external environment, the accuracy of the oscillator is significantly improved, and it has strong temperature stability and power supply voltage suppression, that is, self-adaption.

Description

A High Precision Adaptive Relaxation Oscillator

technical field

The invention relates to a relaxation oscillator, in particular to a high-precision self-adaptive relaxation oscillator, which belongs to the technical field of CMOS integrated circuits.

Background technique

In large-scale integrated circuits, clock signals are generally generated by oscillators. The relaxation oscillator has a simple structure, low cost, easy integration, and relatively low power consumption. It is the most widely used clock generation circuit in the oscillator.

In the application of signal modulation and demodulation, data recovery of storage system, etc., the control current-frequency of the relaxation oscillator used is required to have a high linearity, so as to reduce distortion and increase the relaxation oscillation frequency range of the device. In the relaxation oscillator, the linearity of the control current-frequency is related to the delay of the control circuit of the oscillation amplitude of the charging and discharging capacitor. Therefore, to improve the linearity of the oscillator, to maximize the frequency of the oscillator must minimize the influence of the delay of the control circuit. In the clock recovery circuit, in order to obtain a larger dynamic range, the relaxation oscillator circuit is required to have small jitter. The jitter of the relaxation oscillator circuit is caused by the noise of the circuit itself. A relaxation oscillator circuit with small jitter requires an increase in the oscillation amplitude of its charging and discharging capacitance.

In the prior art, relaxation oscillators have many different structures, and the common requirements for relaxation oscillators of different structures are high precision and good linearity of frequency-controlled current at high frequencies. But the existing relaxation oscillators still have some deficiencies.

Figure 1 shows a current-controlled relaxation oscillator with a single timing capacitor, including charging current source I _charge , discharging current source I _discharge , PMOS transistor M1, NMOS transistor M2, timing capacitor C, two comparators COMP1 and COMP2, and RS trigger device. The output terminal Q of the RS flip-flop is connected to the gate terminals of the PMOS transistor M1 and the NMOS transistor M2. Depending on the signal at the output terminal Q of the RS flip-flop, the PMOS transistor M1 and the NMOS transistor M2 are alternately turned on and off, and the charging current source I _charge and the discharging current source I _discharge alternately charge and discharge the timing capacitor C.

A current-controlled relaxation oscillator with a single timing capacitor operates as follows:

S1) When the output terminal Q of the RS flip-flop is at low level, the PMOS transistor M1 is turned on, the NMOS transistor M2 is turned off, and the charging current source I _charge is given to charge the capacitor C, when the voltage on the timing capacitor C rises above the upper reference level When V is _H , the comparator COMP1 outputs a high level, the RS flip-flop is in a set state, and the output terminal Q outputs a high level;

S2) When the output terminal Q of the RS flip-flop outputs a high level, the PMOS transistor M1 is turned off, the NMOS transistor M2 is turned on, and the discharge current source I _discharge starts to discharge the capacitor C, and the voltage on C drops. When the timing capacitor C When the voltage drops to less than the lower reference level V _L , the comparator COMP2 outputs a high level, the RS flip-flop is in a reset state, and the output terminal Q outputs a low level;

The output terminal Q of the RS flip-flop is low level, returns to the initial state, and then repeats the above two processes in turn.

The current of a single timing capacitor controls the voltage across the capacitor of the relaxation oscillator to oscillate back and forth between an upper reference level V _H and a lower reference level V _L . If the delay of the control circuit (COMP1, COMP2 and RS flip-flops in Fig. 1) can be ignored, and I _charge =I _discharge =I, then the period and frequency of the oscillator are

It can be seen from Equation 2 that if the delay of the control circuit can be ignored, once the capacitor C, the upper reference level V _H and the lower reference level V _L are selected, the current of a single timing capacitor controls the frequency of the relaxation oscillator proportional to the control Current I.

However, the delay of the control circuit of the relaxation oscillator controlled by the current of a single timing capacitor shown in Fig. 1 cannot be ignored, and the actual waveform of the voltage on the timing capacitor C is shown in Fig. 2 . Due to the time delay of the control circuit, when the voltage on the timing capacitor C reaches the upper reference level V _H , the PMOS transistor M1 is not turned off immediately, and the NMOS transistor M2 is not turned on immediately, resulting in the voltage on the capacitor being overcharged. And due to the overcharge of the voltage on the capacitor, when the capacitor voltage drops, it is required to have the same time to discharge the overcharged charge (assuming I _charge = I _discharge ), in this process, the delay of the control circuit is 2td, when the timing capacitor When C discharges to close to the lower reference level V _L , it will also produce over-discharge phenomenon. Therefore, the total delay in one cycle is T _d = 4td, so the frequency formula (Formula 2) is corrected as

Among them, f _ideal is the ideal frequency in formula 1, and T _d is the delay 4td in one cycle of the oscillator. The relationship between the actual frequency f and the control current in Formula 3 can be expressed in Figure 3.

Therefore, in order to improve the linearity and maximize the frequency of the oscillator, the time delay _Td in one cycle of the relaxation oscillator must be reduced.

At the same time, the current-controlled relaxation oscillator with a single timing capacitor also has many other disadvantages, such as the need for two reference levels; and because of the existence of two reference levels, the oscillation amplitude of the timing capacitor is limited, resulting in the circuit itself The noise of the charge and discharge capacitor has an impact on the threshold level of the charge and discharge capacitor, and this effect will accumulate in each cycle, and finally affect the output frequency of the oscillator; finally, due to the mismatch of the device, its charge current and discharge current cannot be completely accurate are equal, therefore, it is difficult to obtain a 50% duty cycle. Therefore, it is necessary to improve the current-controlled relaxation oscillator with a single timing capacitor to address the above shortcomings.

Aiming at the insufficiency of the current-controlled relaxation oscillator with a single timing capacitor, Figure 4 shows a current-controlled relaxation oscillator with dual timing capacitors that can reduce the delay _Td in one cycle, including current sources I ₁ and I ₂ , PMOS tube M3, NMOS tube M4, PMOS tube M5, NMOS tube M6, timing capacitors C01 and C02, two comparators COMP3 and COMP4, RS flip-flop, the non-inverting terminals of comparator COMP3 and comparator COMP4 are respectively connected to timing capacitor C01 , the timing capacitor C02, the inverting terminals of the comparator COMP3 and the comparator COMP4 are connected together to the reference level V _R .

The operation of a current-controlled relaxation oscillator with dual timing capacitors is as follows:

S1) When the circuit starts to work, the output terminal Q of the RS flip-flop is at a low level, the output terminal Q is at a high level, the PMOS transistor M3 is turned on, and the NMOS transistor M4 is turned off. When the current source I _{charge1 is} given, the capacitor C01 is charged, and the PMOS The tube M5 is turned off, the NMOS tube M6 is turned on, and the timing capacitor C02 is discharged to the ground GND. When the voltage on the timing capacitor C01 rises above the reference level VR, the comparator COMP3 outputs a high level, and the _RS flip-flop is in the set state , the output terminal Q becomes high level, and the output terminal Q becomes low level;

S2) The output terminal Q of the RS flip-flop is high level, the output terminal Q is low level, the PMOS transistor M3 is turned off, the NMOS transistor M4 is turned on, the timing capacitor C01 is discharged to the ground GND, the PMOS transistor M5 is turned on, and the NMOS transistor M6 is turned off When the current source I _{charge2 is} given, the capacitor C02 is charged. When the voltage on the timing capacitor C02 exceeds the reference level VR, the comparator COMP4 outputs a high level, the _RS flip-flop is in the reset state, and the output terminal Q becomes a low level. , the output terminal Q is high level;

S3) The output terminal Q of the RS flip-flop is at low level, and the output terminal Q is at high level, returning to the initial state S1).

Compared with the current-controlled relaxation oscillator of Figure 1 with a single timing capacitor, the current-controlled relaxation oscillator with dual timing capacitors shown in Figure 4 has a significantly improved effect:

1) The amplitude of the charging and discharging capacitor of the dual timing capacitor relaxation oscillator is larger than that of the charging and discharging capacitor of a single timing capacitor relaxation oscillator, and can oscillate between close to GND and close to the power supply voltage, thereby reducing the circuit itself. The effect of noise on the flipping level of charge and discharge capacitors.

2) A relaxation oscillator with dual timing capacitors requires only one reference level, while a relaxation oscillator based on a single timing capacitor requires two reference levels.

3) The cycle of the relaxation oscillator of the dual timing capacitors is only determined by the charging process of the capacitors C01 and C02. The charging time of the timing capacitor C02 determines the time when the oscillator output terminal Q is at a high level, and the charging time of the timing capacitor C01 determines the time when the oscillator output Q is at a low level. The cycle of the current-controlled relaxation oscillator of the dual timing capacitor is only determined by the charging process of the capacitor, and its waveform is shown in Fig. ) and the delay of the PMOS tube M3, NMOS tube M4, PMOS tube M5, and NMOS tube M6 used as control switches can affect the cycle of the oscillator, and the delay of the capacitor discharge process does not affect the cycle of the oscillator. Therefore, the entire cycle The delay is reduced from 4td to 2td in a single timing capacitor structure, which improves the control linearity of the oscillator circuit and increases the maximum frequency range of the circuit.

Although the current-controlled relaxation oscillator with dual timing capacitors reduces the delay from 4td to 2td in one cycle, the output frequency of the oscillator is still controlled by the timing capacitor oscillation amplitude control circuit and the PMOS transistor M3 as a control switch , NMOS tube M4, PMOS tube M5, and NMOS tube M6’s delay 2td, especially at high frequencies, the 2td delay is even greater than the period of the oscillator output waveform, which not only reduces the linearity of the frequency-control current, Moreover, the maximum frequency range of the oscillator is limited, so it is necessary to further improve the current-controlled relaxation oscillator with dual timing capacitors to reduce the influence of delay.

Aiming at the shortcomings of the current-controlled relaxation oscillator with dual timing capacitors, Figure 6 shows a high-linearity relaxation oscillator with reference level self-regulation, including an oscillation circuit, a reference level self-regulation circuit and transmission gate selection signal generation circuit. By detecting the peak voltage of the charging and discharging capacitor in the oscillating circuit, the overcharge of the capacitor voltage caused by the delay of the control circuit is obtained, so that the reference level of the comparator in the oscillating circuit is reduced by the corresponding amount as a new reference level To make the oscillation amplitude of the charge and discharge capacitor just the theoretical value, when the new reference level is greater than zero, the relaxation oscillator eliminates the influence of the charge and discharge capacitor on the output frequency caused by the overcharge of the capacitor voltage caused by the delay of the control circuit, Significantly improves the linearity of the frequency-control circuit of the relaxation oscillator. The transmission gate selection signal generation circuit provides the initial reference level for the comparator by controlling the transmission gate. After the new reference level is generated, it is sent to the comparator The inverting terminal of the comparator, and the original reference level is isolated from the inverting terminal of the comparator.

The reference level self-adjusting high linearity relaxation oscillator works as follows:

S1) Assuming that the output terminal Q of the RS flip-flop is at a low level at the beginning, the output terminal Q is at a high level, the control switch S01 is turned on, the control switch S02 is turned off, the current I flows to the charge and discharge capacitor C1, the control switch S03 is turned off, The control switch S04 is turned on, and the charging and discharging capacitor C2 is discharged to the ground. When the potential on the charging and discharging capacitor C1 rises above the initial reference level V _ref of the first comparator COMP5, the first comparator COMP5 outputs a high level, and RS The flip-flop is in the set state, the output terminal Q outputs a high level, and the output terminal Q is a low level. At the same time, the peak value V _peak of the waveform on the charge and discharge capacitor C1 is detected and held by the peak detection and hold circuit, and then passed through the subtractor The circuit subtracts twice the initial reference level 2V _ref to obtain 2V _ref −V _peak , and transmits it to the input terminal of the second transmission gate TG2 . When the circuit is just turned on, V _φ in the transmission gate selection signal generating circuit is low level, At this time, the first transmission gate TG1 is turned on, and the initial reference level V _ref is transmitted to the inverting terminals of the first comparator COMP5 and the second comparator COMP6 in the oscillation circuit. When the circuit is turned on, the transmission gate After the PMOS transistors M7 and M8 in the selection signal generating circuit charge the capacitor C3, V _φ is at a high level, At this time, the first transmission gate TG1 is turned off, the second transmission gate TG2 is turned on, and the signal 2V _ref -V _peak is transmitted to the inverting terminals of the first comparator COMP5 and the second comparator COMP6 through the second transmission gate TG2 as the new reference level;

S2) The output terminal Q of the RS flip-flop outputs a high level, the output terminal Q is a low level, the charging control switch S01 is turned off, the control switch S02 is turned on, the charging and discharging capacitor C1 is discharged to the ground, the control switch S03 is turned on, and the control switch S04 Turn off, the current I flows to the charge and discharge capacitor C2, when the potential on the charge and discharge capacitor C2 rises to exceed the reference level of the second comparator COMP6 (initially V _ref , the transmission gate selection signal generation circuit charges the capacitor C3 Then when it is 2V _ref -V _peak ), the second comparator COMP6 outputs a high level, the RS flip-flop is in a reset state, the output terminal Q outputs a low level, and the output terminal Q is a high level;

S3) The output terminal Q of the RS flip-flop is at low level, the output terminal Q is at high level, returns to the initial state S1), and then circulates in turn.

It can be seen from the above working process that the amplitude of the charge and discharge capacitor in the relaxation oscillator is theoretically V _ref . Due to the delay of the control circuit, the voltage on the charge and discharge capacitors C1 and C2 is overcharged, and the voltage overcharge is The period of the oscillator will be extended and the frequency will be reduced. Therefore, in order to eliminate the influence of overcharge, the reference level of the comparator is reduced by adding a reference level self-adjusting circuit, so that the voltage amplitude on the charging and discharging capacitor is just the theoretical value V _ref , so that the output frequency of the oscillator is just the theoretical design value, and the linearity of the frequency-control current is improved. In order to make the voltage amplitude on the charging and discharging capacitor just equal to the theoretical value V _ref , we use a peak detection and hold circuit to detect the peak value V _peak on the charging and discharging capacitor C1, and then calculate the overcharge V _peak of the voltage on the charging and discharging capacitor C1 -V _ref , in order to make the charging range on the capacitor C1 just equal to the theoretical value V _ref , we subtract the overcharge from the reference level of the comparator as the new reference level, that is, V _ref -(V _peak -V _ref ) =2V _ref -V _peak , the subtraction process to obtain the signal 2V _ref -V _peak is realized by the subtractor. Since the delay of the control circuit is fixed, and after a charge control current I is selected, the overcharge voltage on the charge and discharge capacitor is fixed, therefore, the reference level of the comparator is reduced by an overcharge amount as a new reference Level, so that the voltage amplitude on the charging and discharging capacitor is just the theoretical design value is feasible. Therefore, when the reference level 2V _ref -V _peak provided by the present invention is greater than 0, the influence of the delay of the control circuit on the output frequency of the relaxation oscillator is eliminated, and the frequency-control current linearity of the oscillator is significantly improved. degrees, maximizing the frequency of the relaxation oscillator. Before adding the reference level automatic adjustment circuit and after adding the reference level automatic adjustment circuit, the waveform changes on the capacitor C1 are shown in Figure 7. The amplitude of the charge and discharge capacitor in the relaxation oscillator is theoretically V _ref , due to the control The delay of the circuit leads to the overcharging of the voltage on the charging and discharging capacitors C1 and C2, and the overcharging of the voltage will prolong the period of the oscillator and reduce the frequency, eliminating the influence of the overcharging of the capacitor voltage.

Although the high linearity relaxation oscillator with reference level self-adjustment reduces the transmission delay through the reference level self-adjustment circuit, it should be noted here that the delay of the control circuit will vary with temperature, offset and power supply voltage. Changes and changes, changes in the external environment will cause the peak voltage V _peak on the charge and discharge capacitors C1 and C2 to change, and the effect of the high-precision relaxation oscillator of the above method will become worse, because the reference level self-adjustment is reduced here It is a fixed value transmission delay under a certain condition.

Aiming at the shortcomings of the current-controlled relaxation oscillator with double timing capacitors, Figure 8 shows a high-linearity relaxation oscillator with error delay detection, including an oscillation circuit, a delay error detection circuit, and a modulation current generation circuit. The timing error detection circuit is used to detect the peak voltage of the charging and discharging capacitor in the oscillating circuit, and generate a delay error elimination signal according to the peak voltage, so that the oscillator oscillates at a preset frequency, and the modulation current generation circuit according to the peak value of the charging and discharging capacitor Voltage, generate a corresponding additional control current, increase the charging rate of the charging and discharging capacitor, eliminate the influence of the delay of the oscillating circuit, and improve the linearity of the control current-frequency.

Error delay detection High linearity relaxation oscillator works as follows:

As shown in Figure 8, when the initial state is set, the output terminal Q of the RS flip-flop is at low level, the output terminal Q is at high level, the control switch S1 is turned on, the control switch S2 is turned off, the control current flows to the charge and discharge capacitor C1, and the control switch S3 is turned off, the control switch S4 is turned on, and the charge and discharge capacitor C2 is discharged to the ground. In theory, when the potential on the charge and discharge capacitor C1 rises above the reference level V _ref , the comparator COMP7 outputs a high level, and the RS flip-flop is at In the set state, the output terminal Q outputs a high level, the output terminal Q is a low level, the control switch S1 is turned off, the control switch S2 is turned on, the charging and discharging capacitor C1 is discharged to the ground, the control switch S3 is turned on, and the control switch S4 is turned off. The control current flows to the charging and discharging capacitor C2. When the potential of the charging and discharging capacitor C2 rises above the reference level V _ref , the output terminal Q of the RS flip-flop is at a low level, and the output terminal Q is at a high level, and cycles in turn to generate oscillation waveform, but in fact due to the delay of the oscillating circuit, the peak voltages of the charging and discharging capacitors C1 and C2 will be greater than V _ref , resulting in the nonlinearity of the control current-frequency. The present invention uses the peak detection and hold in the delay error detection circuit The circuit detects the peak voltage on the charging and discharging capacitors C1 and C2, and uses this peak signal as the control signal of the modulation current generation circuit. The greater the circuit delay, the greater the peak voltage V _peak will be, so that the output current of the modulation current generation circuit It also increases accordingly, and the charging rate of the charging and discharging capacitors C1 and C2 increases. When the modulation current reaches the preset value, the output frequency of the oscillator is the preset frequency, eliminating the influence of the circuit delay.

Although the high linearity relaxation oscillator with error delay detection reduces the transmission delay, the above circuit needs to detect the peak voltage on the charge and discharge capacitors C1 and C2 first, and then use the detected peak voltage as the modulation current The control signal of the generation circuit increases the output current of the modulation current generation circuit, and the frequency of the oscillator gradually increases. It takes a long time until the frequency of the oscillator reaches the preset value, that is, the oscillator has a long start-up time. Moreover, the delay of the control circuit will change with changes in temperature, offset and power supply voltage. Changes in the external environment will cause changes in the peak voltage V _peak0 on the charging and discharging capacitors C1 and C2. If the oscillator frequency reaches a stable Previously, the delay of the control circuit changed due to changes in temperature, offset, and power supply voltage, and the frequency of the oscillator would be difficult to reach a stable value within a certain period of time, which would cause the oscillator to function abnormally. The existence of the above-mentioned relaxation oscillator greatly limits the performance stability.

Contents of the invention

Aiming at the problem that the relaxation oscillator can maintain high precision when the external environment changes, the invention proposes a method of using the principle of capacitor pre-charging to offset the delay generated by the charge-discharge control circuit, so as to significantly improve the high linearity of frequency-control current The relaxation oscillator with self-adaptive precision can still maintain a high precision as the external environment changes.

In order to achieve the above invention, the present invention adopts the following technical scheme: a high-precision self-adaptive relaxation oscillator, which is characterized in that: based on the oscillation circuit, two capacitor pre-charging circuits are added, and the principle of capacitor pre-charging is used to offset the The delay generated by the charging and discharging control circuit in the oscillator circuit; including the oscillator circuit, the first capacitor pre-charging circuit and the second capacitor pre-charging circuit, the capacitor pre-charging circuit is used to pre-charge the oscillator charging and discharging capacitor, the oscillator circuit is in the capacitor The pre-charging circuit performs charging and discharging on the basis of the pre-charging level, and offsets the error delay caused by the two-time charging of the capacitor, so that the oscillator works at the preset frequency and achieves a significant increase in frequency-control current linearity; where:

The oscillating circuit includes current sources I ₀ , I ₁ , control switches S30 , S40 , charge and discharge capacitors C10 , C20 , comparators CMP1 , CMP2 , RS flip-flop RS1 and a reference level V _X +V _ref , wherein the comparators CMP1 , CMP2 and RS flip-flop RS1 form a charge and discharge control circuit; the negative poles of the current source _I0 and the negative poles of the current source _I1 are connected to the power supply VDD, and the positive poles of the current source _I0 and the positive poles of the current source _I1 are respectively connected to one end of the control switch S30 and one end of the control switch S40, the other end of the control switch S30 is connected to one end of the charge and discharge capacitor C10 and the non-inverting input end of the comparator CMP1, the other end of the charge and discharge capacitor C10 is grounded, and the other end of the control switch S40 is connected to the charge and discharge capacitor C20 One end is connected to the non-inverting input end of the comparator CMP2, the other end of the charging and discharging capacitor C20 is grounded, the inverting input end of the comparator CMP1 is connected to the inverting input end of the comparator CMP2 and connected to the reference level V _X +V _ref , and the comparison The output terminal of the comparator CMP1 and the output terminal of the comparator CMP2 are respectively connected to the setting input terminal S and the reset input terminal R of the RS flip-flop RS1;

The first capacitor pre-charging circuit includes control switches S10, S50, two input AND gates AND1, a pulse generation circuit and a charge and discharge control circuit, wherein the charge and discharge control circuit includes comparators CMP3, CMP4, RS flip-flop RS2 and a reference level V _X , V _M , the inverting input terminal of the comparator CMP3 is connected to the reference level V _X , the non-inverting input terminal of the comparator CMP4 is connected to the reference level V _M , the non-inverting input terminal of the comparator CMP3 is connected to the inverting input terminal of the comparator CMP4 Interconnect and connect together with one end of the control switch S50, one end of the control switch S10 and the other end of the control switch S30 in the oscillation circuit, the other end of the control switch S10 is connected to the positive pole of the current source _I0 in the oscillation circuit, and the control switch S50 The other end is grounded, the control end of the control switch S50 is connected to the output signal of the pulse generating circuit, the input end of the pulse generating circuit is connected to the output end Q1 of the RS flip-flop RS1 in the oscillation circuit, the output end of the comparator CMP3 and the output end of the comparator CMP4 Connect the set input terminal S and reset input terminal R of the RS flip-flop RS2 respectively, the output terminal Q2 of the RS flip-flop RS2 is connected to one input terminal of the two-input AND gate AND1, and the other input terminal of the two-input AND gate AND1 is connected to the oscillator circuit The output terminal of RS flip-flop RS1 in the The output terminal of the two-input AND gate AND1 is connected to the control terminal of the control switch S30 in the oscillation circuit, and the output terminal of the RS flip-flop RS2 Connect the control end of the control switch S10;

The structure of the second capacitor pre-charging circuit is the same as that of the first capacitor pre-charging circuit, including control switches S20, S60, two input AND gates AND2, pulse generation circuit and charge and discharge control circuit, wherein the charge and discharge control circuit includes comparators CMP5, CMP6 and RS flip-flop RS3 and reference levels V _X , V _M , the inverting input terminal of comparator CMP5 is connected to reference level V _X , the non-inverting input terminal of comparator CMP6 is connected to reference level V _M , and the non-inverting input terminal of comparator CMP5 is connected to reference level V M . The input terminal is interconnected with the inverting input terminal of the comparator CMP6 and is connected together with one end of the control switch S60, one end of the control switch S20 and the other end of the control switch S40 in the oscillation circuit, and the other end of the control switch S20 is connected in the oscillation circuit The positive pole of the current source _I1 , the other end of the control switch S60 is grounded, the control end of the control switch S60 is connected to the output signal of the pulse generating circuit, and the input end of the pulse generating circuit is connected to the output end of the RS flip-flop RS1 in the oscillation circuit The output end of the comparator CMP5 and the output end of the comparator CMP6 are respectively connected to the setting input end S and the reset input end R of the RS flip-flop RS3, and the output end Q3 of the RS flip-flop RS3 is connected to an input end of the two-input AND gate AND2, The other input end of the two-input AND gate AND2 is connected to the output end Q1 of the RS flip-flop RS1 in the oscillation circuit, the output end of the two-input AND gate AND2 is connected to the control end of the control switch S40 in the oscillation circuit, and the output end of the RS flip-flop RS3 Connect the control end of the control switch S20;

The above circuit controls the control switches S10 and S20 to precharge the charge and discharge capacitors C10 and C20 by detecting the voltage on the charge and discharge capacitors C10 and C20 through the charge and discharge control circuit in the two capacitor precharge circuits, and then controls the switches S30 and S40 to The charging and discharging capacitors C10 and C20 are charged, and the narrow pulse output generated by the pulse generating circuit is used to discharge the charging and discharging capacitors C10 and C20, and the temperature, imbalance and power generated during the two charging processes of the charging and discharging capacitors C10 and C20 are used The error delay affected by the voltage factor is offset to realize a high-precision self-adaptive relaxation oscillator.

The structures of the charging and discharging capacitors C10 and C20 are identical to the capacitance values; the structures of the comparators CMP1, CMP2, CMP3, CMP4, CMP5, and CMP6 are identical; the structures of the RS flip-flops RS1, RS2, and RS3 are identical; the two inputs and The gate AND1 and the two-input AND gate AND2 have exactly the same structure; the set reference level threshold voltage should satisfy V _M ≤ V _X +ΔV ≤ V _X +V _ref , where ΔV is the charge and discharge capacitance of flip-flops RS1, RS2 and RS3 Voltage overshoot generated on C10 and C20.

In the process of generating oscillation, the pulse width of the pulse generating circuit is not less than the time for the charge and discharge capacitors C10 and C20 to discharge from the level V _X + V _ref to V _M , and not greater than the time for the charge and discharge capacitors C10 and C20 to discharge from the level V _X + V The time when _ref discharges to zero potential avoids the excessively wide pulse width causing the control switch S50 and the control switch S60 to remain open during the charging and discharging process of the capacitors C10 and C20, resulting in abnormal operation of the oscillator.

The pulse generating circuits in the first and second capacitor precharging circuits include PMOS transistors MP1-MP6, NMOS transistors MN1-MN6, capacitors C _P and resistors R _P , and the sources of the PMOS transistors MP1-MP6 are all connected to the power supply VCC, the sources of NMOS transistors MN1~MN3, the sources of NMOS transistors MN5, MN6 and one end of capacitor C _P are all grounded, the gate of PMOS transistor MP1 is interconnected with the gate of NMOS transistor MN1 and used as the input of the pulse generating circuit terminal, the drain of the PMOS transistor MP1 is connected with the drain of the NMOS transistor MN1 and the gate of the PMOS transistor MP2 and the gate of the NMOS transistor MN2, and the drain of the PMOS transistor MP2 is interconnected with the drain of the NMOS transistor MN2 and One end of the resistance R _P is connected, the other end of the resistance R _P is connected with the other end of the capacitor C _P and the gate of the PMOS transistor MP3 and the gate of the NMOS transistor MN3 are connected together, and the drain of the PMOS transistor MP3 is connected with the gate of the NMOS transistor MN3 The drain is interconnected and connected together with the gate of the PMOS transistor MP4 and the gate of the NMOS transistor MN5, the drain of the PMOS transistor MP4 is connected with the drain of the PMOS transistor MP5, the drain of the NMOS transistor MN4 and the gate of the PMOS transistor MP6 The gate of the NMOS transistor MN6 is connected together, the gate of the PMOS transistor MP5 is interconnected with the gate of the NMOS transistor MN4 and is connected to the interconnection end of the gate of the PMOS transistor MP1 and the gate of the NMOS transistor MN1, and the gate of the NMOS transistor MN4 The source is connected to the drain of the NMOS transistor MN5, and the drain of the PMOS transistor MP6 is interconnected with the drain of the NMOS transistor MN6 and used as the output end of the pulse generating circuit.

The circuit structure of the comparators CMP1-CMP6 includes PMOS transistors MP7-MP9 and NMOS transistors MN7-MN10, the sources of the PMOS transistors MP7-MP9 are all connected to the power supply VCC, and the gates of the PMOS transistors MP7 and PMOS transistors MP8 are interconnected. Connect and connect the drain of the PMOS transistor MP7 and the drain of the NMOS transistor MN7, the source of the NMOS transistor MN7 is interconnected with the source of the NMOS transistor MN8 and connected to the drain of the NMOS transistor MN9, the gate of the NMOS transistor MN9 is connected to the NMOS transistor The gates of MN10 are interconnected and connected to the bias voltage V _BIAS , the source of the NMOS transistor MN9 and the source of the NMOS transistor MN10 are both grounded, and the drain of the NMOS transistor MN10 is interconnected with the drain of the PMOS transistor MP9 as a comparator At the output end, the gate of the NMOS transistor MN8 is the non-inverting input end of the comparator, and the gate of the NMOS transistor MN7 is the inverting input end of the comparator.

The circuit structure of the RS flip-flops RS1-RS3 includes PMOS transistors MP10-MP13 and NMOS transistors MN11-MN14, the source of the PMOS transistor MP10 and the source of the PMOS transistor MP12 are connected to the source VCC, and the drain of the PMOS transistor MP10 is connected to the PMOS transistor. The source of the transistor MP11, the drain of the PMOS transistor MP12 are connected to the source of the PMOS transistor MP13, the sources of the NMOS transistors MN11~MN14 are all grounded, and the gate of the NMOS transistor MN11 is interconnected with the gate of the PMOS transistor MP10 and used as an RS trigger The set input terminal S of the device, the gate of the NMOS transistor MN14 is interconnected with the gate of the PMOS transistor MP13 and used as the reset input terminal R of the RS flip-flop, the gate of the NMOS transistor MN12 is interconnected with the gate of the PMOS transistor MP11 and The drain of the NMOS transistor MN14, the drain of the NMOS transistor MN13 and the drain of the PMOS transistor MP13 are connected together as the output terminal Q of the RS flip-flop, and the drain of the NMOS transistor MN12 is connected to the drain of the PMOS transistor MP11. The electrodes are interconnected and connected together with the drain of the NMOS transistor MN11, the gate of the NMOS transistor MN13 and the gate of the PMOS transistor MP12 as the output terminal Q of the RS flip-flop.

Compared with prior art, advantage and beneficial effect of the present invention are:

(1) The high-precision adaptive relaxation oscillator of the present invention precharges the charging and discharging capacitors C10 and C20, and the delay of the control circuit caused by charging can be offset by charging twice, so that the oscillator frequency has a high Accuracy and frequency-control current linearity.

(2) The high-precision self-adaptive relaxation oscillator of the present invention has self-adaptability under the change of the external environment of the circuit, because the time delay of the control circuit will change with the change of temperature, offset and power supply voltage, the present invention is not directly The delay is reduced by increasing the speed of the comparator or RS flip-flop, but the influence of the delay generated by the control circuit and the offset that changes with the external environment is offset by the two charging processes, which significantly improves the accuracy of the oscillator, and It has strong temperature stability and power supply voltage suppression, that is, adaptability.

(3) The start-up time of the high-precision adaptive relaxation oscillator of the present invention is very short, and a stable oscillator frequency signal can be output after one oscillation cycle.

(4) The high-precision self-adaptive relaxation oscillator of the present invention has a large amplitude, which can be close to the ground potential to close to the power supply voltage, thereby reducing the impact of jitter on the oscillator period.

Description of drawings

FIG. 1 is a current-controlled relaxation oscillator based on a single grounded timing capacitor in the prior art;

Fig. 2 is the voltage waveform on the charging and discharging capacitor C in Fig. 1;

Fig. 3 is a graph of the effect of propagation delay in the frequency-controlled current relationship in the relaxation oscillator of Fig. 1;

FIG. 4 is a prior art current-controlled relaxation oscillator with dual grounded timing capacitors;

Figure 5 is the charging and discharging capacitors C1, C2 and the oscillator output Q and the waveform;

Fig. 6 is the relaxation oscillator with reference level automatic adjustment in the prior art;

Fig. 7 is the waveform of charging and discharging capacitor C1 and oscillator output Q in Fig. 6;

Fig. 8 is a relaxation oscillator with an error delay detection circuit in the prior art;

Fig. 9 is the waveform of charging and discharging capacitor C1 and oscillator output Q in Fig. 6;

Fig. 10 is a basic structural block diagram of the high-precision self-adaptive relaxation oscillator of the present invention;

Fig. 11 is the waveform change on the charging and discharging capacitor C10 after the high-precision adaptive relaxation oscillator of the present invention is powered on;

Fig. 12 is a working flow diagram of the high-precision self-adaptive relaxation oscillator of the present invention;

Fig. 13 is the waveform of the high precision adaptive relaxation oscillator control switches S10, S20, S30, S40, charge and discharge capacitors C10, C20 and oscillator output Q of the present invention;

Fig. 14 is a kind of implementation circuit diagram of the self-adaptive relaxation oscillator of high precision of the present invention;

Fig. 15 is the implementation circuit diagram of the pulse generating circuit adopted by the high precision adaptive relaxation oscillator of the present invention;

Fig. 16 is the implementation circuit of the comparator adopted by the high precision adaptive relaxation oscillator of the present invention;

FIG. 17 is an implementation circuit of the RS flip-flop used in the high-precision adaptive relaxation oscillator of the present invention.

detailed description

The principles and features of the present invention will be described below in conjunction with the accompanying drawings, and the examples given are only used to explain the present invention, and are not intended to limit the scope of the present invention.

Referring to FIG. 10 and FIG. 14 , the present invention adds a first capacitor precharging circuit 2 and a second capacitor precharging circuit 3 capable of precharging the charge and discharge capacitors on the basis of the oscillator circuit 1 . The oscillation circuit 1 , the first capacitor pre-charging circuit 2 and the second capacitor pre-charging circuit 3 all include charge and discharge control circuits with the same structure.

Oscillation circuit 1 includes current sources I ₀ , I ₁ , control switches S30 , S40 , charge and discharge capacitors C10 , C20 , comparators CMP1 , CMP2 , RS flip-flop RS1 and reference level V _X +V _ref , wherein comparators CMP1 , CMP2 and RS flip-flop RS1 form a charge and discharge control circuit. The negative pole of the current source _I0 is connected to the power supply VDD, the positive pole is connected to the control switches S10 and S30, the other end of the control switch S30 is connected to one end of the charge and discharge capacitor C10 and the non-inverting input end of the comparator CMP1, the other end of the charge and discharge capacitor C10 is grounded, and the current The negative pole of the source _I1 is connected to the power supply VDD, the positive pole is connected to the control switches S20 and S40, the other end of the control switch S40 is connected to one end of the charge and discharge capacitor C20 and the non-inverting input end of the comparator CMP2, the other end of the charge and discharge capacitor C20 is grounded, and the comparator The inverting input terminals of CMP1 and CMP2 are interconnected and connected to the reference level V _X +V _ref , the output terminal of CMP1 is connected to the set input terminal S of RS flip-flop RS1, and the output terminal of CMP2 is connected to the reset input terminal of RS flip-flop RS1 R.

The first capacitor pre-charging circuit 2 includes control switches S10, S50, a pulse generating circuit, a charge-discharge control circuit composed of two-input AND gate AND1, comparators CMP3, _CMP4 , RS flip-flop RS2 and reference levels V _X , VM. One end of the control switch S10 is connected to the positive pole of the current source _I0 , the other end of the control switch S10 is connected to one end of the charging and discharging capacitor C10, one end of the control switch S50, the non-inverting input end of the comparator CMP3 and the inverting input end of the comparator CMP4, The other end of the control switch S50 is grounded, the inverting input terminal of the comparator CMP3 is connected to the reference level V _X , the non-inverting input terminal of the comparator CMP4 is connected to the reference level V _M , the output terminal of the comparator CMP3 is connected to the setting of the RS flip-flop RS2 The bit input terminal S, the output terminal of the comparator CMP4 is connected to the reset input terminal R of the RS flip-flop RS2, and the output of the RS flip-flop RS2 The high level can directly close the control switch S10, and output Q2 and RS flip-flop RS1 They are respectively connected to the two input ends of the two-input AND gate AND1, and the high level of the output end of the two-input AND gate AND1 can directly close the control switch S30.

The second capacitor pre-charging circuit 3 is identical in structure to the first capacitor pre-charging circuit 2, including control switches S20, S60, a pulse generating circuit, two input AND gates AND2, comparators CMP5, CMP6 and RS flip-flop RS3 and reference level V Capacitor pre-charging control circuit composed of _X and V _M. One end of the control switch S20 is connected to the positive pole of the current source _I1 , the other end of the control switch S20 is connected to one end of the charging and discharging capacitor C20, one end of the control switch S60, the non-inverting input end of the comparator CMP5 and the inverting input end of the comparator CMP6, The other end of the control switch S60 is grounded, the inverting input terminal of the comparator CMP5 is connected to the reference level V _X , the non-inverting input terminal of the comparator CMP6 is connected to the reference level V _M , the output terminal of the comparator CMP5 is connected to the setting of the RS flip-flop RS3 The bit input terminal S, the output terminal of the comparator CMP6 is connected to the reset input terminal R of the RS flip-flop RS3, and the output of the RS flip-flop RS3 The high level can directly close the control switch S20, the output Q3 and the Q1 of the RS flip-flop RS1 are respectively connected to the two input terminals of the two-input AND gate AND2, and the high level of the output terminal of the two-input AND gate AND2 can directly make the control switch S40 closed.

The structure and capacitance value of the above-mentioned charging and discharging capacitor C10 and charging and discharging capacitor C20 are exactly the same, the structure and current value of the current source _I0 and the current source _I1 are exactly the same, and the circuit structure of the comparators CMP1, CMP2, CMP3, CMP4, CMP5 and CMP6 They are exactly the same, the RS flip-flops RS1, RS2 and RS3 are the same, the two-input AND gates AND1, AND2 have the same circuit structure, and the pulse generating circuits in the two capacitor precharging circuits have the same structure.

As shown in Figure 10, when the initial state is set, the output terminal Q1 of the RS flip-flop RS1 is at a low level, the capacitor pre-charge control circuit controls the control switch S10 to open, S50 is turned off, the current source _I0 charges the charge and discharge capacitor C10, and the capacitor The pre-charging control circuit controls the control switch S20 to turn on, S60 to turn off, and the current source _I1 charges the charge and discharge capacitor C20. When the potential on the charge and discharge capacitor C10 rises above the reference level V _X , the control switch S10 is turned off, and the control The switch S30 is turned on, the current source _I0 continues to charge the charging and discharging capacitor C10, and at the same time the control switch S20 is turned off, the control switch S60 is turned off, the current source _I1 stops charging the charging and discharging capacitor C20, and the voltage across the charging and discharging capacitor remains unchanged , when the potential on the charging and discharging capacitor C10 rises above the reference level V _X +V _ref , the control switch S10 and the control switch S30 are turned off, the control switch S50 is turned on under a pulse generated by the pulse generating circuit, and the charging and discharging capacitor C10 The discharge starts, and at the same time, the control switch S40 is turned on, the control switch S60 is turned off, and the current source _I1 continues to charge the charging and discharging capacitor C20. When the potential on the charging and discharging capacitor C20 rises to exceed the reference level V _X +V _ref , When the potential on the charge and discharge capacitor C10 drops below the reference level V _M , the control switch S10 is turned on, and the control switch S50 is turned off after the pulse width, and the current source _I0 charges the charge and discharge capacitor C10. When the charge and discharge capacitor C10 When the potential of the charging and discharging capacitor C20 rises above the reference level V _X , the control switch S10 is turned off, and the potential on the charging and discharging capacitor C10 remains unchanged. When the potential on the charging and discharging capacitor C20 rises above the reference level V _X +V _ref The control switch S30 is turned on, and the current source I ₀ charges the charge and discharge capacitor C10. At the same time, the control switch S60 is turned on under a pulse generated by the pulse generating circuit, and the charge and discharge capacitor C20 starts to discharge. This cycle repeats to generate an oscillating waveform. The above working process is as follows: Figure 12 shows.

After adding the charging and discharging capacitor pre-charging circuit in the present invention, the waveform changes on the charging and discharging capacitor C10 are shown in FIG. 11 . During the oscillation process, the pulse width of the pulse generating circuit should be designed to satisfy: the pulse width is not less than the time for the charge and discharge capacitors C10 and C20 to discharge from the level V _X + V _ref to V _M , and not greater than the time for the charge and discharge capacitors C10 and C20 to discharge from the level V X + V ref to V M . The time when the level V _X +V _ref is discharged to zero potential prevents the control switch S50 and the control switch S60 from being turned on during the charging process of the charging and discharging capacitors C10 and C20 due to too wide pulse width, resulting in abnormal operation of the oscillator.

The discharge time marked in Figure 13 is the pulse width of the pulse generating circuit. The period of the relaxation oscillator is twice the charging time of the charging and discharging capacitors C10 and C20 from pre-charging to exceeding the reference level V _X when the potential starts to charge to exceeding the reference level V _X +V _ref , and the charging and discharging capacitors C10 and C20 charge After reaching the reference level V _X or V _X +V _ref , the overcharge due to the delay of the control circuit is offset in the same environment, and the offset includes the offset effect of the circuit, etc., thus ensuring that the relaxation oscillator has high precision and Frequency - Controls current linearity.

As shown in Figure 11(a), when the reference level is V _ref , before the capacitor precharge circuit is added, when the oscillator starts to power on, due to the influence of the circuit delay td (td and temperature T, offset OS and power supply voltage VDD and so on are all related, which can be expressed as td(T, OS, VDD)), the voltage of capacitor C10 is overcharged during the rising process and rises to the initial peak voltage V _peak0 , the output of the oscillator (RS flip-flop output Q The frequency of the signal) is greater than the preset value; after adding the capacitor pre-charging circuit, the two charging processes of the charging and discharging capacitor will cause overcharging due to the delay of the circuit, because the structure and capacitance value of the charging and discharging capacitors C10 and C20 are exactly the same, and the current source The structure and current value of I ₀ and I ₁ are exactly the same, then in any environment of the oscillator, the influence of overcharge and offset due to circuit delay can be offset, and the relaxation oscillator has high precision and frequency- Control current linearity and adaptability not affected by external environment and imbalance.

The working process of Figure 14 is as follows:

1) Assume that the initial states of the output terminals Q1, Q2 and Q3 of the RS flip-flop are all low, the capacitors C10 and C20 are equal in size and both are C and the initial voltage is 0, and the current sources I ₀ and I ₁ are both I _REF , the threshold voltage of the comparator V _X +V _ref >V _X >V _M ;

2) At the beginning, the switches S10 and S20 are closed, and S30, S40, S50 and S60 are disconnected. The current source I ₀ and the current source I ₁ charge the capacitors C10 and C20 respectively. When the capacitors C10 and C20 are charged to V _X , Q2 and The output level of Q3 jumps and outputs a high level, and the charging time

In the formula, C is the same capacitance value of capacitors C10 and C20, I _REF is the value of charging current I ₀ and I ₁ , td(T, OS, VDD) is related to temperature T, offset OS and power supply voltage VDD, etc. circuit delay.

3) After Q2 and Q3 output high level, the switches S10, S20, S40, S50 and S60 are disconnected, S30 is closed, the voltage across the capacitor C20 keeps V _X unchanged, the current source _I0 continues to charge the capacitor C10, and the capacitor C10 When charging to V _X +V _ref , the level of Q1 jumps and outputs a high level, and the charging time

In the formula, C is the same capacitance value of capacitors C10 and C20, I _REF is the value of charging current I ₀ and I ₁ , td(T, OS, VDD) is related to temperature T, offset OS and power supply voltage VDD, etc. circuit delay.

4) After Q1 outputs a high level, the switches S10, S20, S30 and S60 are disconnected, S40 and S50 are closed, the current source I ₁ charges the capacitor C20, and the capacitor C10 discharges. When the capacitor C10 is discharged to V _M , the output level of Q2 A transition occurs and outputs a low level;

5) After Q2 outputs a low level, switch S10 is closed, S50 is turned off, current source I ₀ charges capacitor C10, and after capacitor C10 is charged to V _X , the output level of Q2 jumps and outputs high level;

6) After Q2 outputs a high level, the switch S10 is turned off. At this time, the voltage on the capacitor C10 keeps V _X unchanged. When the capacitor C20 is charged to V _X +V _ref , the output level of Q1 jumps and outputs a low level , charging time

In the formula, C is the same capacitance value of capacitors C10 and C20, I _REF is the value of charging current I ₀ and I ₁ , td(T, OS, VDD) is related to temperature T, offset OS and power supply voltage VDD, etc. circuit delay.

7) After the output level of Q1 becomes low level, S40 is disconnected, S30 is closed, the current source I ₀ charges the capacitor C10, and the capacitor C20 discharges. When the capacitor C20 is discharged to V _M , the output level of Q3 jumps and outputs high level;

8) After Q3 outputs a high level, the switch S60 is disconnected after the pulse ends, S20 is closed, the current source I ₁ charges the capacitor C20, and after the capacitor C20 is charged to V _X , the output level of Q3 jumps and outputs a low level;

9) After Q3 outputs a low level, the switch S20 is turned off. At this time, the voltage on the capacitor C20 keeps V _X unchanged. When the capacitor C10 is charged to V _X +V _ref , the output level of Q1 jumps and outputs a high level , charging time

In the formula, C is the same capacitance value of capacitors C10 and C20, I _REF is the value of charging current I ₀ and I ₁ , td(T, OS, VDD) is related to temperature T, offset OS and power supply voltage VDD, etc. circuit delay.

10) Repeat the working process from step 4 to step 9 above to form an oscillation.

Assuming that the voltage overshoot generated on the capacitor due to the delay of the control circuit RS trigger is ΔV, then if the circuit works normally, the set reference level (threshold voltage) should satisfy the following relationship

V _M ≤ V _X +ΔV ≤ V _X +V _ref Formula 8

According to the working principle of the circuit, referring to Figure 13 for the working process of the circuit, it can be seen that the cycle of the capacitor pre-charging circuit depends on the time for the capacitors C10 and C20 to charge from the voltage V _X + ΔV to the voltage V _X + V _ref + ΔV, and the cycle is

Wherein, C is the same capacitance value of the capacitors C10 and C20, and I _REF is the value of the charging current I ₀ and I ₁ .

The frequency of the oscillator is

Wherein, C is the same capacitance value of the capacitors C10 and C20, and I _REF is the value of the charging current I ₀ and I ₁ .

FIG. 15 is an implementation circuit of the pulse generating circuit used in the high-precision adaptive relaxation oscillator of the present invention. In this embodiment, the output of RS1 is used to pass through the pulse generating circuit, and a narrow pulse signal is generated at the rising edge of the input signal to control the closing of the switches S50 and S60, so that the potentials on the charging and discharging capacitors C10 and C20 can be discharged to V _M , where The pulse width can be calculated and determined by the discharge voltage and capacitance on the charging and discharging capacitor, and the pulse width is shown in the waveform diagram as shown in Figure 13.

FIG. 16 is an implementation circuit of a comparator used in the high-precision adaptive relaxation oscillator of the present invention. MP7, MP8, MN7, MN8, and MN9 form a five-tube differential input stage, and MP9 and MN10 form a two-stage open-loop operational amplifier for the second gain stage as a comparator, so that the comparator can compare the two input voltages and output a high level or low level.

FIG. 17 is an implementation circuit of the RS flip-flop used in the high-precision adaptive relaxation oscillator of the present invention. In an embodiment, the RS flip-flop is based on two NAND gates.

In the shown embodiments, other modifications and combinations are possible, and the invention is not limited to the few shown examples. Although the invention has been described above using particular embodiments, numerous modifications may be made by a person skilled in the art within the scope of the claims. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (6)

1. A high-precision self-adaptive relaxation oscillator is characterized in that: based on the oscillation circuit, two capacitor pre-charging circuits are added, and the delay caused by the charge-discharge control circuit produced in the oscillator circuit is offset by utilizing the capacitor pre-charging principle. When; including the oscillator circuit, the first capacitor pre-charging circuit and the second capacitor pre-charging circuit, the capacitor pre-charging circuit is used to pre-charge the oscillator charge and discharge capacitor, and the oscillator circuit is based on the pre-charging level of the capacitor pre-charging circuit. Charge and discharge, the error delay caused by the two charging of the capacitor is offset, so that the oscillator works at the preset frequency, and the frequency-control current linearity is significantly improved; among them: The oscillating circuit includes current sources I ₀ , I ₁ , control switches S30 , S40 , charge and discharge capacitors C10 , C20 , comparators CMP1 , CMP2 , RS flip-flop RS1 and a reference level V _X +V _ref , wherein the comparators CMP1 , CMP2 and RS flip-flop RS1 form a charge and discharge control circuit; the negative poles of the current source _I0 and the negative poles of the current source _I1 are connected to the power supply VDD, and the positive poles of the current source _I0 and the positive poles of the current source _I1 are respectively connected to one end of the control switch S30 and one end of the control switch S40, the other end of the control switch S30 is connected to one end of the charge and discharge capacitor C10 and the non-inverting input end of the comparator CMP1, the other end of the charge and discharge capacitor C10 is grounded, and the other end of the control switch S40 is connected to the charge and discharge capacitor C20 One end is connected to the non-inverting input end of the comparator CMP2, the other end of the charging and discharging capacitor C20 is grounded, the inverting input end of the comparator CMP1 is connected to the inverting input end of the comparator CMP2 and connected to the reference level V _X +V _ref , and the comparison The output terminal of the comparator CMP1 and the output terminal of the comparator CMP2 are respectively connected to the setting input terminal S and the reset input terminal R of the RS flip-flop RS1; The first capacitor pre-charging circuit includes control switches S10, S50, two input AND gates AND1, a pulse generation circuit and a charge and discharge control circuit, wherein the charge and discharge control circuit includes comparators CMP3, CMP4, RS flip-flop RS2 and a reference level V _X , V _M , the inverting input terminal of the comparator CMP3 is connected to the reference level V _X , the non-inverting input terminal of the comparator CMP4 is connected to the reference level V _M , the non-inverting input terminal of the comparator CMP3 is connected to the inverting input terminal of the comparator CMP4 Interconnect and connect together with one end of the control switch S50, one end of the control switch S10 and the other end of the control switch S30 in the oscillation circuit, the other end of the control switch S10 is connected to the positive pole of the current source _I0 in the oscillation circuit, and the control switch S50 The other end is grounded, the control end of the control switch S50 is connected to the output signal of the pulse generating circuit, the input end of the pulse generating circuit is connected to the output end Q1 of the RS flip-flop RS1 in the oscillation circuit, the output end of the comparator CMP3 and the output end of the comparator CMP4 Connect the set input terminal S and reset input terminal R of the RS flip-flop RS2 respectively, the output terminal Q2 of the RS flip-flop RS2 is connected to one input terminal of the two-input AND gate AND1, and the other input terminal of the two-input AND gate AND1 is connected to the oscillator circuit The output terminal of RS flip-flop RS1 in the The output terminal of the two-input AND gate AND1 is connected to the control terminal of the control switch S30 in the oscillation circuit, and the output terminal of the RS flip-flop RS2 Connect the control end of the control switch S10; The structure of the second capacitor pre-charging circuit is the same as that of the first capacitor pre-charging circuit, including control switches S20, S60, two input AND gates AND2, pulse generation circuit and charge and discharge control circuit, wherein the charge and discharge control circuit includes comparators CMP5, CMP6 and RS flip-flop RS3 and reference levels V _X , V _M , the inverting input terminal of comparator CMP5 is connected to reference level V _X , the non-inverting input terminal of comparator CMP6 is connected to reference level V _M , and the non-inverting input terminal of comparator CMP5 is connected to reference level V M . The input terminal is interconnected with the inverting input terminal of the comparator CMP6 and is connected together with one end of the control switch S60, one end of the control switch S20 and the other end of the control switch S40 in the oscillation circuit, and the other end of the control switch S20 is connected in the oscillation circuit The positive pole of the current source _I1 , the other end of the control switch S60 is grounded, the control end of the control switch S60 is connected to the output signal of the pulse generating circuit, and the input end of the pulse generating circuit is connected to the output end of the RS flip-flop RS1 in the oscillation circuit The output end of the comparator CMP5 and the output end of the comparator CMP6 are respectively connected to the setting input end S and the reset input end R of the RS flip-flop RS3, and the output end Q3 of the RS flip-flop RS3 is connected to an input end of the two-input AND gate AND2, The other input end of the two-input AND gate AND2 is connected to the output end Q1 of the RS flip-flop RS1 in the oscillation circuit, the output end of the two-input AND gate AND2 is connected to the control end of the control switch S40 in the oscillation circuit, and the output end of the RS flip-flop RS3 Connect the control end of the control switch S20; The above circuit controls the control switches S10 and S20 to precharge the charge and discharge capacitors C10 and C20 by detecting the voltage on the charge and discharge capacitors C10 and C20 through the charge and discharge control circuit in the two capacitor precharge circuits, and then controls the switches S30 and S40 to The charging and discharging capacitors C10 and C20 are charged, and the narrow pulse output generated by the pulse generating circuit is used to discharge the charging and discharging capacitors C10 and C20, and the temperature, imbalance and power generated during the two charging processes of the charging and discharging capacitors C10 and C20 are used The error delay affected by the voltage factor is offset to realize a high-precision self-adaptive relaxation oscillator. 2. the relaxation oscillator of high precision self-adaptation according to claim 1, is characterized in that; The structure of described charging and discharging capacitor C10 and C20 is identical with capacitance value; Comparator CMP1, CMP2, CMP3, CMP4, CMP5 and The structures of CMP6 are identical; the structures of RS flip-flops RS1, RS2 and RS3 are identical; the structures of the two-input AND gate AND1 and the two-input AND gate AND2 are identical; the set reference level threshold voltage should satisfy V _M ≤ V _X + ΔV≤V _X +V _ref , where ΔV is the voltage overshoot generated by flip-flops RS1 , RS2 and RS3 on the charging and discharging capacitors C10 and C20 . 3. according to claim 1 or 2 described high-precision self-adaptive relaxation oscillators, it is characterized in that: in the process of generating oscillation, the pulse width of the pulse generating circuit is not less than the charge and discharge capacitor C10 and C20 from the level V _x +V The time for _ref to discharge to V _M is not longer than the time for charging and discharging capacitors C10 and C20 to discharge from the level V _X + V _ref to zero potential, so as to avoid the excessive pulse width causing the control switch S50 and control switch S60 to be in the charge and discharge capacitor C10 and C20 is still open during charging, causing the oscillator to work abnormally. 4. The high-precision self-adaptive relaxation oscillator according to claim 3, wherein the pulse generation circuits in the first and second capacitor pre-charging circuits include PMOS transistors MP1-MP6, NMOS transistors MN1 ~MN6, capacitor C _P and resistor R _P , the sources of the PMOS transistors MP1~MP6 are all connected to the power supply VCC, the sources of the NMOS transistors MN1~MN3, the sources of the NMOS transistors MN5, MN6 and one end of the capacitor C _P are all grounded, The gate of the PMOS transistor MP1 is interconnected with the gate of the NMOS transistor MN1 and used as the input end of the pulse generating circuit, the drain of the PMOS transistor MP1 is connected with the drain of the NMOS transistor MN1 and is connected with the gate of the PMOS transistor MP2 and the gate of the NMOS transistor MN2 The gates are connected together, the drain of the PMOS transistor MP2 is interconnected with the drain of the NMOS transistor MN2 and connected to one end of the resistor R _P , and the other end of the resistor R _P is connected to the other end of the capacitor C _P and the gate of the PMOS transistor MP3 The gate of the NMOS transistor MN3 is connected together, the drain of the PMOS transistor MP3 is interconnected with the drain of the NMOS transistor MN3 and is connected with the gate of the PMOS transistor MP4 and the gate of the NMOS transistor MN5, and the drain of the PMOS transistor MP4 The drain of the PMOS transistor MP5, the drain of the NMOS transistor MN4, the gate of the PMOS transistor MP6, and the gate of the NMOS transistor MN6 are connected together, and the gate of the PMOS transistor MP5 is interconnected and connected to the gate of the NMOS transistor MN4. The gate of the PMOS transistor MP1 is interconnected with the gate of the NMOS transistor MN1, the source of the NMOS transistor MN4 is connected to the drain of the NMOS transistor MN5, and the drain of the PMOS transistor MP6 is interconnected with the drain of the NMOS transistor MN6 as a pulse generate the output of the circuit. 5. The high-precision self-adaptive relaxation oscillator according to claim 2, characterized in that: the circuit structure of the comparators CMP1-CMP6 includes PMOS transistors MP7-MP9 and NMOS transistors MN7-MN10, PMOS transistors MP7-MP9 The source electrodes of the PMOS transistor MP7 are connected to the power supply VCC, the gate of the PMOS transistor MP7 is interconnected with the gate of the PMOS transistor MP8 and connected to the drain of the PMOS transistor MP7 and the drain of the NMOS transistor MN7, and the source of the NMOS transistor MN7 is connected to that of the NMOS transistor MN8. The source is interconnected and connected to the drain of the NMOS transistor MN9, the gate of the NMOS transistor MN9 is interconnected with the gate of the NMOS transistor MN10 and connected to the bias voltage V _BIAS , the source of the NMOS transistor MN9 and the source of the NMOS transistor MN10 are both Grounded, the drain of the NMOS transistor MN10 is interconnected with the drain of the PMOS transistor MP9 and used as the output terminal of the comparator, the gate of the NMOS transistor MN8 is the non-inverting input terminal of the comparator, and the gate of the NMOS transistor MN7 is the inverting input terminal of the comparator end. 6. The high-precision self-adaptive relaxation oscillator according to claim 2, characterized in that: the circuit structure of the RS flip-flops RS1-RS3 includes PMOS transistors MP10-MP13 and NMOS transistors MN11-MN14, PMOS transistor MP10 Both the source and the source of the PMOS transistor MP12 are connected to the source VCC, the drain of the PMOS transistor MP10 is connected to the source of the PMOS transistor MP11, the drain of the PMOS transistor MP12 is connected to the source of the PMOS transistor MP13, and the sources of the NMOS transistors MN11-MN14 Both are grounded, the gate of the NMOS transistor MN11 is interconnected with the gate of the PMOS transistor MP10 and used as the set input terminal S of the RS flip-flop, and the gate of the NMOS transistor MN14 is interconnected with the gate of the PMOS transistor MP13 and used as the RS flip-flop The reset input terminal R of the NMOS transistor MN12 is interconnected with the gate of the PMOS transistor MP11 and connected with the drain of the NMOS transistor MN14, the drain of the NMOS transistor MN13, and the drain of the PMOS transistor MP13 together as an RS flip-flop As the output terminal Q of the RS flip-flop, the drain of the NMOS transistor MN12 is interconnected with the drain of the PMOS transistor MP11 and is connected together with the drain of the NMOS transistor MN11, the gate of the NMOS transistor MN13, and the gate of the PMOS transistor MP12. As the output of the RS flip-flop