CN106973351B - Micro feedback cavity sensor and manufacturing method thereof - Google Patents
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Abstract
一种微型回馈腔传感器包括:一个半导体基底,具有一感测电路;一接合结构层,位于半导体基底上;以及一感测元芯片,具有一低阻值的半导体本体、一第一端部及一第二端部,半导体本体中形成有多个导电柱,第一端部形成有感测元结构,第二端部通过接合结构层连接至半导体基底,感测元结构、半导体基底与半导体本体之间形成一回馈腔体结构,感测元结构通过此些导电柱以电连接至感测电路。感测元结构与回馈腔体结构共同反应一外界输入的物理信号而产生一感测信号输出至感测电路。一种微型回馈腔传感器的制造方法也一并提供。
A miniature feedback cavity sensor includes: a semiconductor substrate having a sensing circuit; a bonding structure layer located on the semiconductor substrate; and a sensing element chip having a semiconductor body with a low resistance, a first end, and a second end, wherein a plurality of conductive pillars are formed in the semiconductor body, a sensing element structure is formed at the first end, and the second end is connected to the semiconductor substrate through the bonding structure layer, and a feedback cavity structure is formed between the sensing element structure, the semiconductor substrate, and the semiconductor body, and the sensing element structure is electrically connected to the sensing circuit through these conductive pillars. The sensing element structure and the feedback cavity structure jointly react to a physical signal input from the outside to generate a sensing signal output to the sensing circuit. A manufacturing method of a miniature feedback cavity sensor is also provided.
Description
技术领域technical field
本发明涉及一种微型回馈腔传感器及其制造方法,且特别涉及一种用于声波及/或压力的微型回馈腔传感器及其制造方法。The present invention relates to a micro feedback cavity sensor and a manufacturing method thereof, and particularly relates to a micro feedback cavity sensor for acoustic waves and/or pressure and a manufacturing method thereof.
背景技术Background technique
压电式(Piezoelectric)、压阻式(Piezoresistive)与电容式(Capacitive)是目前常见的微型传感器技术。压电式传感器是利用压电材料在受外力干扰后会输出电流或电压的特性,将输入物理信号转换成电信号,而压阻式传感器是利用压阻材料在受力之后电阻特性发生改变。而一种最常见的感测方式则是电容式,其具有容易制造、高感度及低功耗等优良特性,是目前市场发展的主流。Piezoelectric, Piezoresistive and Capacitive are the common micro-sensor technologies. Piezoelectric sensors use the characteristics of piezoelectric materials to output current or voltage after being disturbed by external forces, and convert input physical signals into electrical signals, while piezoresistive sensors use piezoresistive materials to change the resistance characteristics after being stressed. One of the most common sensing methods is capacitive, which has excellent characteristics such as easy manufacturing, high sensitivity and low power consumption, and is currently the mainstream of market development.
特别是一种具有回馈腔体设计的传感器,例如微型压力传感器以及微型麦克风,例如密闭真空回馈腔体的压力传感器,通过与外界的压力差产生结构变形(产生压电、压阻或与电容的物理量)。再例如微型麦克风,需要一声学回馈腔,以反映接收到的声学信号。因此对这种具有回馈腔体设计的传感器,一个重要的传感器品质是来自所述回馈腔体的体积,例如对压力传感器,回馈腔体内部在制造时设计维持于一低压的状态(也即接近高真空状态),但是由于制造完成后回馈腔体的器壁的放气(outgassing)效应仍会存在有一些气体,所述残留气体会因热涨冷缩原理,而对量测造成影响。已知理想气体方程式为pV=nRT,其中p为理想气体的压力,V为理想气体的体积,n为气体物质的量,T为理想气体的热力学温度,R为理想气体常数。因此,如果设计上加大回馈腔体的体积,等于加大了V,则可以得到更低的p,所以温度效应造成的热涨冷缩对传感器的影响较低。In particular, a sensor with a feedback cavity design, such as a micro pressure sensor and a micro microphone, such as a pressure sensor with a closed vacuum feedback cavity, produces structural deformation (piezoelectric, piezoresistive or capacitive) through the pressure difference with the outside world. physical quantity). Another example is a miniature microphone, which needs an acoustic feedback cavity to reflect the received acoustic signal. Therefore, for such a sensor with a feedback cavity design, an important sensor quality is the volume from the feedback cavity. For example, for a pressure sensor, the interior of the feedback cavity is designed to maintain a low pressure state (that is, close to high vacuum state), but there will still be some gas due to the outgassing effect of the wall of the feedback cavity after the manufacturing is completed, and the residual gas will affect the measurement due to the principle of thermal expansion and contraction. The known ideal gas equation is pV=nRT, where p is the pressure of the ideal gas, V is the volume of the ideal gas, n is the amount of gas substance, T is the thermodynamic temperature of the ideal gas, and R is the ideal gas constant. Therefore, if the volume of the feedback cavity is increased in design, which is equivalent to increasing V, a lower p can be obtained, so the thermal expansion and contraction caused by the temperature effect have a lower impact on the sensor.
另外例如微型麦克风,其都是利用传统的封装技术完成。图14显示一种传统的微型麦克风的封装示意图。如图所示,在传统的微型麦克风的封装过程中,先将微机电感测芯片520与信号处理芯片530分开安装在封装基板510上,然后通过打线的方式将微机电感测芯片520与信号处理芯片530作电连接,接着在将盖体540罩覆住微机电感测芯片520与信号处理芯片530,以形成一个腔体。这种封装方式,只能采用芯片级的封装,无法采用晶圆级封装。微型麦克风的封装体结构在设计时,有下列重要项目须谨慎评估与考量。首先是前腔(Front Chamber)距离,是指声压进入入音孔后至到达传感器振膜前的空间距离(传统的距离为基板510厚度再加上微机电感测芯片520,其值至少>300um),太长的前腔距离会加大音阻,影响品质。因此,前腔距离应越小会较适当,当然,也可将前腔距离对应于前腔体积。Another example is miniature microphones, which are all completed using traditional packaging technology. FIG. 14 shows a schematic diagram of a package of a conventional miniature microphone. As shown in the figure, during the packaging process of the traditional miniature microphone, the microcomputer electrical sensing chip 520 and the signal processing chip 530 are firstly mounted on the packaging substrate 510 separately, and then the microcomputer electrical sensing chip 520 and the signal processing chip 520 are connected by wire bonding. The chip 530 is electrically connected, and then the cover 540 is covered to cover the microcomputer electrical sensing chip 520 and the signal processing chip 530 to form a cavity. In this packaging method, only chip-level packaging can be used, and wafer-level packaging cannot be used. When designing the package structure of the miniature microphone, the following important items must be carefully evaluated and considered. The first is the distance of the front chamber (Front Chamber), which refers to the spatial distance from the sound pressure entering the sound hole to the front of the sensor diaphragm (the traditional distance is the thickness of the substrate 510 plus the microcomputer electrical sensing chip 520, and its value is at least >300um ), too long front cavity distance will increase the sound resistance and affect the quality. Therefore, it is more appropriate that the distance of the anterior cavity should be smaller, and of course, the distance of the anterior cavity may also correspond to the volume of the anterior cavity.
其次,背腔(Back Chamber)体积相对于前腔体积,是指振膜与封装体内部所形成的密闭空间体积,也即为声音通过微机电振膜芯片后的密封体积。背腔越大时感度会越大,这是因为当背腔体积增大时,振膜受到来自背腔内空气的反作用力会愈小使感测信号不失真。因此,背腔体积应越大会较适当。另外,须特别注意的是,背腔内的空间必须完全受到密封(仅保留经由振膜连通至外界);若背腔未能妥善密封而与前腔空间相连通时,会使频响曲线在低频区段发生感度降低现象。在已知技术中,通常使用封装盖体(package lid)来将微机电芯片覆盖住,以提供庞大的背腔,然而,这种封装方式不适合芯片的整合,产出的微型麦克风的体积也相当庞大,且无法以晶圆级的制造方式大量生产。Secondly, the volume of the back chamber relative to the volume of the front chamber refers to the volume of the closed space formed by the diaphragm and the inside of the package, that is, the volume of the sealed space after the sound passes through the MEMS diaphragm chip. The larger the back cavity is, the greater the sensitivity will be, because when the volume of the back cavity increases, the reaction force of the diaphragm from the air in the back cavity will be smaller, so that the sensing signal will not be distorted. Therefore, the larger the volume of the back cavity would be more appropriate. In addition, it should be noted that the space in the back cavity must be completely sealed (only remaining connected to the outside world through the diaphragm); if the back cavity is not properly sealed and communicated with the front cavity space, the frequency response curve will be in the Sensitivity reduction occurs in the low frequency range. In the known technology, a package lid is usually used to cover the MEMS chip to provide a huge back cavity. However, this packaging method is not suitable for chip integration, and the volume of the produced micro microphone is also low. It is quite bulky and cannot be mass-produced in wafer-level manufacturing.
发明内容SUMMARY OF THE INVENTION
本发明的一个目的是提供一种微型回馈腔传感器及其制造方法,具芯片整合的优点,且能以晶圆级的制造方式进行大量生产,降低成本。An object of the present invention is to provide a micro feedback cavity sensor and a manufacturing method thereof, which have the advantages of chip integration, and can be mass-produced in a wafer-level manufacturing manner, thereby reducing costs.
本发明的另一目的是提供一种微型回馈腔传感器及其制造方法,此微型回馈腔传感器可以当作麦克风使用,且能提供庞大的背腔、微小的前腔来提高麦克风的感测效果。Another object of the present invention is to provide a micro feedback cavity sensor and a manufacturing method thereof. The micro feedback cavity sensor can be used as a microphone, and can provide a huge back cavity and a tiny front cavity to improve the sensing effect of the microphone.
本发明的又另一目的是提供一种微型回馈腔传感器及其制造方法,此微型回馈腔传感器可以当作压力传感器使用,且能提供庞大的腔体的容积、提高压力传感器的感测效果。Yet another object of the present invention is to provide a micro feedback cavity sensor and a manufacturing method thereof. The micro feedback cavity sensor can be used as a pressure sensor, and can provide a huge cavity volume and improve the sensing effect of the pressure sensor.
本发明的又另一目的是提供一种微型回馈腔传感器及其制造方法,此微型回馈腔传感器可以提供压力传感器及麦克风的功能。Yet another object of the present invention is to provide a micro feedback cavity sensor and a manufacturing method thereof. The micro feedback cavity sensor can provide the functions of a pressure sensor and a microphone.
为实现上述目的,本发明采取以下技术方案:To achieve the above object, the present invention adopts the following technical solutions:
本发明提供一种微型回馈腔传感器,包括:一个半导体基底,具有一感测电路;一接合结构层,位于该半导体基底上;以及一感测元芯片,具有一低阻值的半导体本体、一第一端部及一第二端部,该半导体本体中形成有多个导电柱,该第一端部形成有至少一感测元结构,该第二端部是通过接合结构层连接至该半导体基底,至少一感测元结构、半导体基底与半导体本体之间形成一回馈腔体结构,至少一感测元结构是通过此些导电柱以电连接至该感测电路。至少一感测元结构与该回馈腔体结构共同反应一外界输入的物理信号而产生一感测信号输出至该感测电路。The present invention provides a miniature feedback cavity sensor, comprising: a semiconductor substrate with a sensing circuit; a bonding structure layer on the semiconductor substrate; and a sensing element chip having a low-resistance semiconductor body, a A first end portion and a second end portion, a plurality of conductive pillars are formed in the semiconductor body, the first end portion is formed with at least one sensing element structure, and the second end portion is connected to the semiconductor through a bonding structure layer The substrate, at least one sensing element structure, a feedback cavity structure is formed between the semiconductor substrate and the semiconductor body, and the at least one sensing element structure is electrically connected to the sensing circuit through the conductive columns. At least one sensing element structure and the feedback cavity structure jointly respond to an externally input physical signal to generate a sensing signal and output it to the sensing circuit.
在上述微型回馈腔传感器中,该感测元芯片可以还包括一第一电性输出入结构,位于该回馈腔体结构的周围,该第一电性输出入结构具有多个第一连接垫,通过此些导电柱以电连接至该感测电路。In the above-mentioned micro feedback cavity sensor, the sensing element chip may further include a first electrical I/O structure located around the feedback cavity structure, and the first electrical I/O structure has a plurality of first connection pads, It is electrically connected to the sensing circuit through the conductive pillars.
上述微型传感器可以还包括:一电路板,设置于该第一电性输出入结构的上方,并电连接至此些第一连接垫。The above-mentioned micro sensor may further include: a circuit board disposed above the first electrical I/O structure and electrically connected to the first connection pads.
在上述微型回馈腔传感器中,该第一电性输出入结构可具有一导体连接层,该导体连接层的一上表面与该感测元结构的一上表面位于同一平面上。In the above-mentioned micro feedback cavity sensor, the first electrical I/O structure may have a conductor connection layer, and an upper surface of the conductor connection layer and an upper surface of the sensing element structure are located on the same plane.
上述微型回馈腔传感器可以还包括一遮蔽芯片,具有一低阻值的半导体本体、一第一端部以及一第二端部,该遮蔽芯片的第二端部连接至该感测元芯片的第一端部,以及去除部分遮蔽芯片的半导体本体以露出部分或全部的感测元结构而形成的一开放工作腔,该感测元结构感测经由该开放工作腔所接收的物理信号而产生感测信号。The above-mentioned micro feedback cavity sensor may further comprise a shielding chip having a low-resistance semiconductor body, a first end and a second end, and the second end of the shielding chip is connected to the first end of the sensing element chip. One end, and an open working cavity formed by removing part of the semiconductor body that shields the chip to expose part or all of the sensing element structure, the sensing element structure senses the physical signal received through the open working cavity to generate sensing measurement signal.
在上述微型回馈腔传感器中,该感测元芯片可以还包括一第一电性输出入结构,位于该回馈腔体结构的周围,该第一电性输出入结构具有多个第一连接垫,通过此些导电柱以电连接至该感测电路,该遮蔽芯片还包括一第二电性输出入结构,位于该开放工作腔的周围以及该第一电性输出入结构上,该第二电性输出入结构具有多个第二连接垫,分别电连接至此些第一连接垫。In the above-mentioned micro feedback cavity sensor, the sensing element chip may further include a first electrical I/O structure located around the feedback cavity structure, and the first electrical I/O structure has a plurality of first connection pads, The shielding chip further includes a second electrical I/O structure located around the open working cavity and on the first electrical I/O structure to be electrically connected to the sensing circuit through the conductive pillars. The I/O structure has a plurality of second connection pads, which are respectively electrically connected to the first connection pads.
上述微型回馈腔传感器可还包括:一电路板,设置于该遮蔽芯片的上方,并电连接至此些第二连接垫。The micro feedback cavity sensor may further include: a circuit board disposed above the shielding chip and electrically connected to the second connection pads.
在上述微型回馈腔传感器中,物理信号可以是通过电路板与此些第二连接垫之间的空隙进入该开放工作腔。In the above-mentioned micro feedback cavity sensor, the physical signal may enter the open working cavity through the gap between the circuit board and the second connection pads.
在上述微型回馈腔传感器中,该第二电性输出入结构可还包括:多个垂直导体,贯穿该遮蔽芯片而电连接至此些第二连接垫及此些第一连接垫。In the above-mentioned micro feedback cavity sensor, the second electrical I/O structure may further include: a plurality of vertical conductors passing through the shielding chip and electrically connected to the second connection pads and the first connection pads.
在上述微型回馈腔传感器中,该感测元结构可包括:一第一电极板,固定地设置于该半导体本体上,并具有多个孔洞;以及一第二电极板,可动地设置于该第一电极板的上方,该第一电极板与该第二电极板形成一感测电容,该第一电极板与该第二电极板之间形成有一间隙。In the above-mentioned micro feedback cavity sensor, the sensing element structure may include: a first electrode plate fixedly disposed on the semiconductor body and having a plurality of holes; and a second electrode plate movably disposed on the semiconductor body Above the first electrode plate, the first electrode plate and the second electrode plate form a sensing capacitor, and a gap is formed between the first electrode plate and the second electrode plate.
在上述微型回馈腔传感器中,该感测元结构可为一悬浮结构,感测一物理信号而变形,该悬浮结构包括:一第一电极板;一压电材料层,设置于该第一电极板上;以及一第二电极板,设置于该压电材料层上。In the above-mentioned micro feedback cavity sensor, the sensing element structure may be a floating structure, which is deformed by sensing a physical signal, and the floating structure includes: a first electrode plate; a piezoelectric material layer disposed on the first electrode plate; and a second electrode plate, disposed on the piezoelectric material layer.
在上述微型回馈腔传感器中,该半导体基底可包括:一第一硅基板,具有感测电路;一模塑料层,包围该第一硅基板的一个或多个侧面;以及一导体连接层,位于该第一硅基板及模塑料层上,并将该感测电路电连接至该感测元芯片。In the above-mentioned micro feedback cavity sensor, the semiconductor substrate may include: a first silicon substrate having a sensing circuit; a molding compound layer surrounding one or more side surfaces of the first silicon substrate; and a conductor connection layer located on the On the first silicon substrate and the molding compound layer, the sensing circuit is electrically connected to the sensing element chip.
在上述微型回馈腔传感器中,该遮蔽芯片可包括一外露导体层,电连接至一固定电位。In the above-mentioned micro feedback cavity sensor, the shielding chip may include an exposed conductor layer electrically connected to a fixed potential.
在上述微型回馈腔传感器中,该遮蔽芯片包括一外露导体层,该整合式导体层位于该遮蔽芯片的该半导体本体上,且更贯穿该遮蔽芯片的该半导体本体及该感测元芯片的一部分,而电连接至该感测元芯片的一电性输出入结构,以电连接至该感测电路。In the above-mentioned micro feedback cavity sensor, the shielding chip includes an exposed conductor layer, the integrated conductor layer is located on the semiconductor body of the shielding chip, and further penetrates the semiconductor body of the shielding chip and a part of the sensing element chip , and is electrically connected to an electrical I/O structure of the sensing element chip, so as to be electrically connected to the sensing circuit.
上述微型回馈腔传感器可还包括一电路板,设置于该遮蔽芯片的上方,并电连接至该遮蔽芯片上的多个连接垫,其中该物理信号是通过该电路板与该多个连接垫之间的空隙进入该开放工作腔。The above-mentioned micro feedback cavity sensor may further include a circuit board disposed above the shielding chip and electrically connected to a plurality of connection pads on the shielding chip, wherein the physical signal is passed through the circuit board and the plurality of connection pads. into the open working chamber.
上述微型回馈腔传感器可还包括一电路板,设置于该半导体基底的下方,并电连接至该半导体基底的一下表面上的多个连接垫。The above-mentioned micro feedback cavity sensor may further include a circuit board disposed under the semiconductor substrate and electrically connected to a plurality of connection pads on the lower surface of the semiconductor substrate.
在上述微型回馈腔传感器中,该半导体基底可更具有一第二感测电路;该感测元芯片可更具有至少一第二感测元结构,该半导体本体中形成有多个第二导电柱,至少一第二感测元结构、半导体基底与半导体本体之间形成一第二回馈腔体结构,至少一第二感测元结构是通过此些第二导电柱以电连接至该第二感测电路。至少一第二感测元结构与该第二回馈腔体结构共同反应一外界输入的第二物理信号而产生一第二感测信号输出至该第二感测电路。In the above-mentioned micro feedback cavity sensor, the semiconductor substrate may further have a second sensing circuit; the sensing element chip may further have at least one second sensing element structure, and a plurality of second conductive pillars are formed in the semiconductor body , a second feedback cavity structure is formed between at least one second sensing element structure, the semiconductor substrate and the semiconductor body, and at least one second sensing element structure is electrically connected to the second sensing element through the second conductive pillars test circuit. The at least one second sensing element structure and the second feedback cavity structure jointly respond to a second physical signal input from the outside to generate a second sensing signal and output it to the second sensing circuit.
本发明也提供一种微型回馈腔传感器的制造方法,包括以下步骤:提供一个半导体基底,具有一感测电路;在该半导体基底上形成一第一接合结构;提供一复合结构层,包括:一感测结构层;以及一个半导体基板,位于该感测结构层上;将该复合结构层通过第一接合结构与该半导体基底进行接合,以形成一接合结构层;移除该复合结构层的一部分,以形成:一感测元芯片,具有一低阻值的半导体本体、一第一端部及一第二端部,该半导体本体中形成有多个导电柱,该第一端部形成有至少一感测元结构,该第二端部是通过该接合结构层连接至该半导体基底,至少一感测元结构的下方与该半导体基底之间形成一回馈腔体结构,至少一感测元结构是通过此些导电柱以电连接至该感测电路。至少一感测元结构与该回馈腔体结构共同反应一外界输入的物理信号而产生一感测信号输出至该感测电路。The present invention also provides a method for manufacturing a micro feedback cavity sensor, comprising the following steps: providing a semiconductor substrate with a sensing circuit; forming a first bonding structure on the semiconductor substrate; providing a composite structure layer, including: a a sensing structure layer; and a semiconductor substrate on the sensing structure layer; bonding the composite structure layer with the semiconductor substrate through a first bonding structure to form a bonding structure layer; removing a part of the composite structure layer , to form: a sensor chip with a low-resistance semiconductor body, a first end portion and a second end portion, a plurality of conductive pillars are formed in the semiconductor body, and the first end portion is formed with at least a sensing element structure, the second end is connected to the semiconductor substrate through the bonding structure layer, a feedback cavity structure is formed between the bottom of at least one sensing element structure and the semiconductor substrate, at least one sensing element structure It is electrically connected to the sensing circuit through the conductive posts. At least one sensing element structure and the feedback cavity structure jointly respond to an externally input physical signal to generate a sensing signal and output it to the sensing circuit.
在上述制造方法中,移除该复合结构层的一部分的步骤所形成的感测元芯片可还包括一第一电性输出入结构,位于该回馈腔体结构的周围,该第一电性输出入结构具有多个第一连接垫,通过此些导电柱以电连接至该感测电路。In the above manufacturing method, the sensor chip formed by the step of removing a part of the composite structure layer may further include a first electrical input/output structure located around the feedback cavity structure, the first electrical output The input structure has a plurality of first connection pads, which are electrically connected to the sensing circuit through the conductive pillars.
在上述制造方法中,移除该复合结构层的一部分的步骤所形成的感测元芯片可还包括一遮蔽芯片,具有一低阻值的半导体本体、一第一端部以及一第二端部,该遮蔽芯片的第二端部连接至感测元芯片的第一端部,以及去除部分遮蔽芯片的半导体本体以露出部分或全部的感测元结构而形成的一开放工作腔,该感测元结构感测经由该开放工作腔所接收的物理信号而产生感测信号。In the above-mentioned manufacturing method, the sensor chip formed by the step of removing a part of the composite structure layer may further include a shielding chip having a low-resistance semiconductor body, a first end portion and a second end portion , the second end of the shielding chip is connected to the first end of the sensing element chip, and an open working cavity formed by removing part of the semiconductor body of the shielding chip to expose part or all of the sensing element structure, the sensing element The metastructure senses the physical signal received via the open working cavity to generate the sensing signal.
在上述制造方法中,移除该复合结构层的一部分的步骤所形成的感测元芯片可还包括一第一电性输出入结构,位于该回馈腔体结构的周围,该第一电性输出入结构具有多个第一连接垫,通过此些导电柱以电连接至该感测电路,而该遮蔽芯片还包括一第二电性输出入结构,位于该开放工作腔的周围以及第一电性输出入结构上,该第二电性输出入结构具有多个第二连接垫,分别电连接至此些第一连接垫。In the above manufacturing method, the sensor chip formed by the step of removing a part of the composite structure layer may further include a first electrical input/output structure located around the feedback cavity structure, the first electrical output The input structure has a plurality of first connection pads, which are electrically connected to the sensing circuit through the conductive pillars, and the shielding chip further includes a second electrical input/output structure located around the open working cavity and the first electrical On the electrical I/O structure, the second electrical I/O structure has a plurality of second connection pads, which are respectively electrically connected to the first connection pads.
在上述制造方法中,该遮蔽芯片可包括一整合式导体层,所述整合式导体层位于该遮蔽芯片的该半导体本体上,且更贯穿该遮蔽芯片的该半导体本体及该感测元芯片的一部分,而电连接至该感测元芯片的一电性输出入结构,以电连接至该感测电路。In the above manufacturing method, the shielding chip may include an integrated conductor layer, the integrated conductor layer is located on the semiconductor body of the shielding chip and further penetrates the semiconductor body of the shielding chip and the sensing element chip. A part is electrically connected to an electrical I/O structure of the sensing chip, so as to be electrically connected to the sensing circuit.
本发明的有益效果是:通过上述实施例,可以让微型回馈腔传感器当作麦克风使用,也可以当作压力传感器使用,也可以是让微型回馈腔传感器同时具有麦克风与压力传感器的功能,达到传感器整合的效果。此外,本发明利用晶圆级的制造技术,可以大量生产,降低成本。再者,本发明的制造方式可以达到大幅加大工作腔(背腔)的体积,降低麦克风的前腔体积,也可以大幅缩小微型回馈腔传感器的尺寸。The beneficial effects of the present invention are: through the above embodiment, the micro feedback cavity sensor can be used as a microphone, and can also be used as a pressure sensor, or the micro feedback cavity sensor can have the functions of a microphone and a pressure sensor at the same time, so that the sensor can be used as a sensor. integrated effect. In addition, the present invention utilizes the wafer-level manufacturing technology, which can be mass-produced and reduce the cost. Furthermore, the manufacturing method of the present invention can greatly increase the volume of the working cavity (back cavity), reduce the volume of the front cavity of the microphone, and can also greatly reduce the size of the micro feedback cavity sensor.
为让本发明的上述内容能更明显易懂,下文特举较佳实施例,并配合附图,作详细说明如下。In order to make the above-mentioned content of the present invention more obvious and easy to understand, preferred embodiments are exemplified below, and are described in detail as follows in conjunction with the accompanying drawings.
附图说明Description of drawings
图1显示依据本发明第一实施例的微型回馈腔传感器的局部剖视图。FIG. 1 shows a partial cross-sectional view of a micro feedback cavity sensor according to a first embodiment of the present invention.
图2A至图4C显示依据本发明第一实施例的微型回馈腔传感器的制造方法的各步骤的局部剖视图。2A to FIG. 4C are partial cross-sectional views showing each step of the manufacturing method of the micro feedback cavity sensor according to the first embodiment of the present invention.
图5显示依据本发明第二实施例的微型回馈腔传感器的局部剖视图。FIG. 5 shows a partial cross-sectional view of a micro feedback cavity sensor according to a second embodiment of the present invention.
图6A至图6D显示依据本发明第二实施例的微型回馈腔传感器的制造方法的各步骤的局部剖视图。FIGS. 6A to 6D are partial cross-sectional views of each step of the manufacturing method of the micro feedback cavity sensor according to the second embodiment of the present invention.
图7显示依据本发明第三实施例的微型回馈腔传感器的局部剖视图。7 shows a partial cross-sectional view of a micro feedback cavity sensor according to a third embodiment of the present invention.
图8A与图8B显示依据本发明各实施例的微型回馈腔传感器的感测元结构的另一个例子的局部剖视图及俯视示意图。8A and 8B show a partial cross-sectional view and a schematic top view of another example of the sensing element structure of the micro feedback cavity sensor according to various embodiments of the present invention.
图9显示依据本发明各实施例的微型回馈腔传感器的半导体基底的另一个例子的局部剖视图。9 shows a partial cross-sectional view of another example of a semiconductor substrate of a micro feedback cavity sensor according to various embodiments of the present invention.
图10显示依据本发明第四实施例的微型回馈腔传感器的局部剖视图。10 shows a partial cross-sectional view of a micro feedback cavity sensor according to a fourth embodiment of the present invention.
图11A至图12F显示依据本发明第四实施例的微型回馈腔传感器的制造方法的各步骤的局部剖视图。FIGS. 11A to 12F are partial cross-sectional views showing various steps of a manufacturing method of a micro feedback cavity sensor according to a fourth embodiment of the present invention.
图13显示依据本发明第五实施例的微型回馈腔传感器的局部剖视图。13 shows a partial cross-sectional view of a micro feedback cavity sensor according to a fifth embodiment of the present invention.
图14显示一种传统的微型麦克风的封装示意图。FIG. 14 shows a schematic diagram of a package of a conventional miniature microphone.
附图标号:CV:固定电位;H:孔洞;10:半导体基底;10':半导体基底;11:第一硅基板;12:感测电路;13:模塑料层;14:导体连接层;15:侧面;16:下表面;20:感测元芯片;21:半导体本体;22:第一端部;23:感测元结构;23A:第二感测元结构;24:第二端部;25:回馈腔体结构;25A:第二回馈腔体结构;26:第一电性输出入结构;27、27':导电柱;27A、27A':第二导电柱;28:第一连接垫;29、29':导电路径;29A、29A':第二导电路径;30:遮蔽芯片;31:半导体本体;32:第一端部;34:第二端部;35:开放工作腔;36:第二电性输出入结构;37:导体层;38:第二连接垫;39:沟槽;40:接合结构层;41:第一接合结构;42:第二接合结构;50:电路板;50C:开口;60:连接部;71:绝缘层;72:绝缘层;73、73A、73B:绝缘层;74:绝缘层;80:整合式导体层;100、100'、100”、100C、100D:微型回馈腔传感器;200:复合结构层;210:半导体基板;211:沟槽;220:感测结构层;231:第一电极板;231A:第一电极板;232:第二电极板;232A:第二电极板;233:上表面;234:压电材料层;235、235':间隙;236:凹槽;262:导体连接层;263:上表面;301:半导体基板;302:绝缘层;303:第一电极板层;304:凹槽;305:绝缘层;306:凹槽;307:第二电极板层;308:凹槽;309:绝缘层;310:凹槽;311:下表面;363:垂直导体;400:半导体基板。Reference numerals: CV: fixed potential; H: hole; 10: semiconductor substrate; 10': semiconductor substrate; 11: first silicon substrate; 12: sensing circuit; 13: molding compound layer; 14: conductor connection layer; 15 : side surface; 16: lower surface; 20: sensing element chip; 21: semiconductor body; 22: first end portion; 23: sensing element structure; 23A: second sensing element structure; 24: second end portion; 25: feedback cavity structure; 25A: second feedback cavity structure; 26: first electrical I/O structure; 27, 27': conductive posts; 27A, 27A': second conductive posts; 28: first connection pads ; 29, 29': conductive path; 29A, 29A': second conductive path; 30: shield chip; 31: semiconductor body; 32: first end; 34: second end; 35: open working cavity; 36 : second electrical I/O structure; 37: conductor layer; 38: second connection pad; 39: groove; 40: bonding structure layer; 41: first bonding structure; 42: second bonding structure; 50: circuit board ; 50C: opening; 60: connecting part; 71: insulating layer; 72: insulating layer; 73, 73A, 73B: insulating layer; 74: insulating layer; 80: integrated conductor layer; , 100D: micro feedback cavity sensor; 200: composite structure layer; 210: semiconductor substrate; 211: trench; 220: sensing structure layer; 231: first electrode plate; 231A: first electrode plate; 232: second electrode plate; 232A: second electrode plate; 233: upper surface; 234: piezoelectric material layer; 235, 235': gap; 236: groove; 262: conductor connection layer; 263: upper surface; 301: semiconductor substrate; 302 : insulating layer; 303: first electrode plate layer; 304: groove; 305: insulating layer; 306: groove; 307: second electrode plate layer; 308: groove; 309: insulating layer; 310: groove; 311: lower surface; 363: vertical conductor; 400: semiconductor substrate.
具体实施方式Detailed ways
本发明的实施例的具有回馈腔体设计的微型回馈腔传感器可以当作声波传感器(例如麦克风)、超声波传感器使用,也可以当作压力传感器使用,也可以是同时具有例如麦克风与压力传感器的功能,达到传感器整合的效果。当然也不限定于此,其他可以通过回馈腔体设计达到提升传感器品质的其他类型传感器,例如热感应式(thermal-type),移动式(motion-type)等等传感器也都可以适用于本发明的结构及制造工艺。此外,本发明利用晶圆级的制造技术,可以大量生产,降低成本。再者,本发明完全舍弃传统的封装方式以制作工作腔(背腔)的体积,而完全利用晶圆级制造方式可以同时完成大工作腔(背腔)的体积设计制造,并且也完成了晶圆级的封装技术,例如降低麦克风的前腔长度,也大幅缩小微型回馈腔传感器的尺寸。这些特征,都是已知技术完全没有的。为此,以下实施例将说明本发明的特点,并将它延伸至所有需要回馈腔体设计的传感器。The miniature feedback cavity sensor with the feedback cavity design of the embodiment of the present invention can be used as an acoustic wave sensor (such as a microphone), an ultrasonic sensor, or a pressure sensor, or can have functions such as a microphone and a pressure sensor at the same time. , to achieve the effect of sensor integration. Of course, it is not limited to this. Other types of sensors that can improve the quality of the sensor through the design of the feedback cavity, such as thermal-type sensors, motion-type sensors, etc., can also be applied to the present invention. structure and manufacturing process. In addition, the present invention utilizes the wafer-level manufacturing technology, which can be mass-produced and reduce the cost. Furthermore, the present invention completely abandons the traditional packaging method to manufacture the volume of the working cavity (back cavity), and completely uses the wafer-level manufacturing method to complete the volume design and manufacture of the large working cavity (back cavity) at the same time, and also completes the wafer-level manufacturing process. Circular-level packaging techniques, such as reducing the length of the front cavity of the microphone, have also greatly reduced the size of the micro feedback cavity sensor. These features are completely absent from the known technology. To this end, the following examples will illustrate the features of the present invention and extend it to all sensors that require a feedback cavity design.
图1显示依据本发明第一实施例的微型回馈腔传感器100的局部剖视图。如图1所示,本实施例的微型回馈腔传感器100包括一个半导体基底10、一接合结构层40以及一感测元芯片20。FIG. 1 shows a partial cross-sectional view of a micro feedback cavity sensor 100 according to a first embodiment of the present invention. As shown in FIG. 1 , the micro feedback cavity sensor 100 of this embodiment includes a semiconductor substrate 10 , a bonding structure layer 40 and a sensor chip 20 .
半导体基底10具有一感测电路12。举例而言,半导体基底10包括一第一硅基板11以及一导体连接层14。感测电路12形成于第一硅基板11内。导体连接层14位于第一硅基板11及感测电路12上,并将感测电路12电连接至感测元芯片20。导体连接层14包括导体连接线及层间介电层(Inter-Layer Dielectric,ILD)或金属层间介电层(Inter-MetalDielectric,IMD),主要是提供电连接的功能,可以利用目前的半导体制造技术轻易完成,故在此不再赘述。The semiconductor substrate 10 has a sensing circuit 12 . For example, the semiconductor substrate 10 includes a first silicon substrate 11 and a conductor connection layer 14 . The sensing circuit 12 is formed in the first silicon substrate 11 . The conductor connection layer 14 is located on the first silicon substrate 11 and the sensing circuit 12 , and electrically connects the sensing circuit 12 to the sensing element chip 20 . The conductor connection layer 14 includes conductor connection lines and an interlayer dielectric layer (Inter-Layer Dielectric, ILD) or a metal interlayer dielectric layer (Inter-Metal Dielectric, IMD), which mainly provides the function of electrical connection, and can utilize the current semiconductor The manufacturing technology is easy to accomplish, so it is not repeated here.
感测元芯片20具有一低阻值的半导体本体21、一第一端部22(芯片正面)及一第二端部24(芯片背面)。接合结构层40位于半导体基底10上,并包括第一接合结构41与第二接合结构42。第一接合结构41与第二接合结构42的材料可以是选自于铝、铜、锗、金、锡、铟、硅等等所组成的群组。举例而言,第一接合结构41的材料为铝,而第二接合结构42的材料为锗,其中铝和锗可以在约420℃形成共晶接合(eutectic bonding),并且这两种材料与CMOS制造工艺相容,更适合应用于本实施例具有集成电路整合的设计。另外有种情况,第二接合结构42是不存在的,半导体本体21的硅材料本身就可以是第二接合结构42的材料,而此时第一接合结构41可以是金(Au)。The sensor chip 20 has a low-resistance semiconductor body 21 , a first end 22 (chip front) and a second end 24 (chip back). The bonding structure layer 40 is located on the semiconductor substrate 10 and includes a first bonding structure 41 and a second bonding structure 42 . The materials of the first bonding structure 41 and the second bonding structure 42 may be selected from the group consisting of aluminum, copper, germanium, gold, tin, indium, silicon, and the like. For example, the material of the first bonding structure 41 is aluminum, and the material of the second bonding structure 42 is germanium, wherein aluminum and germanium can form eutectic bonding at about 420° C., and these two materials are compatible with CMOS The manufacturing process is compatible, and it is more suitable for the design with integrated circuit integration in this embodiment. In another case, the second bonding structure 42 does not exist, the silicon material of the semiconductor body 21 itself may be the material of the second bonding structure 42, and the first bonding structure 41 may be gold (Au).
半导体本体21的材料譬如是硅,其中半导体本体21被设计制造成几部分,以包括有多个独立导电柱27。第一端部22形成有位于半导体本体21的正面的至少一感测元结构23。半导体本体21的背面及第二端部24是通过接合结构层40连接至半导体基底10,至少一感测元结构23、半导体基底10与四周的半导体本体21的侧壁之间形成一回馈腔体结构25。至少一感测元结构23是通过此些导电柱27以电连接至感测电路12,其中导电柱27为整个导电路径29的一部分。在此实施例中,感测元结构23包括一第一电极板231及一第二电极板232,这样的安排为一电容式感测结构。第一电极板231固定地设置于半导体本体21上,并具有多个孔洞H,以让例如声波对第二电极板232产生振动时,使位于两电极板间的空气得以反映所述振动而通过所述多个孔洞H进入所述回馈腔体结构25中。第二电极板232可动地设置于第一电极板231的上方。第一电极板231与第二电极板232形成一感测电容,第一电极板231与第二电极板232之间形成有一间隙235,第二电极板232的设计因传感器而异,当作为麦克风振膜时,其可为不完全密闭的弹性结构。当微型回馈腔传感器100当作压力传感器使用时,第二电极板232为一密闭结构,完全阻绝所述回馈腔体结构25的腔体与外界连通,受到流体压力的变化而变形,从而产生电容变化,回馈腔体结构25为一个密闭的腔体,特别是超低压的腔体。回馈腔体结构内的腔体的高度在本发明中,完全由硅晶圆的厚度决定可以制作到700微米(um)以上,也因此,本发明完全利用了晶圆制造的弹性制作了大体积(Z轴由厚度决定,X与Y轴由光罩设计决定)。如果用传统TSV结构来将感测元结构23电连接至感测电路12,则受限TSV技术,所述半导体本体21的厚度约100um~150um,代表腔体体积将只有本发明的1/4~1/10,将降低传感器品质。这里的大体积回馈腔体设计,主要发明特点来自于,完全不需要TSV设计,而是利用光刻技术,制作出独立的硅导体柱,两两间空气绝缘,并利用相同流程,完成了此一大体积回馈腔体设计。因此,这也是本发明实施例所提供的特征及优点。The material of the semiconductor body 21 is silicon, for example, wherein the semiconductor body 21 is designed and manufactured in several parts to include a plurality of independent conductive pillars 27 . The first end portion 22 is formed with at least one sensing element structure 23 located on the front surface of the semiconductor body 21 . The backside of the semiconductor body 21 and the second end portion 24 are connected to the semiconductor substrate 10 through the bonding structure layer 40 , and a feedback cavity is formed between at least one sensing element structure 23 , the semiconductor substrate 10 and the sidewalls of the surrounding semiconductor body 21 . Structure 25. At least one sensing element structure 23 is electrically connected to the sensing circuit 12 through the conductive pillars 27 , wherein the conductive pillars 27 are part of the entire conductive path 29 . In this embodiment, the sensing element structure 23 includes a first electrode plate 231 and a second electrode plate 232, and this arrangement is a capacitive sensing structure. The first electrode plate 231 is fixedly disposed on the semiconductor body 21 and has a plurality of holes H, so that when, for example, sound waves vibrate the second electrode plate 232, the air between the two electrode plates can reflect the vibration and pass through. The plurality of holes H enter into the feedback cavity structure 25 . The second electrode plate 232 is movably disposed above the first electrode plate 231 . The first electrode plate 231 and the second electrode plate 232 form a sensing capacitor, and a gap 235 is formed between the first electrode plate 231 and the second electrode plate 232. The design of the second electrode plate 232 varies depending on the sensor, and is used as a microphone When the diaphragm is used, it can be an elastic structure that is not completely sealed. When the micro feedback cavity sensor 100 is used as a pressure sensor, the second electrode plate 232 is a closed structure, which completely blocks the cavity of the feedback cavity structure 25 from communicating with the outside world, and is deformed by the change of fluid pressure, thereby generating capacitance Variation, the feedback cavity structure 25 is a closed cavity, especially an ultra-low pressure cavity. In the present invention, the height of the cavity in the feedback cavity structure is completely determined by the thickness of the silicon wafer and can be fabricated to more than 700 microns (um). Therefore, the present invention fully utilizes the flexibility of wafer fabrication to produce a large volume (The Z axis is determined by the thickness, and the X and Y axes are determined by the reticle design). If the traditional TSV structure is used to electrically connect the sensing element structure 23 to the sensing circuit 12, the TSV technology is limited, and the thickness of the semiconductor body 21 is about 100um-150um, which means that the volume of the cavity will be only 1/4 of the present invention ~1/10, will degrade sensor quality. The main inventive feature of the large-volume feedback cavity design here comes from the fact that it does not require TSV design at all, but uses photolithography technology to produce independent silicon conductor columns, which are air-insulated, and use the same process to complete this. Large volume feedback cavity design. Therefore, this is also a feature and advantage provided by the embodiments of the present invention.
至少一感测元结构23与回馈腔体结构25共同反应一外界输入的物理信号而产生一感测信号输出至感测电路12。此物理信号包括但不限于声波、气体压力等。接收到声波时,第二电极板232振动而产生感测电容的变化,如此可以获得感测信号。由于可以使用深刻蚀技术来形成回馈腔体结构25,使得回馈腔体结构25的体积可以被制作得相当大,大幅提升感测效果。At least one sensing element structure 23 and the feedback cavity structure 25 jointly respond to an externally input physical signal to generate a sensing signal and output it to the sensing circuit 12 . Such physical signals include, but are not limited to, sound waves, gas pressure, and the like. When the sound wave is received, the second electrode plate 232 vibrates to generate a change in the sensing capacitance, so that a sensing signal can be obtained. Since the feedback cavity structure 25 can be formed by using a deep etching technique, the volume of the feedback cavity structure 25 can be made quite large, which greatly improves the sensing effect.
值得注意的是,具有上述结构的微型回馈腔传感器100即可达成本发明实施例的功效。当然,以下结构的附加仅是让本发明实施例的实施更加完整,并非将本发明限制于此。It should be noted that the micro feedback cavity sensor 100 with the above structure can achieve the effect of the embodiment of the present invention. Of course, the addition of the following structures is only to make the implementation of the embodiments of the present invention more complete, and does not limit the present invention to this.
为了将感测电路12的信号往上传到上方的电路板上,感测元芯片20还包括一第一电性输出入结构26,位于回馈腔体结构25的周围,第一电性输出入结构26具有多个第一连接垫28,通过此些部分半导体本体21所形成的导电柱27',以电连接至感测电路12,其中导电柱27'为整个导电路径29'的一部分。因此,微型回馈腔传感器100可以还包括一电路板50,设置于第一电性输出入结构26的上方,并电连接至此些第一连接垫28,譬如是通过多个连接部60而电连接至第一连接垫28。在一例子中,连接部60可以是锡球,利用球栅阵列封装(Ball Grid Array,简称BGA)的方式进行封装。当然,其他电连接方式也可被采用。In order to upload the signal of the sensing circuit 12 to the upper circuit board, the sensing element chip 20 further includes a first electrical I/O structure 26 located around the feedback cavity structure 25. The first electrical I/O structure 26 has a plurality of first connection pads 28, and the conductive pillars 27' formed by these parts of the semiconductor body 21 are electrically connected to the sensing circuit 12, wherein the conductive pillars 27' are part of the entire conductive path 29'. Therefore, the micro feedback cavity sensor 100 may further include a circuit board 50 disposed above the first electrical I/O structure 26 and electrically connected to the first connection pads 28 , for example, through a plurality of connection parts 60 . to the first connection pad 28 . In one example, the connection portion 60 may be a solder ball, and is packaged in a Ball Grid Array (Ball Grid Array, BGA for short) manner. Of course, other electrical connection methods can also be used.
此外,由于使用半导体制造工艺来制作,所以第一电极板231与第二电极板232的材料譬如是多晶硅,第一电性输出入结构26的一导体连接层262也是由多晶硅所制作出。因此,第二电极板232、第一电极板231与导体连接层262可以在同一系列的制造工艺中完成。因此,导体连接层262的一上表面263与感测元结构23的一上表面233位于同一平面上。In addition, since the semiconductor manufacturing process is used, the first electrode plate 231 and the second electrode plate 232 are made of polysilicon, for example, and a conductor connection layer 262 of the first electrical I/O structure 26 is also made of polysilicon. Therefore, the second electrode plate 232, the first electrode plate 231 and the conductor connection layer 262 can be completed in the same series of manufacturing processes. Therefore, an upper surface 263 of the conductor connection layer 262 and an upper surface 233 of the sensing element structure 23 are located on the same plane.
为了提供前腔,微型回馈腔传感器100可以还包括一遮蔽芯片30,具有一低阻值的半导体本体31、一第一端部32以及一第二端部34。第二端部34连接至感测元芯片20的第一端部22,以及去除部分遮蔽芯片30的半导体本体31以露出部分或全部的感测元结构23而形成的一开放工作腔35。感测元结构23感测经由开放工作腔35所接收的物理信号而产生感测信号。In order to provide the front cavity, the micro feedback cavity sensor 100 may further include a shielding chip 30 having a low-resistance semiconductor body 31 , a first end 32 and a second end 34 . The second end 34 is connected to the first end 22 of the sensing element chip 20 and an open working cavity 35 formed by removing part of the semiconductor body 31 shielding the chip 30 to expose part or all of the sensing element structure 23 . The sensing element structure 23 senses the physical signal received through the open working chamber 35 to generate a sensing signal.
值得注意的是,导体连接层14上有绝缘层71,绝缘层71设置于第一接合结构41之间以及第二接合结构42之间,以提供绝缘的效果。此外,第一电极板231与第二电极板232之间的部分绝缘层72被去除(通称牺牲层刻蚀),部分绝缘层72被保留用于支撑第一电极板231与第二电极板232,而且第二电极板232与半导体本体31之间也形成有绝缘层73。再者,半导体本体21与第一电极板231之间也形成有绝缘层74,当然为了制造及电性考虑,上述绝缘层可以为单一或复合层材料。It is worth noting that there is an insulating layer 71 on the conductor connection layer 14 , and the insulating layer 71 is disposed between the first bonding structures 41 and between the second bonding structures 42 to provide an insulating effect. In addition, part of the insulating layer 72 between the first electrode plate 231 and the second electrode plate 232 is removed (referred to as sacrificial layer etching), and part of the insulating layer 72 is reserved for supporting the first electrode plate 231 and the second electrode plate 232 , and an insulating layer 73 is also formed between the second electrode plate 232 and the semiconductor body 31 . Furthermore, an insulating layer 74 is also formed between the semiconductor body 21 and the first electrode plate 231 . Of course, for the consideration of manufacturing and electrical properties, the insulating layer may be a single layer or a composite layer material.
图2A至图4C显示依据本发明第一实施例的微型回馈腔传感器的制造方法的各步骤的局部剖视图。首先,如图1所示,提供一个半导体基底10,其具有一感测电路12,并在半导体基底10上形成一第一接合结构41。此外,如图2A至3C所示,提供一复合结构层200,其包括:一第二接合结构42;一感测结构层220,位于第二接合结构42上;以及一个半导体基板210(图4B,半导体基板210为半导体基板400的一部分),位于感测结构层220上。此外,如图4A所示,将复合结构层200通过第一接合结构41及第二接合结构42进行接合,以形成接合结构层40。当第二接合结构42不存在时,也可进行接合,如上所述。在此情况下,则是将复合结构层200通过第一接合结构41与半导体基底10进行接合,以形成接合结构层40。2A to FIG. 4C are partial cross-sectional views showing each step of the manufacturing method of the micro feedback cavity sensor according to the first embodiment of the present invention. First, as shown in FIG. 1 , a semiconductor substrate 10 having a sensing circuit 12 is provided, and a first bonding structure 41 is formed on the semiconductor substrate 10 . In addition, as shown in FIGS. 2A to 3C, a composite structure layer 200 is provided, which includes: a second bonding structure 42; a sensing structure layer 220 on the second bonding structure 42; and a semiconductor substrate 210 (FIG. 4B , the semiconductor substrate 210 is a part of the semiconductor substrate 400 ) located on the sensing structure layer 220 . In addition, as shown in FIG. 4A , the composite structure layer 200 is bonded through the first bonding structure 41 and the second bonding structure 42 to form the bonding structure layer 40 . Bonding may also be performed when the second bonding structure 42 is not present, as described above. In this case, the composite structure layer 200 is bonded to the semiconductor substrate 10 through the first bonding structure 41 to form the bonding structure layer 40 .
然后,如图4A至图4C所示(配合参考图1),移除复合结构层200的一部分,以形成:一感测元芯片20,具有一低阻值的半导体本体21、一第一端部22及一第二端部24,半导体本体21中形成有多个导电柱27,第一端部22形成有至少一感测元结构23,第二端部24是通过接合结构层40连接至半导体基底10,至少一感测元结构23的下方与半导体基底10之间形成一回馈腔体结构25,至少一感测元结构23是通过此些导电柱27以电连接至感测电路12。Then, as shown in FIGS. 4A to 4C (with reference to FIG. 1 ), a part of the composite structure layer 200 is removed to form: a sensor chip 20 , a semiconductor body 21 having a low resistance value, a first end A plurality of conductive pillars 27 are formed in the semiconductor body 21, at least one sensing element structure 23 is formed on the first end 22, and the second end 24 is connected to the In the semiconductor substrate 10 , a feedback cavity structure 25 is formed between the at least one sensing element structure 23 and the semiconductor substrate 10 , and the at least one sensing element structure 23 is electrically connected to the sensing circuit 12 through the conductive pillars 27 .
移除复合结构层200的一部分的步骤所形成的感测元芯片20可以还包括第一电性输出入结构26以及遮蔽芯片30,如图4C与图1所示。上述的制造工艺都可以使用晶圆级的制造工艺来完成,以达成大量生产的目的。The sensor chip 20 formed by the step of removing a part of the composite structure layer 200 may further include the first electrical I/O structure 26 and the shielding chip 30 , as shown in FIG. 4C and FIG. 1 . The above-mentioned manufacturing processes can all be accomplished using wafer-level manufacturing processes to achieve mass production.
详言之,如图2A所示,提供一个半导体基板301,并在半导体基板301上形成一个图案化的绝缘层302。然后,如图2B所示,在半导体基板301以及绝缘层302上形成一个图案化的第一电极板层303,其具有多个凹槽304。接着,如图2C所示,在第一电极板层303及凹槽304上形成一个图案化的绝缘层305,绝缘层305具有多个凹槽306以露出部分的第一电极板层303。然后,如图2D所示,在绝缘层305与第一电极板层303上形成一个图案化的第二电极板层307,填满凹槽306。接着,如图2E所示,在第二电极板层307上形成多个第一连接垫28。然后,如图2F所示,移除部分的第二电极板层307,以形成多个凹槽308,并在第二电极板层307与凹槽308中形成一绝缘层309,并在绝缘层309上形成多个凹槽310,以露出第一连接垫28,值得说明的是,上述制造工艺更可以包括利用化学机械研磨(Chemical-MechanicalPolishing,CMP)将不平整的表面,研磨成平坦表面,以利厚度控制,并且,上述绝缘层,甚或电极板层,也可以不是单一材料,更可以包括复合层材料,例如绝缘层可以是氧化硅、氮化硅、氧化铝、碳化硅(SiC)、类碳钻膜(Diamond like carbon)等等单一层或组合层,而电极板层在本实施例为多晶硅,当然也可以是与上述绝缘层材料组合而成的复合结构,例如绝缘层/多晶硅/绝缘层。Specifically, as shown in FIG. 2A , a semiconductor substrate 301 is provided, and a patterned insulating layer 302 is formed on the semiconductor substrate 301 . Then, as shown in FIG. 2B , a patterned first electrode plate layer 303 having a plurality of grooves 304 is formed on the semiconductor substrate 301 and the insulating layer 302 . Next, as shown in FIG. 2C , a patterned insulating layer 305 is formed on the first electrode plate layer 303 and the grooves 304 . The insulating layer 305 has a plurality of grooves 306 to expose part of the first electrode plate layer 303 . Then, as shown in FIG. 2D , a patterned second electrode plate layer 307 is formed on the insulating layer 305 and the first electrode plate layer 303 to fill the groove 306 . Next, as shown in FIG. 2E , a plurality of first connection pads 28 are formed on the second electrode plate layer 307 . Then, as shown in FIG. 2F, a part of the second electrode plate layer 307 is removed to form a plurality of grooves 308, and an insulating layer 309 is formed in the second electrode plate layer 307 and the grooves 308, and the insulating layer A plurality of grooves 310 are formed on the 309 to expose the first connection pad 28. It is worth noting that the above-mentioned manufacturing process may further include using chemical mechanical polishing (Chemical-Mechanical Polishing, CMP) to grind the uneven surface into a flat surface, In order to facilitate thickness control, and the above-mentioned insulating layer, or even the electrode plate layer, may not be a single material, but may include a composite layer material, for example, the insulating layer can be silicon oxide, silicon nitride, aluminum oxide, silicon carbide (SiC), Diamond like carbon film (Diamond like carbon), etc. is a single layer or a combined layer, and the electrode plate layer is polysilicon in this embodiment, of course, it can also be a composite structure combined with the above insulating layer materials, such as insulating layer/polysilicon/ Insulation.
然后,如图3A所示,将一个半导体基板400附着至绝缘层309上,在本实施例中两者是通过低温接合方式(low temperature fusion bonding)形成具有氢键强度的接口。当然在形成低温接合之前,更可以包括水清洗及例如低浓度氢氟酸以去除半导体基板400表面的氧化层(HF dip),为了达到表面活化,更可以包括表面电浆(plasma)处理,例如暴露在氧气(O2)及氮气(N2)的电浆环境下,而且为了让接合的表面有很好的平坦度,更可以利用化学机械研磨法(CMP)将待接合的表面予以抛光及抛平。接着,如图3B所示,在半导体基板301的下表面311形成图案化的第二接合结构42。然后,如图3C所示,以第二接合结构42作为遮罩进行刻蚀,以移除部分的半导体基板301,而形成具有感测结构层220的复合结构层200。另一种制造具体实施方式是在图3C的对应步骤中,可以直接去除位于第一电极板231与第二电极板232之间的部分绝缘层72(通称牺牲层刻蚀,请对应参照图1),以完成所述电容式感测元结构。Then, as shown in FIG. 3A , a semiconductor substrate 400 is attached to the insulating layer 309 , in this embodiment, the two are formed by a low temperature fusion bonding method to form an interface with hydrogen bond strength. Of course, before forming the low-temperature bonding, water cleaning and, for example, low-concentration hydrofluoric acid may be included to remove the oxide layer (HF dip) on the surface of the semiconductor substrate 400. In order to achieve surface activation, surface plasma treatment may be included, such as It is exposed to the plasma environment of oxygen (O 2 ) and nitrogen (N 2 ), and in order to make the joint surface have a good flatness, chemical mechanical polishing (CMP) can be used to polish the surface to be joined and Flatten. Next, as shown in FIG. 3B , a patterned second bonding structure 42 is formed on the lower surface 311 of the semiconductor substrate 301 . Then, as shown in FIG. 3C , etching is performed using the second bonding structure 42 as a mask to remove part of the semiconductor substrate 301 to form the composite structure layer 200 having the sensing structure layer 220 . Another specific manufacturing method is that in the corresponding step of FIG. 3C , part of the insulating layer 72 between the first electrode plate 231 and the second electrode plate 232 can be directly removed (commonly referred to as sacrificial layer etching, please refer to FIG. 1 ). ) to complete the capacitive sensing element structure.
接着,如图4A所示,将复合结构层200通过第一接合结构41及第二接合结构42进行接合,以形成包括第一接合结构41与第二接合结构42的接合结构层40。然后,如图4B所示,移除半导体基板400的一部分,以将半导体基板变薄而形成半导体基板210,目的是缩短前腔距离,在本实施例,所述前腔距离<100um,当然不限定于此。然后,移除部分的半导体基板210,以形成半导体本体31,并移除部分的绝缘层305,以形成间隙235。Next, as shown in FIG. 4A , the composite structure layer 200 is bonded through the first bonding structure 41 and the second bonding structure 42 to form the bonding structure layer 40 including the first bonding structure 41 and the second bonding structure 42 . Then, as shown in FIG. 4B , a part of the semiconductor substrate 400 is removed to thin the semiconductor substrate to form the semiconductor substrate 210 , in order to shorten the front cavity distance. In this embodiment, the front cavity distance is less than 100um, of course not limited to this. Then, a portion of the semiconductor substrate 210 is removed to form the semiconductor body 31 , and a portion of the insulating layer 305 is removed to form the gap 235 .
上述的制造工艺涉及电容式感测技术。当使用压电或压阻式感测技术时,例如绝缘层305换成压电材料层,而第一与第二电极板则形成为所述压电材料层的接触电极。具有通常知识者可以轻易推敲而得,故于此不再赘述。The above-described fabrication process involves capacitive sensing technology. When piezoelectric or piezoresistive sensing techniques are used, for example, the insulating layer 305 is replaced by a layer of piezoelectric material, and the first and second electrode plates are formed as contact electrodes for the layer of piezoelectric material. Those with general knowledge can easily deduce it, so I won't repeat it here.
图5显示依据本发明第二实施例的微型回馈腔传感器100'的局部剖视图。如图5所示,本实施例类似于第一实施例,的不同点在于遮蔽芯片30还包括一第二电性输出入结构36,位于开放工作腔35的周围以及第一电性输出入结构26上,第二电性输出入结构36具有多个第二连接垫38,分别电连接至此些第一连接垫28,而第二电性输出入结构36还包括多个垂直导体363,贯穿遮蔽芯片30而电连接至此些第二连接垫38及此些第一连接垫28。此外,遮蔽芯片30包括一外露导体层37,电连接至一固定电位CV,譬如是接地电位或其他电位,使半导体本体31成为非浮动状态,避免杂讯干扰感测结果。值得注意的是,也可使用连接部60来将外露导体层37连接至电路板50的固定电位。FIG. 5 shows a partial cross-sectional view of the micro feedback cavity sensor 100 ′ according to the second embodiment of the present invention. As shown in FIG. 5 , this embodiment is similar to the first embodiment, except that the shielding chip 30 further includes a second electrical I/O structure 36 located around the open working cavity 35 and the first electrical I/O structure 26, the second electrical I/O structure 36 has a plurality of second connection pads 38, which are respectively electrically connected to the first connection pads 28, and the second electrical I/O structure 36 also includes a plurality of vertical conductors 363, penetrating the shielding The chip 30 is electrically connected to the second connection pads 38 and the first connection pads 28 . In addition, the shielding chip 30 includes an exposed conductor layer 37 that is electrically connected to a fixed potential CV, such as a ground potential or other potentials, so that the semiconductor body 31 is in a non-floating state to prevent noise from interfering with the sensing results. Notably, the connection portion 60 may also be used to connect the exposed conductor layer 37 to a fixed potential of the circuit board 50 .
此外,电路板50设置于遮蔽芯片30的上方,并电连接至此些第二连接垫38。如此一来,物理信号是通过电路板50与此些第二连接垫38之间的空隙进入开放工作腔35。In addition, the circuit board 50 is disposed above the shielding chip 30 and is electrically connected to the second connection pads 38 . In this way, physical signals enter the open working cavity 35 through the gaps between the circuit board 50 and the second connection pads 38 .
图6A至图6D显示依据本发明第二实施例的微型回馈腔传感器的制造方法的各步骤的局部剖视图。本实施例的制造方法的前段过程类似于图2A至图4B,在此不再赘述类似的部分。FIGS. 6A to 6D are partial cross-sectional views of each step of the manufacturing method of the micro feedback cavity sensor according to the second embodiment of the present invention. The preceding process of the manufacturing method of the present embodiment is similar to FIG. 2A to FIG. 4B , and similar parts are not repeated here.
首先,如图6A所示,在半导体基板210上形成多个沟槽211。然后,如图6B所示,在沟槽211中形成垂直导体363,在本实施例中,所述垂直导体可以是钨(W)、铜(Cu)等等。接着,如图6C所示,在半导体基板210及垂直导体363上形成多个第二连接垫38及多个外露导体层37。接着,如图6D所示,移除部分的半导体基板210以形成感测元芯片20。因此,如图6D与图5所示,此感测元芯片20还包括一第一电性输出入结构26,位于回馈腔体结构25的周围,第一电性输出入结构26具有多个第一连接垫28,通过此些部分半导体本体21所形成的导电柱27',以电连接至感测电路12,而遮蔽芯片30还包括一第二电性输出入结构36,位于开放工作腔35的周围以及第一电性输出入结构26上,第二电性输出入结构36具有多个第二连接垫38,分别电连接至此些第一连接垫28。First, as shown in FIG. 6A , a plurality of trenches 211 are formed on the semiconductor substrate 210 . Then, as shown in FIG. 6B, vertical conductors 363 are formed in the trenches 211, and in this embodiment, the vertical conductors may be tungsten (W), copper (Cu), or the like. Next, as shown in FIG. 6C , a plurality of second connection pads 38 and a plurality of exposed conductor layers 37 are formed on the semiconductor substrate 210 and the vertical conductors 363 . Next, as shown in FIG. 6D , part of the semiconductor substrate 210 is removed to form the sensor chip 20 . Therefore, as shown in FIG. 6D and FIG. 5 , the sensor chip 20 further includes a first electrical I/O structure 26 located around the feedback cavity structure 25 , and the first electrical I/O structure 26 has a plurality of first electrical I/O structures 26 . A connecting pad 28 is electrically connected to the sensing circuit 12 through the conductive pillars 27 ′ formed by the partial semiconductor bodies 21 , and the shielding chip 30 further includes a second electrical I/O structure 36 located in the open working cavity 35 Around and on the first electrical I/O structure 26 , the second electrical I/O structure 36 has a plurality of second connection pads 38 , which are electrically connected to the first connection pads 28 , respectively.
图7显示依据本发明第三实施例的微型回馈腔传感器100”的局部剖视图。如图7所示,本实施例类似于第二实施例,不同点在于有两个微型回馈腔传感器被整合在一起。因此,半导体基底10更具有一第二感测电路12A,感测元芯片20更具有至少一第二感测元结构23A,半导体本体21中形成有多个第二导电柱27A及27A',至少一第二感测元结构23A、半导体基底10与半导体本体21之间形成一第二回馈腔体结构25A。值得注意的是,第二感测元结构23A的第一电极板也可以是有孔洞H的,而不是密闭的,这样在第一电极板231A与第二电极板232A中间的绝缘层(譬如是氧化层,当作牺牲层)才能被去除。此外,至少一第二感测元结构23A是通过此些第二导电柱27A以电连接至第二感测电路12A,其中第二导电柱27A为整个第二导电路径29A的一部分。再者,第一连接垫28通过此些部分半导体本体21所形成的第二导电柱27A',以电连接至感测电路12,其中导电柱27A'为整个第二导电路径29'的一部分。通过此结构,至少一第二感测元结构23A与第二回馈腔体结构25A共同反应一外界输入的第二物理信号而产生一第二感测信号输出至第二感测电路12A。7 shows a partial cross-sectional view of a micro feedback cavity sensor 100 ″ according to a third embodiment of the present invention. As shown in FIG. 7 , this embodiment is similar to the second embodiment, except that two micro feedback cavity sensors are integrated in the Therefore, the semiconductor substrate 10 further has a second sensing circuit 12A, the sensing element chip 20 further has at least one second sensing element structure 23A, and a plurality of second conductive pillars 27A and 27A' are formed in the semiconductor body 21 , a second feedback cavity structure 25A is formed between at least one second sensing element structure 23A, the semiconductor substrate 10 and the semiconductor body 21. It should be noted that the first electrode plate of the second sensing element structure 23A can also be There are holes H, not closed, so that the insulating layer (such as an oxide layer, as a sacrificial layer) between the first electrode plate 231A and the second electrode plate 232A can be removed. In addition, at least one second sensing The meta structure 23A is electrically connected to the second sensing circuit 12A through the second conductive pillars 27A, wherein the second conductive pillars 27A are part of the entire second conductive path 29A. Furthermore, the first connection pads 28 pass through these second conductive pillars 27A. The second conductive column 27A' formed by part of the semiconductor body 21 is electrically connected to the sensing circuit 12, wherein the conductive column 27A' is a part of the entire second conductive path 29'. Through this structure, at least one second sensing element The structure 23A and the second feedback cavity structure 25A jointly respond to a second physical signal input from the outside to generate a second sensing signal and output it to the second sensing circuit 12A.
图8A与图8B显示依据本发明各实施例的微型回馈腔传感器的感测元结构的另一个例子的局部剖视图及俯视示意图。如图8A与图8B所示,感测元结构23'为一悬浮结构,用于感测一物理信号而变形,悬浮结构包括一第一电极板231,一压电材料层234以及一第二电极板232。第一电极板231设置于半导体本体21上。压电材料层234设置于第一电极板231上。第二电极板232设置于压电材料层234上,压电材料层234变形以产生感测信号。第二电极板232上开设有凹槽236,以提供变形的能力。8A and 8B show a partial cross-sectional view and a schematic top view of another example of the sensing element structure of the micro feedback cavity sensor according to various embodiments of the present invention. As shown in FIG. 8A and FIG. 8B , the sensing element structure 23 ′ is a floating structure for sensing a physical signal and deformed. The floating structure includes a first electrode plate 231 , a piezoelectric material layer 234 and a second electrode plate 231 . Electrode plate 232 . The first electrode plate 231 is disposed on the semiconductor body 21 . The piezoelectric material layer 234 is disposed on the first electrode plate 231 . The second electrode plate 232 is disposed on the piezoelectric material layer 234, and the piezoelectric material layer 234 is deformed to generate a sensing signal. Grooves 236 are formed on the second electrode plate 232 to provide deformation capability.
图9显示依据本发明各实施例的微型回馈腔传感器的半导体基底10'的另一个例子的局部剖视图。如图9所示,半导体基底10'包括一第一硅基板11、一模塑料层13以及一导体连接层14。第一硅基板11具有感测电路12。模塑料层13包围第一硅基板11的一个或多个侧面15。导体连接层14位于第一硅基板11及模塑料层13上,并将感测电路12电连接至感测元芯片20。此实施例的优点在于半导体基底10'的体积很小,但是可以通过扇出的方式来加大回馈腔体结构25的腔体容积。FIG. 9 shows a partial cross-sectional view of another example of the semiconductor substrate 10 ′ of the micro feedback cavity sensor according to various embodiments of the present invention. As shown in FIG. 9 , the semiconductor substrate 10 ′ includes a first silicon substrate 11 , a molding compound layer 13 and a conductor connection layer 14 . The first silicon substrate 11 has a sensing circuit 12 . The molding compound layer 13 surrounds one or more side surfaces 15 of the first silicon substrate 11 . The conductor connection layer 14 is located on the first silicon substrate 11 and the molding compound layer 13 , and electrically connects the sensing circuit 12 to the sensing element chip 20 . The advantage of this embodiment is that the volume of the semiconductor substrate 10 ′ is small, but the cavity volume of the feedback cavity structure 25 can be enlarged by means of fan-out.
图10显示依据本发明第四实施例的微型回馈腔传感器100C的局部剖视图。如图10所示,本实施例类似于第一实施例,不同点在于遮蔽芯片30包括一整合式导体层80,所述整合式导体层位于半导体本体31上,更贯穿半导体本体31及感测元芯片20的一部分,而电连接至感测元芯片20的一电性输出入结构26,以电连接至感测电路12。即,外露导体层37与导体连接层262整体连接在一起构成整合式导体层80,可以是相同或不同的的导体材料所形成。故导体连接层262与外露导体层37可被视为是整合式导体层80的一部分,使得整合式导体层80除了外露于半导体本体31上以外,还更进一步贯穿半导体本体31、绝缘层73B、73A、73、72而直接连接导体连接层262,而进一步连接至第一电性输出入结构26的导电柱27'。外露导体层37也构成开放工作腔35的部分边界,也具有遮蔽杂讯干扰的效果。微型回馈腔传感器100C还包括一电路板50,设置于遮蔽芯片30的上方,并电连接至遮蔽芯片30上的多个连接垫28,其中物理信号是通过电路板50与此些连接垫28之间的空隙进入开放工作腔35,当然也可以从对应于开放工作腔35的电路板50的开口50C进入。微型回馈腔传感器100C可以还包括一电路板50,设置于遮蔽芯片30的上方,并电连接至遮蔽芯片30上的多个连接垫28,其中物理信号是通过电路板50与此些连接垫28之间的空隙进入开放工作腔35。FIG. 10 shows a partial cross-sectional view of a micro feedback cavity sensor 100C according to a fourth embodiment of the present invention. As shown in FIG. 10 , this embodiment is similar to the first embodiment, except that the shielding chip 30 includes an integrated conductor layer 80 , the integrated conductor layer is located on the semiconductor body 31 and further penetrates the semiconductor body 31 and the sensing A part of the meta-chip 20 is electrically connected to an electrical I/O structure 26 of the sensing meta-chip 20 so as to be electrically connected to the sensing circuit 12 . That is, the exposed conductor layer 37 and the conductor connection layer 262 are integrally connected together to form the integrated conductor layer 80, which may be formed of the same or different conductor materials. Therefore, the conductor connection layer 262 and the exposed conductor layer 37 can be regarded as a part of the integrated conductor layer 80 , so that the integrated conductor layer 80 is not only exposed on the semiconductor body 31 , but also further penetrates through the semiconductor body 31 , the insulating layer 73B, 73A, 73, 72 are directly connected to the conductor connection layer 262, and further connected to the conductive pillars 27' of the first electrical I/O structure 26. The exposed conductor layer 37 also forms part of the boundary of the open working cavity 35, and also has the effect of shielding noise interference. The micro feedback cavity sensor 100C further includes a circuit board 50 disposed above the shielding chip 30 and electrically connected to a plurality of connection pads 28 on the shielding chip 30 , wherein physical signals pass through the circuit board 50 and the connection pads 28 . The gap between the open working cavity 35 and the opening 50C of the circuit board 50 corresponding to the open working cavity 35 can also be entered. The micro feedback cavity sensor 100C may further include a circuit board 50 disposed above the shielding chip 30 and electrically connected to a plurality of connection pads 28 on the shielding chip 30 , wherein physical signals are connected to the connection pads 28 through the circuit board 50 . The gap between them enters the open working chamber 35 .
图11A至图12F显示依据本发明第四实施例的微型回馈腔传感器的制造方法的各步骤的局部剖视图。本实施例的制造方法类似于第一实施例,所以类似的制造工艺所使用的材料及特性可以应用至所有实施例。FIGS. 11A to 12F are partial cross-sectional views showing various steps of a manufacturing method of a micro feedback cavity sensor according to a fourth embodiment of the present invention. The manufacturing method of this embodiment is similar to that of the first embodiment, so the materials and characteristics used in the similar manufacturing process can be applied to all the embodiments.
如图11A所示,提供低阻值(譬如<0.01欧姆-公分)的半导体基板301,称为第一哑晶圆(dummy wafer),并在半导体基板301上形成一个图案化的绝缘层302(第一绝缘层),譬如是热氧化物(thermal oxide),当然也可结合另一刻蚀抑止层,例如氮化物等等,其中配合一道遮罩当作刻蚀抑止层,使用第一道光罩执行光刻以移除第一绝缘层。As shown in FIG. 11A , a semiconductor substrate 301 with a low resistance value (eg, <0.01 ohm-cm) is provided, which is called a first dummy wafer, and a patterned insulating layer 302 ( The first insulating layer), such as thermal oxide (thermal oxide), of course, can also be combined with another etch stop layer, such as nitride, etc., in which a mask is used as the etch stop layer, and the first mask is used Photolithography is performed to remove the first insulating layer.
如图11B所示,在半导体基板301以及绝缘层302上形成一个图案化的第一电极板层303,其具有多个凹槽304。譬如使用第一道LPCVD(低压化学气相沉积)形成N型低阻值(譬如<0.01欧姆-公分)的多晶硅,最好是制成过程杂质掺杂提高其导电性,以作为薄膜材料。同时也可以进一步在摄氏1000度以上进行退火(annealing)以将应力稳定化,其中使用第二道遮罩进行光刻以移除一部分的第一多晶硅(303)。As shown in FIG. 11B , a patterned first electrode plate layer 303 having a plurality of grooves 304 is formed on the semiconductor substrate 301 and the insulating layer 302 . For example, using the first LPCVD (Low Pressure Chemical Vapor Deposition) to form N-type polysilicon with low resistance (eg <0.01 ohm-cm), it is best to use impurity doping during the manufacturing process to improve its conductivity as a thin film material. At the same time, annealing may be further performed above 1000 degrees Celsius to stabilize the stress, wherein a second mask is used for photolithography to remove a portion of the first polysilicon (303).
如图11C所示,在第一电极板层303及凹槽304上形成一个图案化的绝缘层305,绝缘层305具有多个凹槽306以露出部分的第一电极板层303。绝缘层305为第二绝缘层,材料可以是氧化物,当作牺牲层,厚度小于2微米,可能需要化学机械抛光(CMP)以将氧化层的表面平坦化。接着,使用第三道遮罩进行光刻以移除部分氧化层面,其中可加上一道遮罩来供波纹或凹处(dimple)使用,以提供抗静电沾粘的目的(anti-stiction purpose)。图11A至图11C可以与图2A至2C相同。As shown in FIG. 11C , a patterned insulating layer 305 is formed on the first electrode plate layer 303 and the grooves 304 . The insulating layer 305 has a plurality of grooves 306 to expose part of the first electrode plate layer 303 . The insulating layer 305 is the second insulating layer, and the material can be oxide, as a sacrificial layer, the thickness is less than 2 microns, and chemical mechanical polishing (CMP) may be required to planarize the surface of the oxide layer. Then, a third mask is used for photolithography to remove part of the oxide layer, and a mask can be added for the use of ripples or dimples to provide anti-stiction purposes. . FIGS. 11A to 11C may be the same as FIGS. 2A to 2C .
如图11D所示,在绝缘层305与第一电极板层303上形成一个图案化的第二电极板层307,填满凹槽306。即,利用第二道LPCVD形成N型低阻值(譬如<0.01欧姆-公分)的多晶硅,当作背板(back-plate),制造参数可以类似第一电极板层,包括在摄氏1000度以上进行退火(annealing)以将应力稳定化,其中使用第四道遮罩进行光刻以移除一部分的第二多晶硅(307)。As shown in FIG. 11D , a patterned second electrode plate layer 307 is formed on the insulating layer 305 and the first electrode plate layer 303 to fill the groove 306 . That is, using the second pass LPCVD to form N-type low-resistance (eg <0.01 ohm-cm) polysilicon, as a back-plate, the manufacturing parameters can be similar to the first electrode plate layer, including above 1000 degrees Celsius An annealing is performed to stabilize the stress, wherein photolithography is performed using a fourth mask to remove a portion of the second polysilicon (307).
如图11E所示,在第二电极板层307及露出的绝缘层305上形成绝缘层73,称为第三绝缘层,其材料是氧化物,当作另一牺牲层,可能需要CMP以将氧化层的表面平坦化。接着,在绝缘层73上形成绝缘层73A,称为第四绝缘层,材料可以是氮化物,也可以是氧化铝、碳化硅,类碳钻膜等等,当作刻蚀抑止层。然后,在绝缘层73A上形成绝缘层73B,称为第五绝缘层,其材料可以是氧化物,用来作熔接(fusion bonding)用,可能需要CMP以将氧化层的表面平坦化。并且,上述绝缘层,甚或电极板层,也可以不是单一材料,更可以包括复合层材料,例如绝缘层可以是氧化硅、氮化硅、氧化铝、碳化硅(SiC)、类碳钻膜(Diamond likecarbon)等等单一层或组合层,而电极板层在本实施例为多晶硅,当然也可以是与上述绝缘层材料组合而成的复合结构,例如绝缘层/多晶硅/绝缘层。As shown in FIG. 11E, an insulating layer 73, called a third insulating layer, is formed on the second electrode plate layer 307 and the exposed insulating layer 305, and its material is oxide. As another sacrificial layer, CMP may be required to remove the The surface of the oxide layer is flattened. Next, an insulating layer 73A, called the fourth insulating layer, is formed on the insulating layer 73, and the material may be nitride, or aluminum oxide, silicon carbide, diamond-like carbon film, etc., as an etching stopper layer. Then, an insulating layer 73B, called the fifth insulating layer, is formed on the insulating layer 73A, and its material may be an oxide for fusion bonding, and CMP may be required to planarize the surface of the oxide layer. In addition, the above-mentioned insulating layer, or even the electrode plate layer, may not be a single material, but may include a composite layer material, for example, the insulating layer may be silicon oxide, silicon nitride, aluminum oxide, silicon carbide (SiC), carbon diamond-like film ( Diamond like carbon) and other single layer or combined layer, and the electrode plate layer is polysilicon in this embodiment, of course, it can also be a composite structure combined with the above insulating layer materials, such as insulating layer/polysilicon/insulating layer.
如图11F所示,将半导体本体31(又称为第二哑晶圆,规格可与第一哑晶圆相同)熔接至绝缘层73B,在本实施例中两者是通过低温接合方式(low temperature fusionbonding)形成具有氢键强度的接口。当然在形成低温接合之前,更可以包括水清洗及例如低浓度氢氟酸以去除半导体基板400表面的氧化层(HF dip),为了达到表面活化,更可以包括表面电浆(plasma)处理,例如暴露在氧气(O2)及氮气(N2)的电浆环境下,而且为了让接合的表面有很好的平坦度,更可以利用化学机械研磨法(CMP)将待接合的表面予以抛光及抛平。并且可以利用高温退火至700度以上以增强接合强度,为了薄型化起见,可以在熔接后将第二哑晶圆磨薄,譬如磨掉假想线所绘制的部分。As shown in FIG. 11F , the semiconductor body 31 (also referred to as the second dummy wafer, and the specifications can be the same as the first dummy wafer) are welded to the insulating layer 73B. temperature fusion bonding) to form an interface with hydrogen bonding strength. Of course, before forming the low-temperature bonding, water cleaning and, for example, low-concentration hydrofluoric acid may be included to remove the oxide layer (HF dip) on the surface of the semiconductor substrate 400. In order to achieve surface activation, surface plasma treatment may be included, such as It is exposed to the plasma environment of oxygen (O 2 ) and nitrogen (N 2 ), and in order to make the joint surface have a good flatness, chemical mechanical polishing (CMP) can be used to polish the surface to be joined and Flatten. In addition, high temperature annealing can be used to increase the bonding strength to above 700 degrees. For the purpose of thinning, the second dummy wafer can be thinned after welding, for example, the part drawn by the imaginary line is ground off.
如图11G所示,形成沟槽39,其贯穿半导体本体31、以及绝缘层73B、73A及73,以露出与第二电极板层37属于同一层的多晶硅。可以使用第五道遮罩(譬如使用氧化物来当作硬式遮罩)来进行光刻,使用的是硅的深刻蚀技术,自对准地刻蚀氧化物/氮化物/氧化物。As shown in FIG. 11G , a trench 39 is formed, which penetrates the semiconductor body 31 and the insulating layers 73B, 73A and 73 to expose the polysilicon belonging to the same layer as the second electrode plate layer 37 . Photolithography can be performed using a fifth mask (eg, using oxide as a hard mask), using a silicon deep etch technique to etch oxide/nitride/oxide in a self-aligned manner.
如图11H所示,在沟槽39中及半导体本体31上形成外露导体层37,可称为第三多晶硅,但本发明当然不限于此,其他导体材料包刮金属材料也可以。可以是用多晶硅沉积技术,与第一第二多晶硅沉积的条件可相同或不同。As shown in FIG. 11H , an exposed conductor layer 37 is formed in the trench 39 and on the semiconductor body 31 , which may be called the third polysilicon, but of course the invention is not limited to this, and other conductor materials may also be covered with metal materials. The polysilicon deposition technique may be used, and the conditions for the first and second polysilicon deposition may be the same or different.
如图12A所示,在半导体基板301的背面形成第二接合结构42。譬如,可先将半导体基板301磨薄至大约400微米,然后在半导体基板301的背面形成第二接合结构42。第一接合结构41与第二接合结构42的材料可以是选自于铝、铜、锗、金、锡、铟、硅等等所组成的群组。举例而言,第一接合结构41的材料为铝,而第二接合结构42的材料为锗,其中铝和锗可以在约420℃形成共晶接合(eutectic bonding),并且这两种材料与CMOS制造工艺相容,更适合应用于本实施例具有集成电路整合的设计。另外有种情况,第二接合结构42是不存在的,半导体本体21的硅材料本身就可以是第二接合结构42的材料,而此时第一接合结构41可以是金(Au)。在此半导体基板301的背面沉积譬如锗(Ge)的金属层,接着利用第六道遮罩来对Ge层施以光刻而图案化。As shown in FIG. 12A , the second bonding structure 42 is formed on the back surface of the semiconductor substrate 301 . For example, the semiconductor substrate 301 may be thinned to about 400 microns first, and then the second bonding structure 42 may be formed on the backside of the semiconductor substrate 301 . The materials of the first bonding structure 41 and the second bonding structure 42 may be selected from the group consisting of aluminum, copper, germanium, gold, tin, indium, silicon, and the like. For example, the material of the first bonding structure 41 is aluminum, and the material of the second bonding structure 42 is germanium, wherein aluminum and germanium can form eutectic bonding at about 420° C., and these two materials are compatible with CMOS The manufacturing process is compatible, and it is more suitable for the design with integrated circuit integration in this embodiment. In another case, the second bonding structure 42 does not exist, the silicon material of the semiconductor body 21 itself may be the material of the second bonding structure 42, and the first bonding structure 41 may be gold (Au). A metal layer such as germanium (Ge) is deposited on the backside of the semiconductor substrate 301 , and then the Ge layer is patterned by photolithography using a sixth mask.
如图12B所示,使用第七道遮罩(也可使用氧化物沉积层当作硬式遮罩)来进行硅的深刻蚀达到譬如400微米,以形成多个沟槽。As shown in FIG. 12B, a seventh mask (the oxide deposition layer can also be used as a hard mask) is used to deeply etch the silicon up to, for example, 400 microns to form a plurality of trenches.
如图12C所示,移除部分的绝缘层302与305(牺牲层),以露出第一电极板231及形成间隙235及235'。操作时,可以使用缓冲氧化物刻蚀剂(BOE)或蒸汽氢氟酸(Vapor HF)。As shown in FIG. 12C , parts of the insulating layers 302 and 305 (sacrificial layers) are removed to expose the first electrode plate 231 and form gaps 235 and 235 ′. In operation, buffered oxide etchant (BOE) or vapor hydrofluoric acid (Vapor HF) can be used.
如图12D所示,将图12C的结构接合至半导体基底10,半导体基底10上已经形成有第一接合结构41及感测电路12,其与第二接合结构42共晶接合在一起,以形成回馈腔体结构25。半导体基底10譬如是属于麦克风晶圆的一部分。然后,在外露导体层37上形成多个第一连接垫28。可先在外露导体层37上形成一金属层,然后使用第八道遮罩来进行光刻,也可加上一道遮罩以供焊接遮罩使用。As shown in FIG. 12D , the structure of FIG. 12C is bonded to the semiconductor substrate 10 on which the first bonding structure 41 and the sensing circuit 12 have been formed, which are eutectic bonded with the second bonding structure 42 to form Feedback cavity structure 25 . The semiconductor substrate 10 is, for example, part of a microphone wafer. Then, a plurality of first connection pads 28 are formed on the exposed conductor layer 37 . A metal layer can be formed on the exposed conductor layer 37 first, and then an eighth mask can be used for photolithography, or a mask can be added for a solder mask.
如图12E所示,形成开放工作腔35,其贯通外露导体层37、半导体本体31以及绝缘层73B、73A和73,并与图12C的间隙235'结合成一体。制作时,可以使用第九道遮罩来进行光刻(可使用氧化物当作硬式遮罩),执行硅的深刻蚀,自对准地刻蚀氧化物/氮化物。As shown in FIG. 12E, an open working cavity 35 is formed, which penetrates the exposed conductor layer 37, the semiconductor body 31 and the insulating layers 73B, 73A and 73, and is integrated with the gap 235' of FIG. 12C. During fabrication, the ninth mask can be used for photolithography (the oxide can be used as a hard mask), a deep etch of silicon is performed, and oxide/nitride is etched in a self-aligned manner.
如图12F所示,可以将晶圆级的产品进行切割及进行焊接,利用锡球当作连接部60,以将第一连接垫28焊接至电路板50,如图10所示。As shown in FIG. 12F , the wafer-level product can be cut and soldered, and the solder balls are used as the connection parts 60 to solder the first connection pads 28 to the circuit board 50 , as shown in FIG. 10 .
图13显示依据本发明第五实施例的微型回馈腔传感器100D的局部剖视图。如图13所示,本实施例类似于第四实施例,不同点在于第一连接垫28设置于半导体基底10的下表面16,通过半导体基底10中形成的连接垫18及导体插塞17电连接至感测电路12。因此,电路板50设置于半导体基底10的下方,并电连接至半导体基底10的下表面16上的多个第一连接垫28。此也为一种可行的方案。值得注意的是,第四与第五实施例的制造方法,更相容于半导体制造工艺,且更适合大量生产。FIG. 13 shows a partial cross-sectional view of the micro feedback cavity sensor 100D according to the fifth embodiment of the present invention. As shown in FIG. 13 , this embodiment is similar to the fourth embodiment, except that the first connection pads 28 are disposed on the lower surface 16 of the semiconductor substrate 10 , and the connection pads 18 and the conductor plugs 17 formed in the semiconductor substrate 10 are electrically connected to each other. Connected to the sensing circuit 12 . Therefore, the circuit board 50 is disposed under the semiconductor substrate 10 and is electrically connected to the plurality of first connection pads 28 on the lower surface 16 of the semiconductor substrate 10 . This is also a feasible solution. It should be noted that the manufacturing methods of the fourth and fifth embodiments are more compatible with the semiconductor manufacturing process and are more suitable for mass production.
通过上述实施例,可以让微型回馈腔传感器当作声波传感器(例如麦克风)、超声波传感器使用,也可以当作压力传感器使用,也可以是同时具有例如麦克风与压力传感器的功能,达到传感器整合的效果。当然也不限定于此,其他可以通过回馈腔体设计达到提升传感器品质的其他类型传感器,例如热感应式(thermal-type),移动式(motion-type)等等传感器也都可以适用于本发明的结构及制造工艺。此外,本发明利用晶圆级的制造技术,可以大量生产,降低成本。再者,本发明的制造方式可以达到大幅加大工作腔(背腔)的体积,降低麦克风的前腔体积,也可以大幅缩小微型回馈腔传感器的尺寸。Through the above embodiments, the micro feedback cavity sensor can be used as a sound wave sensor (such as a microphone), an ultrasonic sensor, or a pressure sensor, or it can have functions such as a microphone and a pressure sensor at the same time, so as to achieve the effect of sensor integration . Of course, it is not limited to this. Other types of sensors that can improve the quality of the sensor through the design of the feedback cavity, such as thermal-type sensors, motion-type sensors, etc., can also be applied to the present invention. structure and manufacturing process. In addition, the present invention utilizes the wafer-level manufacturing technology, which can be mass-produced and reduce the cost. Furthermore, the manufacturing method of the present invention can greatly increase the volume of the working cavity (back cavity), reduce the volume of the front cavity of the microphone, and can also greatly reduce the size of the micro feedback cavity sensor.
在较佳实施例的详细说明中所提出的具体实施例仅方便说明本发明的技术内容,而非将本发明狭义地限制在上述实施例,在不超出本发明的精神及以下申请专利范围的情况,所做的种种变化实施,皆属于本发明的范围。The specific embodiments proposed in the detailed description of the preferred embodiments are only for the convenience of illustrating the technical content of the present invention, rather than limiting the present invention to the above-mentioned embodiments in a narrow sense. Various changes and implementations made under different circumstances all belong to the scope of the present invention.
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